From nobody Sat Oct 4 17:33:48 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 909EA28BAAD; Thu, 14 Aug 2025 22:40:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211244; cv=none; b=JlgE0tZ/FyJ4QQniNDA75vz65VHC9czAkItDbNM8df2wRmvRd3zRZEsRiG+4+S97zBWyy+g/5kivyZ88qFNsAAtUcHoKIuH0R2rZHs+SYH3hM8e3kz8PeWfCDby3xqe4SetKfDEGAFmRsKijPkheUkGEdW85swRYzGuNK2cPU04= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211244; c=relaxed/simple; bh=KA/neKNeMQAV5K8Bftcu1FZYImxxRN+GNVxVD2kc3HY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ge+SLOKAKr0Sd8zw/7zhRCpBtTVJBwbXr3tkXug6NHZunVUIyNDVNTNQ3LOTTGk+4qgT5BA5UNLFb9QVDstCabgFE3fGZ2VCENX1QTPO/e2yXTQy0iUhnCPWm8HVYPous2kvnzzVXonjlt7lJVAWEca2wDX4IVHSx7/c4oV4AL4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=MfpGZGHx; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="MfpGZGHx" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMecDw2479141; Thu, 14 Aug 2025 17:40:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211238; bh=/D4CdjzbKBEn0QnVJ7EwHxslGo5HUAf6Sfwsue7wEU4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MfpGZGHxLKcO393R0VmPpZOaF9c+3VnfO/x3URRzldF1wQsD3vv70nlfgiyjuk8n2 XQ5F2sdJTM+F069y1PVjt1LqBApyyPxAEm0qPOBI24fpqrHJkMcA1onCBRTqqgzcnT H6mMrqX6Iiuz+eysB0ZaGHDwO8wWsttSyMAx8o40= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMecgE2016217 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:40:38 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:40:38 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:40:37 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw4u096792; Thu, 14 Aug 2025 17:40:34 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH 21/33] arm64: dts: ti: k3-am62: Enable remote processors at board level Date: Fri, 15 Aug 2025 04:08:27 +0530 Message-ID: <20250814223839.3256046-22-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM62x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index 10e6b5c08619..dcd22ff487ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -407,4 +407,5 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi index 6549b7efa656..75aed3a88284 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -128,6 +128,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <121>; ti,sci-proc-ids =3D <0x01 0xff>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 43ee16f171fd..03b8e246d8c2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -506,6 +506,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &usbss0 { --=20 2.34.1