From nobody Sat Oct 4 17:33:48 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50F6028C5DB; Thu, 14 Aug 2025 22:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211240; cv=none; b=ikMCwMBlNwSbW+irI8MIjuzigADssbG0EdupTIvRzYW/Ey6NOuti/24Mx4C4M04InaJtuDjGqbMr3l+xuR2MiMXm8XT4kEaK5XCqTEXCo68C6KiYsTdgvxaHxm2XlTo1CI0TIe4XU7ut8zm7Jhwg6T2tP7vfty4uKK6F0rgxKos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211240; c=relaxed/simple; bh=WSUzH9TLTmZYdoZaROuv8TqUj+x9oeak6qBd2ccDU0M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R3fP1oBJo1CTg5Dg/oRB/Cb5Gr2Y+HK3xsFNzu/J8bGQnDg2mXGFOe+NOwVEbjp8xtr9Annf9kGCdu9AroiZbDPmJ9BAKSIKrbPS4CKGASTZqwkoIU5Io7WF4iHXYNxqva6DdUlNPgB1c6DA4KtbVbnVtDc5PKH90HAv/oxbJ+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=dTUi79Fg; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dTUi79Fg" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMeYwg2027524; Thu, 14 Aug 2025 17:40:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211234; bh=AB4vrIyN7/UllKdjb7dZzYMxIu0/eesKD4yJVe6j0hc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dTUi79FgwfB3yE5lY9GkSiTzFMDf/IBmNq+bzUG4xI0y7FUQCQfI6op8a+M60kCuP XWAdPMTFLCKA1mvfDBT7EdJQQ5QIVjgCgqnB7bCkXEtRKDYPhh/etHlo8KJdAmw+xu QBb7MZrfT1oEW/BrIxaGUUKVWiHGrvGGkV0g7Ojw= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMeYFK2150405 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:40:34 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:40:33 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:40:33 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw4t096792; Thu, 14 Aug 2025 17:40:30 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH 20/33] arm64: dts: ti: k3-am62: Enable Mailbox nodes at the board level Date: Fri, 15 Aug 2025 04:08:26 +0530 Message-ID: <20250814223839.3256046-21-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Mailbox nodes defined in the top-level AM62x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts | 1 + arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 029380dc1a35..40fb3c9e674c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -808,6 +808,7 @@ mailbox0_cluster0: mailbox@29000000 { #mbox-cells =3D <1>; ti,mbox-num-users =3D <4>; ti,mbox-num-fifos =3D <16>; + status =3D "disabled"; }; =20 ecap0: pwm@23100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/= boot/dts/ti/k3-am62-pocketbeagle2.dts index df2e1b0e74a1..2140e0cdec85 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -299,6 +299,7 @@ &epwm2 { }; =20 &mailbox0_cluster0 { + status =3D "okay"; mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index fba6f5c8d099..1c44d17281dd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -1335,6 +1335,7 @@ &main_i2c3 { }; =20 &mailbox0_cluster0 { + status =3D "okay"; mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; --=20 2.34.1