From nobody Sat Oct 4 17:33:47 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81B4928BAAD; Thu, 14 Aug 2025 22:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211239; cv=none; b=hfkHa7F7Ev4W503j4y9oTQEHOt4xHGltwvz2b/DMVlawuqfzmvS/sDB81ZXo7FXlK5NGDmyZcMKXIUuMJOn2hJx3FgoxGbcb/SI1N2vbAHbbDYcZhFjqZ1Rngguf2unEWI4vOYaIVgT37qXOsF7L+AkdzBYGikeKio9KwWoeP54= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211239; c=relaxed/simple; bh=H5WnNP6QlZs51eHYok11EmojT/YiCZqGcDTghMDGkSY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=crtBdRnWclCcCNYWLck52pw9Yckr/wJyLaooo2om2ZzsvtxA1SdTDKyfQ84TLxI+3IGrsIna2K1TaxFaOY81BqljD5HwASBlIVjB2lKpmUpOz01SiJ5UuX9Ba5JDThJ9VbSKsBirmreeN7SxF2F7P6nanoQQW29lbgKcZuGajfE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ersKHQuP; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ersKHQuP" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMePBA1973416; Thu, 14 Aug 2025 17:40:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211225; bh=WuVDHbbeIgZW6SyeBHuy1J7cw3hZ9x/jabkROnNfXlI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ersKHQuPLUgYHD1TFIP6LJ7aogoKBSD5Yw0EwubKQAeSQHMagKK+IMbl6ARdyKNBc +1YQyzj116SMOO0/M5L/qLEybIZJzBTXn342+z+7J04VcXjAIYNXOaMWlj565eEkRp 7NUghwPBBGeBdSmHZViQrXz4mAax9wcFs6mVTH9o= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMePrg1462066 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:40:25 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:40:25 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:40:25 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw4r096792; Thu, 14 Aug 2025 17:40:20 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Francesco Dolcini , Hiago De Franco , Jo_o Paulo Gon_alves , Stefan Eichenberger , Max Krummenacher , Andrejs Cainikovs Subject: [PATCH 18/33] arm64: dts: ti: k3-am62-verdin: Add missing cfg for TI IPC Firmware Date: Fri, 15 Aug 2025 04:08:24 +0530 Message-ID: <20250814223839.3256046-19-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62-verdin.dtsi file. Correct the firmware memory region label. Currently, only mailbox node is enabled with FIFO assignment for a single M4F remote core. However, there are no users of the enabled mailboxes. Add the missing carveouts for WKUP R5F and MCU M4F remote processors, and enable those by associating to the above carveout and mailboxes. This config aligns with other AM62 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Hiago De Franco # Verdin AM62 --- Cc: Francesco Dolcini Cc: Hiago De Franco Cc: Jo_o Paulo Gon_alves Cc: Stefan Eichenberger Cc: Max Krummenacher Cc: Andrejs Cainikovs Requesting for review/test of this patch arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 43 +++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index 4e9a8921c95d..fba6f5c8d099 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -206,7 +206,25 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -1321,6 +1339,29 @@ mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 /* Verdin CAN_1 */ --=20 2.34.1