From nobody Sat Oct 4 17:33:50 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32778287243; Thu, 14 Aug 2025 22:39:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211199; cv=none; b=UyIuVnFwf5BjGs8JV0FCTcS/YpgoptA0pgZgs1UWxDlXRbXxH6n25tXQA0sipQoSK2ocoXC1cJrTe1eU0p4SFV3JHVEXGinqmQaUeZ8KWuq/eCE6T5po19keNS5qIGzSvd5JBdSfFJXRy98MCcgjnLllS9tk6tmy4A6/gctiDBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211199; c=relaxed/simple; bh=6OOGpF7W1sWa7nPzYl9Mk7s7V+SmAz2yErF+tbK7vFM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Uy2rjXEmFpoYGloeCpt8fzP+rR7w0Y4+astLwr6nK7JLKXkyCZfJlOGZ/TPimsr89sSayPp5sGLtJEugbj7KNN0sterrQOVvC3i356x9Oz7tGbN/0vvpcT5v1xtDlDPJ7U16ZUQUlulfA+Nf0fzfov4S7uzhoN/yof5yp5fTleU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=n4J/2s91; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="n4J/2s91" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMdjIa1973329; Thu, 14 Aug 2025 17:39:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211185; bh=OvV72ojHrNTFCLxl+4trll6FpOg9kL833dLth/2eHPQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=n4J/2s91vfzlSwQOlDlQZOWY90XLWhbesotAdYHKa69WkeOaiSEDGRq2lOmKow2Qa E5x//fg4ZXCbxGoLhwlyTVaYAVYHgNp87dZkYRIx7UqLKvGZQouoxe/tUJDbQ2F1Lr 0JJFP1wEWxb66knNWgNqTcbFpRSOThtFh14Chr54= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMdjPu2015657 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:39:45 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:39:45 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:39:45 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw4i096792; Thu, 14 Aug 2025 17:39:41 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH 09/33] arm64: dts: ti: k3-j721s2-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Fri, 15 Aug 2025 04:08:15 +0530 Message-ID: <20250814223839.3256046-10-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 J721S2 SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J721S2 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi --- .../boot/dts/ti/k3-am68-phycore-som.dtsi | 247 +---------------- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 241 +---------------- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 243 +---------------- .../dts/ti/k3-j721s2-ti-ipc-firmware.dtsi | 249 ++++++++++++++++++ 4 files changed, 254 insertions(+), 726 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am68-phycore-som.dtsi index 383594732e81..21fe9083c19c 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -60,96 +60,6 @@ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg =3D <0x00 0xa8000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vdd_sd_dv: regulator-sd { @@ -243,80 +153,6 @@ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27)= WKUP_I2C0_SDA */ }; }; =20 -&c71_0 { - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; - status =3D "okay"; -}; - -&c71_1 { - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; - status =3D "okay"; -}; - -&mailbox0_cluster0 { - interrupts =3D <436>; - status =3D "okay"; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts =3D <432>; - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - interrupts =3D <428>; - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - interrupts =3D <420>; - status =3D "okay"; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - &main_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&rgmii1_pins_default>; @@ -367,34 +203,6 @@ &main_gpio0 { status =3D "okay"; }; =20 -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - /* eMMC */ &main_sdhci0 { non-removable; @@ -409,59 +217,6 @@ &main_sdhci1 { bootph-all; }; =20 -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer3 { - status =3D "reserved"; -}; - -&main_timer4 { - status =3D "reserved"; -}; - -&main_timer5 { - status =3D "reserved"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; @@ -611,3 +366,5 @@ som_eeprom_opt: eeprom@51 { pagesize =3D <32>; }; }; + +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index 2d2edeeb7347..4b14fb1062bd 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -38,96 +38,6 @@ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg =3D <0x00 0xa8000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; }; =20 @@ -235,153 +145,4 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer3 { - status =3D "reserved"; -}; - -&main_timer4 { - status =3D "reserved"; -}; - -&main_timer5 { - status =3D "reserved"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index f252007262d3..d4d996b985ae 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -42,96 +42,6 @@ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg =3D <0x00 0xa8000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 mux0: mux-controller-0 { @@ -516,157 +426,6 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer3 { - status =3D "reserved"; -}; - -&main_timer4 { - status =3D "reserved"; -}; - -&main_timer5 { - status =3D "reserved"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - &main_i2c4 { bridge_dsi_edp: bridge-dsi-edp@2c { compatible =3D "ti,sn65dsi86"; @@ -693,3 +452,5 @@ port@1 { }; }; }; + +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi b/arch/a= rm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..40c9f2b64e7e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J721S2 SoCs + * + * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg =3D <0x00 0xa8000000 0x00 0x01c00000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + interrupts =3D <428>; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status =3D "okay"; + interrupts =3D <420>; + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status =3D "reserved"; +}; + +&main_timer1 { + status =3D "reserved"; +}; + +&main_timer2 { + status =3D "reserved"; +}; + +&main_timer3 { + status =3D "reserved"; +}; + +&main_timer4 { + status =3D "reserved"; +}; + +&main_timer5 { + status =3D "reserved"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0 { + ti,cluster-mode =3D <0>; + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + ti,cluster-mode =3D <0>; + status =3D "okay"; +}; + +&main_r5fss1_core0 { + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region =3D <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1_core1 { + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region =3D <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; + status =3D "okay"; +}; + +&c71_0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; + memory-region =3D <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; + memory-region =3D <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; --=20 2.34.1