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Thu, 14 Aug 2025 08:56:28 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 5/6] RISC-V: KVM: Implement ONE_REG interface for SBI FWFT state Date: Thu, 14 Aug 2025 21:25:47 +0530 Message-ID: <20250814155548.457172-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814155548.457172-1-apatel@ventanamicro.com> References: <20250814155548.457172-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The KVM user-space needs a way to save/restore the state of SBI FWFT features so implement SBI extension ONE_REG callbacks. Signed-off-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 14 +++ arch/riscv/kvm/vcpu_sbi_fwft.c | 169 +++++++++++++++++++++++++++--- 2 files changed, 171 insertions(+), 12 deletions(-) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index a5ca0f4ce2d3..fc5624e89c7b 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -215,6 +215,17 @@ struct kvm_riscv_sbi_sta { unsigned long shmem_hi; }; =20 +struct kvm_riscv_sbi_fwft_feature { + unsigned long flags; + unsigned long value; +}; + +/* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_sbi_fwft { + struct kvm_riscv_sbi_fwft_feature misaligned_deleg; + struct kvm_riscv_sbi_fwft_feature pointer_masking; +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -298,6 +309,9 @@ struct kvm_riscv_sbi_sta { #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_SBI_STA_REG(name) \ (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_SBI_FWFT (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_SBI_FWFT_REG(name) \ + (offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long)) =20 /* Device Control API: RISC-V AIA */ #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 5a3bad0f9330..0d740e7c5713 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -22,6 +22,11 @@ struct kvm_sbi_fwft_feature { */ enum sbi_fwft_feature_t id; =20 + /** + * @flags_reg_num: ONE_REG index of the feature flag + */ + unsigned long flags_reg_num; + /** * @supported: Check if the feature is supported on the vcpu * @@ -44,7 +49,8 @@ struct kvm_sbi_fwft_feature { * * This callback is mandatory */ - long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long value); + long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value); =20 /** * @get: Get the feature current value @@ -53,7 +59,8 @@ struct kvm_sbi_fwft_feature { * * This callback is mandatory */ - long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long *value); + long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value); }; =20 static const enum sbi_fwft_feature_t kvm_fwft_defined_features[] =3D { @@ -91,16 +98,18 @@ static void kvm_sbi_fwft_reset_misaligned_delegation(st= ruct kvm_vcpu *vcpu) =20 static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long value) + bool one_reg_access, unsigned long value) { struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 if (value =3D=3D 1) { cfg->hedeleg |=3D MIS_DELEG; - csr_set(CSR_HEDELEG, MIS_DELEG); + if (!one_reg_access) + csr_set(CSR_HEDELEG, MIS_DELEG); } else if (value =3D=3D 0) { cfg->hedeleg &=3D ~MIS_DELEG; - csr_clear(CSR_HEDELEG, MIS_DELEG); + if (!one_reg_access) + csr_clear(CSR_HEDELEG, MIS_DELEG); } else { return SBI_ERR_INVALID_PARAM; } @@ -110,10 +119,11 @@ static long kvm_sbi_fwft_set_misaligned_delegation(st= ruct kvm_vcpu *vcpu, =20 static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long *value) + bool one_reg_access, unsigned long *value) { - *value =3D (csr_read(CSR_HEDELEG) & MIS_DELEG) =3D=3D MIS_DELEG; + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 + *value =3D (cfg->hedeleg & MIS_DELEG) =3D=3D MIS_DELEG; return SBI_SUCCESS; } =20 @@ -145,7 +155,7 @@ static void kvm_sbi_fwft_reset_pointer_masking_pmlen(st= ruct kvm_vcpu *vcpu) =20 static long kvm_sbi_fwft_set_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long value) + bool one_reg_access, unsigned long value) { struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); unsigned long pmm; @@ -167,14 +177,15 @@ static long kvm_sbi_fwft_set_pointer_masking_pmlen(st= ruct kvm_vcpu *vcpu, * update here so that VCPU see's pointer masking mode change * immediately. */ - csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); + if (!one_reg_access) + csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); =20 return SBI_SUCCESS; } =20 static long kvm_sbi_fwft_get_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long *value) + bool one_reg_access, unsigned long *value) { switch (vcpu->arch.cfg.henvcfg & ENVCFG_PMM) { case ENVCFG_PMM_PMLEN_0: @@ -198,6 +209,8 @@ static long kvm_sbi_fwft_get_pointer_masking_pmlen(stru= ct kvm_vcpu *vcpu, static const struct kvm_sbi_fwft_feature features[] =3D { { .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, + .flags_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, misaligned_deleg.= flags) / + sizeof(unsigned long), .supported =3D kvm_sbi_fwft_misaligned_delegation_supported, .reset =3D kvm_sbi_fwft_reset_misaligned_delegation, .set =3D kvm_sbi_fwft_set_misaligned_delegation, @@ -206,6 +219,8 @@ static const struct kvm_sbi_fwft_feature features[] =3D= { #ifndef CONFIG_32BIT { .id =3D SBI_FWFT_POINTER_MASKING_PMLEN, + .flags_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, pointer_masking.f= lags) / + sizeof(unsigned long), .supported =3D kvm_sbi_fwft_pointer_masking_pmlen_supported, .reset =3D kvm_sbi_fwft_reset_pointer_masking_pmlen, .set =3D kvm_sbi_fwft_set_pointer_masking_pmlen, @@ -214,6 +229,21 @@ static const struct kvm_sbi_fwft_feature features[] = =3D { #endif }; =20 +static const struct kvm_sbi_fwft_feature *kvm_sbi_fwft_regnum_to_feature(u= nsigned long reg_num) +{ + const struct kvm_sbi_fwft_feature *feature; + int i; + + for (i =3D 0; i < ARRAY_SIZE(features); i++) { + feature =3D &features[i]; + if (feature->flags_reg_num =3D=3D reg_num || + (feature->flags_reg_num + 1) =3D=3D reg_num) + return feature; + } + + return NULL; +} + static struct kvm_sbi_fwft_config * kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t fea= ture) { @@ -267,7 +297,7 @@ static int kvm_sbi_fwft_set(struct kvm_vcpu *vcpu, u32 = feature, =20 conf->flags =3D flags; =20 - return conf->feature->set(vcpu, conf, value); + return conf->feature->set(vcpu, conf, false, value); } =20 static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsigned long feature, @@ -280,7 +310,7 @@ static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsi= gned long feature, if (ret) return ret; =20 - return conf->feature->get(vcpu, conf, value); + return conf->feature->get(vcpu, conf, false, value); } =20 static int kvm_sbi_ext_fwft_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, @@ -354,6 +384,115 @@ static void kvm_sbi_ext_fwft_reset(struct kvm_vcpu *v= cpu) } } =20 +static unsigned long kvm_sbi_ext_fwft_get_reg_count(struct kvm_vcpu *vcpu) +{ + unsigned long max_reg_count =3D sizeof(struct kvm_riscv_sbi_fwft) / sizeo= f(unsigned long); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long reg, ret =3D 0; + + for (reg =3D 0; reg < max_reg_count; reg++) { + feature =3D kvm_sbi_fwft_regnum_to_feature(reg); + if (!feature) + continue; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + continue; + + ret++; + } + + return ret; +} + +static int kvm_sbi_ext_fwft_get_reg_id(struct kvm_vcpu *vcpu, int index, u= 64 *reg_id) +{ + int reg, max_reg_count =3D sizeof(struct kvm_riscv_sbi_fwft) / sizeof(uns= igned long); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + int idx =3D 0; + + for (reg =3D 0; reg < max_reg_count; reg++) { + feature =3D kvm_sbi_fwft_regnum_to_feature(reg); + if (!feature) + continue; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + continue; + + if (index =3D=3D idx) { + *reg_id =3D KVM_REG_RISCV | + (IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64) | + KVM_REG_RISCV_SBI_STATE | + KVM_REG_RISCV_SBI_FWFT | reg; + return 0; + } + + idx++; + } + + return -ENOENT; +} + +static int kvm_sbi_ext_fwft_get_reg(struct kvm_vcpu *vcpu, unsigned long r= eg_num, + unsigned long reg_size, void *reg_val) +{ + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long *value; + int ret =3D 0; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D reg_val; + + feature =3D kvm_sbi_fwft_regnum_to_feature(reg_num); + if (!feature) + return -ENOENT; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + return -ENOENT; + + if (feature->flags_reg_num =3D=3D reg_num) + *value =3D conf->flags; + else + ret =3D conf->feature->get(vcpu, conf, true, value); + + return sbi_err_map_linux_errno(ret); +} + +static int kvm_sbi_ext_fwft_set_reg(struct kvm_vcpu *vcpu, unsigned long r= eg_num, + unsigned long reg_size, const void *reg_val) +{ + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long value; + int ret =3D 0; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D *(const unsigned long *)reg_val; + + feature =3D kvm_sbi_fwft_regnum_to_feature(reg_num); + if (!feature) + return -ENOENT; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + return -ENOENT; + + if (feature->flags_reg_num =3D=3D reg_num) + conf->flags =3D value & SBI_FWFT_SET_FLAG_LOCK; + else + ret =3D conf->feature->set(vcpu, conf, true, value); + + return sbi_err_map_linux_errno(ret); +} + const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft =3D { .extid_start =3D SBI_EXT_FWFT, .extid_end =3D SBI_EXT_FWFT, @@ -361,4 +500,10 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft = =3D { .init =3D kvm_sbi_ext_fwft_init, .deinit =3D kvm_sbi_ext_fwft_deinit, .reset =3D kvm_sbi_ext_fwft_reset, + .have_state =3D true, + .state_reg_subtype =3D KVM_REG_RISCV_SBI_FWFT, + .get_state_reg_count =3D kvm_sbi_ext_fwft_get_reg_count, + .get_state_reg_id =3D kvm_sbi_ext_fwft_get_reg_id, + .get_state_reg =3D kvm_sbi_ext_fwft_get_reg, + .set_state_reg =3D kvm_sbi_ext_fwft_set_reg, }; --=20 2.43.0