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Thu, 14 Aug 2025 08:56:16 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 3/6] RISC-V: KVM: Introduce optional ONE_REG callbacks for SBI extensions Date: Thu, 14 Aug 2025 21:25:45 +0530 Message-ID: <20250814155548.457172-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814155548.457172-1-apatel@ventanamicro.com> References: <20250814155548.457172-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SBI extensions can have per-VCPU state which needs to be saved/restored through ONE_REG interface for Guest/VM migration. Introduce optional ONE_REG callbacks for SBI extensions so that ONE_REG implementation for an SBI extenion is part of the extension sources. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 21 ++-- arch/riscv/kvm/vcpu_onereg.c | 31 +----- arch/riscv/kvm/vcpu_sbi.c | 145 ++++++++++++++++++++++---- arch/riscv/kvm/vcpu_sbi_sta.c | 64 ++++++++---- 4 files changed, 178 insertions(+), 83 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 766031e80960..144c3f6d5eb9 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -59,6 +59,15 @@ struct kvm_vcpu_sbi_extension { void (*deinit)(struct kvm_vcpu *vcpu); =20 void (*reset)(struct kvm_vcpu *vcpu); + + bool have_state; + unsigned long state_reg_subtype; + unsigned long (*get_state_reg_count)(struct kvm_vcpu *vcpu); + int (*get_state_reg_id)(struct kvm_vcpu *vcpu, int index, u64 *reg_id); + int (*get_state_reg)(struct kvm_vcpu *vcpu, unsigned long reg_num, + unsigned long reg_size, void *reg_val); + int (*set_state_reg)(struct kvm_vcpu *vcpu, unsigned long reg_num, + unsigned long reg_size, const void *reg_val); }; =20 void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run= ); @@ -73,10 +82,9 @@ int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); -int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, - const struct kvm_one_reg *reg); -int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, - const struct kvm_one_reg *reg); +int kvm_riscv_vcpu_reg_indices_sbi(struct kvm_vcpu *vcpu, u64 __user *uind= ices); +int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg); +int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg); const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( struct kvm_vcpu *vcpu, unsigned long extid); bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx); @@ -85,11 +93,6 @@ void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sbi_reset(struct kvm_vcpu *vcpu); =20 -int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long re= g_num, - unsigned long *reg_val); -int kvm_riscv_vcpu_set_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long re= g_num, - unsigned long reg_val); - #ifdef CONFIG_RISCV_SBI_V01 extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01; #endif diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index b77748a56a59..5843b0519224 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -1090,36 +1090,9 @@ static unsigned long num_sbi_ext_regs(struct kvm_vcp= u *vcpu) return copy_sbi_ext_reg_indices(vcpu, NULL); } =20 -static int copy_sbi_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) -{ - struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; - int total =3D 0; - - if (scontext->ext_status[KVM_RISCV_SBI_EXT_STA] =3D=3D KVM_RISCV_SBI_EXT_= STATUS_ENABLED) { - u64 size =3D IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_= U64; - int n =3D sizeof(struct kvm_riscv_sbi_sta) / sizeof(unsigned long); - - for (int i =3D 0; i < n; i++) { - u64 reg =3D KVM_REG_RISCV | size | - KVM_REG_RISCV_SBI_STATE | - KVM_REG_RISCV_SBI_STA | i; - - if (uindices) { - if (put_user(reg, uindices)) - return -EFAULT; - uindices++; - } - } - - total +=3D n; - } - - return total; -} - static inline unsigned long num_sbi_regs(struct kvm_vcpu *vcpu) { - return copy_sbi_reg_indices(vcpu, NULL); + return kvm_riscv_vcpu_reg_indices_sbi(vcpu, NULL); } =20 static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu) @@ -1247,7 +1220,7 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *= vcpu, return ret; uindices +=3D ret; =20 - ret =3D copy_sbi_reg_indices(vcpu, uindices); + ret =3D kvm_riscv_vcpu_reg_indices_sbi(vcpu, uindices); if (ret < 0) return ret; uindices +=3D ret; diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 01a93f4fdb16..8b3c393e0c83 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -364,64 +364,163 @@ int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *= vcpu, return 0; } =20 -int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, - const struct kvm_one_reg *reg) +int kvm_riscv_vcpu_reg_indices_sbi(struct kvm_vcpu *vcpu, u64 __user *uind= ices) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + unsigned long state_reg_count; + int i, j, rc, count =3D 0; + u64 reg; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + + if (!ext->have_state || + scontext->ext_status[entry->ext_idx] !=3D KVM_RISCV_SBI_EXT_STATUS_E= NABLED) + continue; + + state_reg_count =3D ext->get_state_reg_count(vcpu); + if (!uindices) + goto skip_put_user; + + for (j =3D 0; j < state_reg_count; j++) { + if (ext->get_state_reg_id) { + rc =3D ext->get_state_reg_id(vcpu, j, ®); + if (rc) + return rc; + } else { + reg =3D KVM_REG_RISCV | + (IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64) | + KVM_REG_RISCV_SBI_STATE | + ext->state_reg_subtype | j; + } + + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } + +skip_put_user: + count +=3D state_reg_count; + } + + return count; +} + +static const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext_withstat= e(struct kvm_vcpu *vcpu, + unsigned long subtype) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int i; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + + if (ext->have_state && + ext->state_reg_subtype =3D=3D subtype && + scontext->ext_status[entry->ext_idx] =3D=3D KVM_RISCV_SBI_EXT_STATUS= _ENABLED) + return ext; + } + + return NULL; +} + +int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg) { unsigned long __user *uaddr =3D (unsigned long __user *)(unsigned long)reg->addr; unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_SBI_STATE); - unsigned long reg_subtype, reg_val; - - if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) + const struct kvm_vcpu_sbi_extension *ext; + unsigned long reg_subtype; + void *reg_val; + u64 data64; + u32 data32; + u16 data16; + u8 data8; + + switch (KVM_REG_SIZE(reg->id)) { + case 1: + reg_val =3D &data8; + break; + case 2: + reg_val =3D &data16; + break; + case 4: + reg_val =3D &data32; + break; + case 8: + reg_val =3D &data64; + break; + default: return -EINVAL; + }; =20 - if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) + if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; =20 reg_subtype =3D reg_num & KVM_REG_RISCV_SUBTYPE_MASK; reg_num &=3D ~KVM_REG_RISCV_SUBTYPE_MASK; =20 - switch (reg_subtype) { - case KVM_REG_RISCV_SBI_STA: - return kvm_riscv_vcpu_set_reg_sbi_sta(vcpu, reg_num, reg_val); - default: + ext =3D kvm_vcpu_sbi_find_ext_withstate(vcpu, reg_subtype); + if (!ext || !ext->set_state_reg) return -EINVAL; - } =20 - return 0; + return ext->set_state_reg(vcpu, reg_num, KVM_REG_SIZE(reg->id), reg_val); } =20 -int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, - const struct kvm_one_reg *reg) +int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg) { unsigned long __user *uaddr =3D (unsigned long __user *)(unsigned long)reg->addr; unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_SBI_STATE); - unsigned long reg_subtype, reg_val; + const struct kvm_vcpu_sbi_extension *ext; + unsigned long reg_subtype; + void *reg_val; + u64 data64; + u32 data32; + u16 data16; + u8 data8; int ret; =20 - if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) + switch (KVM_REG_SIZE(reg->id)) { + case 1: + reg_val =3D &data8; + break; + case 2: + reg_val =3D &data16; + break; + case 4: + reg_val =3D &data32; + break; + case 8: + reg_val =3D &data64; + break; + default: return -EINVAL; + }; =20 reg_subtype =3D reg_num & KVM_REG_RISCV_SUBTYPE_MASK; reg_num &=3D ~KVM_REG_RISCV_SUBTYPE_MASK; =20 - switch (reg_subtype) { - case KVM_REG_RISCV_SBI_STA: - ret =3D kvm_riscv_vcpu_get_reg_sbi_sta(vcpu, reg_num, ®_val); - break; - default: + ext =3D kvm_vcpu_sbi_find_ext_withstate(vcpu, reg_subtype); + if (!ext || !ext->get_state_reg) return -EINVAL; - } =20 + ret =3D ext->get_state_reg(vcpu, reg_num, KVM_REG_SIZE(reg->id), reg_val); if (ret) return ret; =20 - if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) + if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) return -EFAULT; =20 return 0; diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index cc6cb7c8f0e4..d14cf6255d83 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -151,63 +151,83 @@ static unsigned long kvm_sbi_ext_sta_probe(struct kvm= _vcpu *vcpu) return !!sched_info_on(); } =20 -const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta =3D { - .extid_start =3D SBI_EXT_STA, - .extid_end =3D SBI_EXT_STA, - .handler =3D kvm_sbi_ext_sta_handler, - .probe =3D kvm_sbi_ext_sta_probe, - .reset =3D kvm_riscv_vcpu_sbi_sta_reset, -}; +static unsigned long kvm_sbi_ext_sta_get_state_reg_count(struct kvm_vcpu *= vcpu) +{ + return sizeof(struct kvm_riscv_sbi_sta) / sizeof(unsigned long); +} =20 -int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, - unsigned long reg_num, - unsigned long *reg_val) +static int kvm_sbi_ext_sta_get_reg(struct kvm_vcpu *vcpu, unsigned long re= g_num, + unsigned long reg_size, void *reg_val) { + unsigned long *value; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D reg_val; + switch (reg_num) { case KVM_REG_RISCV_SBI_STA_REG(shmem_lo): - *reg_val =3D (unsigned long)vcpu->arch.sta.shmem; + *value =3D (unsigned long)vcpu->arch.sta.shmem; break; case KVM_REG_RISCV_SBI_STA_REG(shmem_hi): if (IS_ENABLED(CONFIG_32BIT)) - *reg_val =3D upper_32_bits(vcpu->arch.sta.shmem); + *value =3D upper_32_bits(vcpu->arch.sta.shmem); else - *reg_val =3D 0; + *value =3D 0; break; default: - return -EINVAL; + return -ENOENT; } =20 return 0; } =20 -int kvm_riscv_vcpu_set_reg_sbi_sta(struct kvm_vcpu *vcpu, - unsigned long reg_num, - unsigned long reg_val) +static int kvm_sbi_ext_sta_set_reg(struct kvm_vcpu *vcpu, unsigned long re= g_num, + unsigned long reg_size, const void *reg_val) { + unsigned long value; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D *(const unsigned long *)reg_val; + switch (reg_num) { case KVM_REG_RISCV_SBI_STA_REG(shmem_lo): if (IS_ENABLED(CONFIG_32BIT)) { gpa_t hi =3D upper_32_bits(vcpu->arch.sta.shmem); =20 - vcpu->arch.sta.shmem =3D reg_val; + vcpu->arch.sta.shmem =3D value; vcpu->arch.sta.shmem |=3D hi << 32; } else { - vcpu->arch.sta.shmem =3D reg_val; + vcpu->arch.sta.shmem =3D value; } break; case KVM_REG_RISCV_SBI_STA_REG(shmem_hi): if (IS_ENABLED(CONFIG_32BIT)) { gpa_t lo =3D lower_32_bits(vcpu->arch.sta.shmem); =20 - vcpu->arch.sta.shmem =3D ((gpa_t)reg_val << 32); + vcpu->arch.sta.shmem =3D ((gpa_t)value << 32); vcpu->arch.sta.shmem |=3D lo; - } else if (reg_val !=3D 0) { + } else if (value !=3D 0) { return -EINVAL; } break; default: - return -EINVAL; + return -ENOENT; } =20 return 0; } + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta =3D { + .extid_start =3D SBI_EXT_STA, + .extid_end =3D SBI_EXT_STA, + .handler =3D kvm_sbi_ext_sta_handler, + .probe =3D kvm_sbi_ext_sta_probe, + .reset =3D kvm_riscv_vcpu_sbi_sta_reset, + .have_state =3D true, + .state_reg_subtype =3D KVM_REG_RISCV_SBI_STA, + .get_state_reg_count =3D kvm_sbi_ext_sta_get_state_reg_count, + .get_state_reg =3D kvm_sbi_ext_sta_get_reg, + .set_state_reg =3D kvm_sbi_ext_sta_set_reg, +}; --=20 2.43.0