From nobody Sat Oct 4 15:59:03 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D53E3262FC0 for ; Mon, 18 Aug 2025 04:37:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755491844; cv=none; b=ep2+fjJD0JSDpeITNXcyifiGW4yBbpwrFyv7Z503scFQzPgYkd8q1da8Z/ej1a2pTpUqZO9Nk7OGR0uZRQBNuM7NM+6K+K1Wn5/ASnoprc/lbhJsu2fL8UAJrWu/kHzasBzkCyYB+aB/drR2x0+6bUeGpYQ8IvPe4JuDD8t0kAk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755491844; c=relaxed/simple; bh=eQ6mbLJ666ylH+iobL9nwWrhK1RwBh90HeDv3LHcVhs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=QKyRvOlSi/Ojy7UGNz/10HrIcNQ+JCNVCGsH1ePTH+Fhs9NkzPSWiFIW+NL1nvDnjosRHs7UI176HSYTdsJONsqxAeUmLZW/buelGodbrdsCGzYVrJlZrnTnFlb2BsZJe2cWiQBBDTxpuuXZPM4d8jYOsK1x9SFenQlRRnY+YD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=jYemU/V/; arc=none smtp.client-ip=203.254.224.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="jYemU/V/" Received: from epcas5p3.samsung.com (unknown [182.195.41.41]) by mailout2.samsung.com (KnoxPortal) with ESMTP id 20250818043719epoutp0264bd11417e9bb03d586c9014b985f9cd~cwocCQ8fl1528515285epoutp026 for ; Mon, 18 Aug 2025 04:37:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20250818043719epoutp0264bd11417e9bb03d586c9014b985f9cd~cwocCQ8fl1528515285epoutp026 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1755491839; bh=xl82Otcai0y60jQ/O2jr10UdDoE6TM4ftxxvpBCLJQM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jYemU/V/NSIjwx2P2zVz9QHeHiLPzTGKU2zfEGt5cM3QJ98lu1YulWakYgzC4fqaF /DqnWCrvI/dYcihH0SF2zLDz2TJj+hO73tSW8MkpwsrkmcER3U5HKa5zpDK40ztgJh ao1k7ANX4H9tXiS9fefTxWHjCrNltBMyc7oQ03uI= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPS id 20250818043719epcas5p4910c652177a448bc6bad489f6c7e881a~cwobik0sO1032010320epcas5p4g; Mon, 18 Aug 2025 04:37:19 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.90]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4c50LQ2Nhjz6B9m4; Mon, 18 Aug 2025 04:37:18 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250814141003epcas5p167e0a3d0ecc52fd8af17151cdddd031a~bp3W8Nc0d0355303553epcas5p1H; Thu, 14 Aug 2025 14:10:03 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250814140959epsmtip2c60bd3f2bed42df98c8f3e5a092a9a7a~bp3THPJDQ1586615866epsmtip2A; Thu, 14 Aug 2025 14:09:59 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 01/12] dt-bindings: clock: Add CAM_CSI clock macro for FSD Date: Thu, 14 Aug 2025 19:39:32 +0530 Message-ID: <20250814140943.22531-2-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141003epcas5p167e0a3d0ecc52fd8af17151cdddd031a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141003epcas5p167e0a3d0ecc52fd8af17151cdddd031a References: <20250814140943.22531-1-inbaraj.e@samsung.com> CAM_CSI block has ACLK, PCLK and PLL clocks. PCLK id is already assigned. To use PCLK and PLL clock in driver add id macro for CAM_CSI_PLL and CAM_CSI_PCLK. Signed-off-by: Inbaraj E --- include/dt-bindings/clock/fsd-clk.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/cloc= k/fsd-clk.h index 3f7b64d93558..58fdec8f4c2a 100644 --- a/include/dt-bindings/clock/fsd-clk.h +++ b/include/dt-bindings/clock/fsd-clk.h @@ -139,5 +139,18 @@ #define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 #define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 #define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 +#define CAM_CSI_PLL 13 +#define CAM_CSI0_0_IPCLKPORT_I_PCLK 14 +#define CAM_CSI0_1_IPCLKPORT_I_PCLK 15 +#define CAM_CSI0_2_IPCLKPORT_I_PCLK 16 +#define CAM_CSI0_3_IPCLKPORT_I_PCLK 17 +#define CAM_CSI1_0_IPCLKPORT_I_PCLK 18 +#define CAM_CSI1_1_IPCLKPORT_I_PCLK 19 +#define CAM_CSI1_2_IPCLKPORT_I_PCLK 20 +#define CAM_CSI1_3_IPCLKPORT_I_PCLK 21 +#define CAM_CSI2_0_IPCLKPORT_I_PCLK 22 +#define CAM_CSI2_1_IPCLKPORT_I_PCLK 23 +#define CAM_CSI2_2_IPCLKPORT_I_PCLK 24 +#define CAM_CSI2_3_IPCLKPORT_I_PCLK 25 =20 #endif /*_DT_BINDINGS_CLOCK_FSD_H */ --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB5CD265CAD for ; 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Mon, 18 Aug 2025 04:37:24 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.91]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4c50LW3f53z3hhTB; Mon, 18 Aug 2025 04:37:23 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250814141009epcas5p153e4aacfc1ead3db8c9bb647c6e5c7c4~bp3cJoraC0184301843epcas5p1q; Thu, 14 Aug 2025 14:10:09 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250814141005epsmtip2d1643f4a1ca80c05e99ef3861a193ff7~bp3YUwBVU1817818178epsmtip2j; Thu, 14 Aug 2025 14:10:05 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 02/12] clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block Date: Thu, 14 Aug 2025 19:39:33 +0530 Message-ID: <20250814140943.22531-3-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141009epcas5p153e4aacfc1ead3db8c9bb647c6e5c7c4 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141009epcas5p153e4aacfc1ead3db8c9bb647c6e5c7c4 References: <20250814140943.22531-1-inbaraj.e@samsung.com> Add clock id for PCLK and PLL. These clock id will be used for operation of CSI driver. PCLK is AXI2APB clock used for register access. PLL clock is main clock source for CAM_CSI block. Signed-off-by: Inbaraj E --- drivers/clk/samsung/clk-fsd.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index 594931334574..4124d65e3d18 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -89,7 +89,7 @@ #define CLKS_NR_FSYS1 (PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1) #define CLKS_NR_IMEM (IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1) #define CLKS_NR_MFC (MFC_MFC_IPCLKPORT_ACLK + 1) -#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_ACLK + 1) +#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_PCLK + 1) =20 static const unsigned long cmu_clk_regs[] __initconst =3D { PLL_LOCKTIME_PLL_SHARED0, @@ -1646,7 +1646,7 @@ static const struct samsung_pll_rate_table pll_cam_cs= i_rate_table[] __initconst }; =20 static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst =3D { - PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll", + PLL(pll_142xx, CAM_CSI_PLL, "fout_pll_cam_csi", "fin_pll", PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_tabl= e), }; =20 @@ -1682,51 +1682,51 @@ static const struct samsung_gate_clock cam_csi_gate= _clks[] __initconst =3D { GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE= _UNUSED, 0), GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_ca= m_csi0_aclk", GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI0_0_IPCLKPORT_I_PCLK, "cam_csi0_0_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_ca= m_csi0_aclk", GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI0_1_IPCLKPORT_I_PCLK, "cam_csi0_1_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_ca= m_csi0_aclk", GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI0_2_IPCLKPORT_I_PCLK, "cam_csi0_2_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_ca= m_csi0_aclk", GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI0_3_IPCLKPORT_I_PCLK, "cam_csi0_3_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_ca= m_csi1_aclk", GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI1_0_IPCLKPORT_I_PCLK, "cam_csi1_0_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_ca= m_csi1_aclk", GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI1_1_IPCLKPORT_I_PCLK, "cam_csi1_1_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_ca= m_csi1_aclk", GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI1_2_IPCLKPORT_I_PCLK, "cam_csi1_2_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_ca= m_csi1_aclk", GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI1_3_IPCLKPORT_I_PCLK, "cam_csi1_3_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_ca= m_csi2_aclk", GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI2_0_IPCLKPORT_I_PCLK, "cam_csi2_0_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_ca= m_csi2_aclk", GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI2_1_IPCLKPORT_I_PCLK, "cam_csi2_1_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_ca= m_csi2_aclk", GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI2_2_IPCLKPORT_I_PCLK, "cam_csi2_2_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_ca= m_csi2_aclk", GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), - GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GATE(CAM_CSI2_3_IPCLKPORT_I_PCLK, "cam_csi2_3_ipclkport_i_pclk", "dout_ca= m_csi_busp", GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d", "dout_cam_csi_busd", --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 701F7262FF8 for ; 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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141014epcas5p410d41ede7e8ae4f3cf8db6d041d03946 References: <20250814140943.22531-1-inbaraj.e@samsung.com> Document the MIPI CSI2 controller device tree bindings for Tesla FSD SoC Signed-off-by: Inbaraj E --- .../bindings/media/nxp,imx-mipi-csi2.yaml | 88 ++++++++++++++----- 1 file changed, 68 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml= b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml index 03a23a26c4f3..802fb1bd150d 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml @@ -14,7 +14,7 @@ description: |- The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 receiver IP core named CSIS. The IP core originates from Samsung, and ma= y be compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS ve= rsion - 3.3, and i.MX8 SoCs use CSIS version 3.6.3. + 3.3, i.MX8 SoCs use CSIS version 3.6.3 and FSD SoC uses CSIS version 4.3. =20 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PH= Y is completely wrapped by the CSIS and doesn't expose a control interface of= its @@ -26,6 +26,7 @@ properties: - enum: - fsl,imx7-mipi-csi2 - fsl,imx8mm-mipi-csi2 + - tesla,fsd-mipi-csi2 - items: - enum: - fsl,imx8mp-mipi-csi2 @@ -38,24 +39,21 @@ properties: maxItems: 1 =20 clocks: - minItems: 3 - items: - - description: The peripheral clock (a.k.a. APB clock) - - description: The external clock (optionally used as the pixel cloc= k) - - description: The MIPI D-PHY clock - - description: The AXI clock + minItems: 2 + maxItems: 4 =20 clock-names: - minItems: 3 - items: - - const: pclk - - const: wrap - - const: phy - - const: axi + minItems: 2 + maxItems: 4 =20 power-domains: maxItems: 1 =20 + samsung,syscon-csis: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Syscon used to hold and release the reset of MIPI D-PHY + phy-supply: description: The MIPI D-PHY digital power supply =20 @@ -85,7 +83,8 @@ properties: properties: data-lanes: description: - Note that 'fsl,imx7-mipi-csi2' only supports up to 2 dat= a lines. + Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data + lines. minItems: 1 items: - const: 1 @@ -107,7 +106,6 @@ required: - interrupts - clocks - clock-names - - power-domains - ports =20 additionalProperties: false @@ -116,20 +114,70 @@ allOf: - if: properties: compatible: - contains: - const: fsl,imx7-mipi-csi2 + const: fsl,imx7-mipi-csi2 then: + properties: + clocks: + items: + - description: The peripheral clock (a.k.a. APB clock) + - description: The external clock (optionally used as the pixel + clock) + - description: The MIPI D-PHY clock + clock-names: + items: + - const: pclk + - const: wrap + - const: phy + samsung,syscon-csis: false required: + - power-domains - phy-supply - resets - else: + + - if: + properties: + compatible: + const: fsl,imx8mm-mipi-csi2 + then: properties: clocks: - minItems: 4 + items: + - description: The peripheral clock (a.k.a. APB clock) + - description: The external clock (optionally used as the pixel + clock) + - description: The MIPI D-PHY clock + - description: The AXI clock clock-names: - minItems: 4 + items: + - const: pclk + - const: wrap + - const: phy + - const: axi + samsung,syscon-csis: false phy-supply: false resets: false + required: + - power-domains + + - if: + properties: + compatible: + const: tesla,fsd-mipi-csi2 + then: + properties: + clocks: + items: + - description: The peripheral clock (a.k.a. APB clock) + - description: The DMA clock + clocks-names: + items: + - const: pclk + - const: aclk + phy-supply: false + resets: false + power-domains: false + required: + - samsung,syscon-csis =20 examples: - | --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8626E262FF3 for ; Mon, 18 Aug 2025 04:37:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755491870; cv=none; b=HaRX/EQ8gr//ryUhk0ANtA+RXgsNjsL0ZSjZbSTClrkLx5JfB3iEg55/TxztdiTby2XgPjIf81OYYr4YFca1/CyCZd3AnXheWcwiSJ0oSxLUVEkGT5ixBlmtX2pBpxVuV/b2IsxpUsxe7+ydNDX1iIRPKRARiOiJ7KtHvNs8ISs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755491870; 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Thu, 14 Aug 2025 14:10:19 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250814141015epsmtip213875c3a71a7740663108afc82388f23~bp3iBPqAy1817818178epsmtip2l; Thu, 14 Aug 2025 14:10:15 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes Date: Thu, 14 Aug 2025 19:39:35 +0530 Message-ID: <20250814140943.22531-5-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141019epcas5p2f957b934d5b60d4649cf9c6abd6969d5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141019epcas5p2f957b934d5b60d4649cf9c6abd6969d5 References: <20250814140943.22531-1-inbaraj.e@samsung.com> There is a csi dma and csis interface that bundles together to allow csi2 capture. Signed-off-by: Inbaraj E --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 96 +++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 552 ++++++++++++++++++++++++++ 2 files changed, 648 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/te= sla/fsd-evb.dts index 9ff22e1c8723..dcc9a138cdb9 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -130,3 +130,99 @@ &serial_0 { &ufs { status =3D "okay"; }; + +&mipicsis0 { + status =3D "okay"; +}; + +&mipicsis1 { + status =3D "okay"; +}; + +&mipicsis2 { + status =3D "okay"; +}; + +&mipicsis3 { + status =3D "okay"; +}; + +&mipicsis4 { + status =3D "okay"; +}; + +&mipicsis5 { + status =3D "okay"; +}; + +&mipicsis6 { + status =3D "okay"; +}; + +&mipicsis7 { + status =3D "okay"; +}; + +&mipicsis8 { + status =3D "okay"; +}; + +&mipicsis9 { + status =3D "okay"; +}; + +&mipicsis10 { + status =3D "okay"; +}; + +&mipicsis11 { + status =3D "okay"; +}; + +&csis0 { + status =3D "okay"; +}; + +&csis1 { + status =3D "okay"; +}; + +&csis2 { + status =3D "okay"; +}; + +&csis3 { + status =3D "okay"; +}; + +&csis4 { + status =3D "okay"; +}; + +&csis5 { + status =3D "okay"; +}; + +&csis6 { + status =3D "okay"; +}; + +&csis7 { + status =3D "okay"; +}; + +&csis8 { + status =3D "okay"; +}; + +&csis9 { + status =3D "okay"; +}; + +&csis10 { + status =3D "okay"; +}; + +&csis11 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla= /fsd.dtsi index a5ebb3f9b18f..a83503e9c502 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -493,6 +493,558 @@ clock_mfc: clock-controller@12810000 { clock-names =3D "fin_pll"; }; =20 + mipicsis0: mipi-csis@12640000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x12640000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_0_out: endpoint { + remote-endpoint =3D <&csis_in_0>; + }; + }; + }; + }; + + csis0: csis@12641000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x12641000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_0: endpoint { + remote-endpoint =3D <&mipi_csis_0_out>; + }; + }; + }; + + mipicsis1: mipi-csis@12650000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x12650000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_1_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_1_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_1_out: endpoint { + remote-endpoint =3D <&csis_in_1>; + }; + }; + }; + }; + + csis1: csis@12651000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x12651000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_1_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_1_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_1: endpoint { + remote-endpoint =3D <&mipi_csis_1_out>; + }; + }; + }; + + mipicsis2: mipi-csis@12660000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x12660000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_2_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_2_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_2_out: endpoint { + remote-endpoint =3D <&csis_in_2>; + }; + }; + }; + }; + + csis2: csis@12661000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x12661000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_2_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_2_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_2: endpoint { + remote-endpoint =3D <&mipi_csis_2_out>; + }; + }; + }; + + mipicsis3: mipi-csis@12670000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x12670000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_3_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_3_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_3_out: endpoint { + remote-endpoint =3D <&csis_in_3>; + }; + }; + }; + }; + + csis3: csis@12671000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x12671000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_3_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_3_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_3: endpoint { + remote-endpoint =3D <&mipi_csis_3_out>; + }; + }; + }; + + mipicsis4: mipi-csis@12680000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x12680000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI1_0_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI1_0_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_4_out: endpoint { + remote-endpoint =3D <&csis_in_4>; + }; + }; + }; + }; + + csis4: csis@12681000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x12681000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI1_0_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI1_0_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_4: endpoint { + remote-endpoint =3D <&mipi_csis_4_out>; + }; + }; + }; + + mipicsis5: mipi-csis@12690000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x12690000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI1_1_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI1_1_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_5_out: endpoint { + remote-endpoint =3D <&csis_in_5>; + }; + }; + }; + }; + + csis5: csis@12691000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x12691000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI1_1_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI1_1_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_5: endpoint { + remote-endpoint =3D <&mipi_csis_5_out>; + }; + }; + }; + + mipicsis6: mipi-csis@126a0000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x126a0000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI1_2_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI1_2_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_6_out: endpoint { + remote-endpoint =3D <&csis_in_6>; + }; + }; + }; + }; + + csis6: csis@126a1000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x126a1000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI1_2_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI1_2_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_6: endpoint { + remote-endpoint =3D <&mipi_csis_6_out>; + }; + }; + }; + + mipicsis7: mipi-csis@126b0000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x126b0000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI1_3_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI1_3_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_7_out: endpoint { + remote-endpoint =3D <&csis_in_7>; + }; + }; + }; + }; + + csis7: csis@126b1000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x126b1000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI1_3_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI1_3_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_7: endpoint { + remote-endpoint =3D <&mipi_csis_7_out>; + }; + }; + }; + + mipicsis8: mipi-csis@126c0000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x126c0000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI2_0_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI2_0_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_8_out: endpoint { + remote-endpoint =3D <&csis_in_8>; + }; + }; + }; + }; + + csis8: csis@126c1000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x126c1000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI2_0_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI2_0_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_8: endpoint { + remote-endpoint =3D <&mipi_csis_8_out>; + }; + }; + }; + + mipicsis9: mipi-csis@126d0000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x126d0000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI2_1_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI2_1_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_9_out: endpoint { + remote-endpoint =3D <&csis_in_9>; + }; + }; + }; + }; + + csis9: csis@126d1000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x126d1000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI2_1_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI2_1_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_9: endpoint { + remote-endpoint =3D <&mipi_csis_9_out>; + }; + }; + }; + + mipicsis10: mipi-csis@126e0000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x126e0000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI2_2_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI2_2_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_10_out: endpoint { + remote-endpoint =3D <&csis_in_10>; + }; + }; + }; + }; + + csis10: csis@126e1000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x126e1000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI2_2_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI2_2_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + status =3D "disabled"; + + port { + csis_in_10: endpoint { + remote-endpoint =3D <&mipi_csis_10_out>; + }; + }; + }; + + mipicsis11: mipi-csis@126f0000 { + compatible =3D "tesla,fsd-mipi-csi2"; + reg =3D <0x0 0x126f0000 0x0 0x124>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI2_3_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI2_3_IPCLKPORT_I_PCLK>; + clock-names =3D "aclk", "pclk"; + samsung,syscon-csis =3D <&sysreg_cam 0x40c>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + + mipi_csis_11_out: endpoint { + remote-endpoint =3D <&csis_in_11>; + }; + }; + }; + }; + + csis11: csis@126f1000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x0 0x126f1000 0x0 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI2_3_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI2_3_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; 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Thu, 14 Aug 2025 14:10:25 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250814141021epsmtip2fc5a1f0b0511a018a32f4c76fb4e853e~bp3neAIzV1817818178epsmtip2m; Thu, 14 Aug 2025 14:10:21 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 05/12] media: imx-mipi-csis: Move clk to mipi_csis_info structure Date: Thu, 14 Aug 2025 19:39:36 +0530 Message-ID: <20250814140943.22531-6-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141025epcas5p2b226c4eaab5d60d0e95f684e2ef930f2 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141025epcas5p2b226c4eaab5d60d0e95f684e2ef930f2 References: <20250814140943.22531-1-inbaraj.e@samsung.com> clock names in NXP SoC's is different from the FSD SoC. Inorder to extend this driver to use for FSD SoC. Move the clock names to mipi_csis_info structure. Signed-off-by: Inbaraj E --- drivers/media/platform/nxp/imx-mipi-csis.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/pla= tform/nxp/imx-mipi-csis.c index 2beb5f43c2c0..4afa75734f05 100644 --- a/drivers/media/platform/nxp/imx-mipi-csis.c +++ b/drivers/media/platform/nxp/imx-mipi-csis.c @@ -267,6 +267,8 @@ static const struct mipi_csis_event mipi_csis_events[] = =3D { =20 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) =20 +#define MIPI_CSIS_MAX_CLOCKS 4 + enum mipi_csis_clk { MIPI_CSIS_CLK_PCLK, MIPI_CSIS_CLK_WRAP, @@ -274,13 +276,6 @@ enum mipi_csis_clk { MIPI_CSIS_CLK_AXI, }; =20 -static const char * const mipi_csis_clk_id[] =3D { - "pclk", - "wrap", - "phy", - "axi", -}; - enum mipi_csis_version { MIPI_CSIS_V3_3, MIPI_CSIS_V3_6_3, @@ -289,6 +284,7 @@ enum mipi_csis_version { struct mipi_csis_info { enum mipi_csis_version version; unsigned int num_clocks; + const char *clk_names[MIPI_CSIS_MAX_CLOCKS]; }; =20 struct mipi_csis_device { @@ -697,7 +693,7 @@ static int mipi_csis_clk_get(struct mipi_csis_device *c= sis) return -ENOMEM; =20 for (i =3D 0; i < csis->info->num_clocks; i++) - csis->clks[i].id =3D mipi_csis_clk_id[i]; + csis->clks[i].id =3D csis->info->clk_names[i]; =20 ret =3D devm_clk_bulk_get(csis->dev, csis->info->num_clocks, csis->clks); @@ -1539,12 +1535,14 @@ static const struct of_device_id mipi_csis_of_match= [] =3D { .data =3D &(const struct mipi_csis_info){ .version =3D MIPI_CSIS_V3_3, .num_clocks =3D 3, + .clk_names =3D {"pclk", "wrap", "phy"}, }, }, { .compatible =3D "fsl,imx8mm-mipi-csi2", .data =3D &(const struct mipi_csis_info){ .version =3D MIPI_CSIS_V3_6_3, .num_clocks =3D 4, + .clk_names =3D {"pclk", "wrap", "phy", "axi"}, }, }, { /* sentinel */ }, --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BC8326A1C1 for ; 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Mon, 18 Aug 2025 04:37:57 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.88]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4c50M86WLRz6B9mD; Mon, 18 Aug 2025 04:37:56 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250814141030epcas5p45a75274697463bbca9cab12f776a4e8c~bp3wECC8s1288712887epcas5p4Z; Thu, 14 Aug 2025 14:10:30 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250814141026epsmtip2c41e27576eca50949b643b58df963c58~bp3sPL3m81817818178epsmtip2n; Thu, 14 Aug 2025 14:10:26 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 06/12] media: imx-mipi-csis: Move irq flag and handler to mipi_csis_info structure Date: Thu, 14 Aug 2025 19:39:37 +0530 Message-ID: <20250814140943.22531-7-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141030epcas5p45a75274697463bbca9cab12f776a4e8c X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141030epcas5p45a75274697463bbca9cab12f776a4e8c References: <20250814140943.22531-1-inbaraj.e@samsung.com> FSD CSI IP has only one IRQ line, shared between imx-mipi-csis and fsd-csi-media drivers. To extend this driver for FSD SoC support, move the IRQ flag and IRQ handler to the device data(structure mipi_csis_info). Signed-off-by: Inbaraj E --- drivers/media/platform/nxp/imx-mipi-csis.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/pla= tform/nxp/imx-mipi-csis.c index 4afa75734f05..a3e2c8ae332f 100644 --- a/drivers/media/platform/nxp/imx-mipi-csis.c +++ b/drivers/media/platform/nxp/imx-mipi-csis.c @@ -285,6 +285,8 @@ struct mipi_csis_info { enum mipi_csis_version version; unsigned int num_clocks; const char *clk_names[MIPI_CSIS_MAX_CLOCKS]; + unsigned int irq_flag; + irq_handler_t irq_handler; }; =20 struct mipi_csis_device { @@ -1462,7 +1464,7 @@ static int mipi_csis_probe(struct platform_device *pd= ev) mipi_csis_phy_reset(csis); =20 /* Now that the hardware is initialized, request the interrupt. */ - ret =3D devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, + ret =3D devm_request_irq(dev, irq, csis->info->irq_handler, csis->info->i= rq_flag, dev_name(dev), csis); if (ret) { dev_err(dev, "Interrupt request failed\n"); @@ -1536,6 +1538,8 @@ static const struct of_device_id mipi_csis_of_match[]= =3D { .version =3D MIPI_CSIS_V3_3, .num_clocks =3D 3, .clk_names =3D {"pclk", "wrap", "phy"}, + .irq_flag =3D 0, + .irq_handler =3D mipi_csis_irq_handler, }, }, { .compatible =3D "fsl,imx8mm-mipi-csi2", @@ -1543,6 +1547,8 @@ static const struct of_device_id mipi_csis_of_match[]= =3D { .version =3D MIPI_CSIS_V3_6_3, .num_clocks =3D 4, .clk_names =3D {"pclk", "wrap", "phy", "axi"}, + .irq_flag =3D 0, + .irq_handler =3D mipi_csis_irq_handler, }, }, { /* sentinel */ }, --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8CE1266EFC for ; Mon, 18 Aug 2025 04:38:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; 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spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="HidAGXEb" Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250818043803epoutp04b9c7a704099eb4bb6732e026da925575~cwpFCY1cx2679326793epoutp04J for ; Mon, 18 Aug 2025 04:38:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250818043803epoutp04b9c7a704099eb4bb6732e026da925575~cwpFCY1cx2679326793epoutp04J DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1755491883; bh=43oXxFKfnsTWy5UmLZ+z7pzwjTP2nYXG45oAqT0iINc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HidAGXEb3n8+rtLRb67VjqbdwkW8ShU4IpRJmpCb8tE76nkKUA7L9sBDUF25GKCcA nLH5ASW+dUQKp9I8QJM9wZxt9/y/1FkOhpz6lQKTuod/4oZAH6IfB+kYL43esXXxkM 40fKHZsY9MhlEqvrwzwXlCABbw3w2flssTs779So= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250818043802epcas5p3f4f768164a3d19f44e67d63533bea352~cwpEFn6bj2560625606epcas5p3x; Mon, 18 Aug 2025 04:38:02 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.89]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4c50MF6MqPz3hhTC; Mon, 18 Aug 2025 04:38:01 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250814141036epcas5p1fc02cea3f97534303673eb8453b6a18f~bp305UicQ0355803558epcas5p1I; Thu, 14 Aug 2025 14:10:36 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250814141031epsmtip26b88e96818e2b889c40dbd1ebeaccd62~bp3xEo9mG1850318503epsmtip2N; Thu, 14 Aug 2025 14:10:31 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 07/12] media: imx-mipi-csis: Add support to configure specific vc Date: Thu, 14 Aug 2025 19:39:38 +0530 Message-ID: <20250814140943.22531-8-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141036epcas5p1fc02cea3f97534303673eb8453b6a18f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141036epcas5p1fc02cea3f97534303673eb8453b6a18f References: <20250814140943.22531-1-inbaraj.e@samsung.com> MIPI_CSIS_V3_3 and MIPI_CSIS_V3_6_3 support streaming only on VC0. The MIPI_CSIS_V4_3 present in the FSD SoC supports streaming on any one VC out of four VCs. To extend support for the FSD SoC, add the ability to configure a specific VC. The FSD CSI Rx can configure any one VC and start streaming. Signed-off-by: Inbaraj E --- drivers/media/platform/nxp/imx-mipi-csis.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/pla= tform/nxp/imx-mipi-csis.c index a3e2c8ae332f..4f6c417fdf58 100644 --- a/drivers/media/platform/nxp/imx-mipi-csis.c +++ b/drivers/media/platform/nxp/imx-mipi-csis.c @@ -54,7 +54,7 @@ =20 /* CSIS common control */ #define MIPI_CSIS_CMN_CTRL 0x04 -#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) +#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n) BIT(((n) + 16)) #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) @@ -319,6 +319,7 @@ struct mipi_csis_device { u32 hs_settle; u32 clk_settle; } debug; + unsigned int vc; }; =20 /* -----------------------------------------------------------------------= ------ @@ -544,9 +545,10 @@ static void __mipi_csis_set_format(struct mipi_csis_de= vice *csis, const struct csis_pix_format *csis_fmt) { u32 val; + unsigned int vc =3D csis->vc; =20 /* Color format */ - val =3D mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); + val =3D mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(vc)); val &=3D ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK | MIPI_CSIS_ISPCFG_PIXEL_MASK); =20 @@ -567,11 +569,11 @@ static void __mipi_csis_set_format(struct mipi_csis_d= evice *csis, val |=3D MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; =20 val |=3D MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type); - mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); + mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(vc), val); =20 /* Pixel resolution */ val =3D format->width | (format->height << 16); - mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val); + mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(vc), val); } =20 static int mipi_csis_calculate_params(struct mipi_csis_device *csis, @@ -631,6 +633,7 @@ static void mipi_csis_set_params(struct mipi_csis_devic= e *csis, { int lanes =3D csis->bus.num_data_lanes; u32 val; + unsigned int vc =3D csis->vc; =20 val =3D mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); val &=3D ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; @@ -648,7 +651,7 @@ static void mipi_csis_set_params(struct mipi_csis_devic= e *csis, val =3D (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); - mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val); + mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(vc), val); =20 val =3D mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); val |=3D MIPI_CSIS_CLK_CTRL_WCLK_SRC; @@ -669,7 +672,7 @@ static void mipi_csis_set_params(struct mipi_csis_devic= e *csis, /* Update the shadow register. */ val =3D mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, - val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | + val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(vc) | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); } =20 @@ -945,6 +948,8 @@ static int mipi_csis_s_stream(struct v4l2_subdev *sd, i= nt enable) struct v4l2_subdev_state *state; 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Thu, 14 Aug 2025 14:10:37 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 08/12] media: imx-mipi-csis: Add support to dump all vc regs Date: Thu, 14 Aug 2025 19:39:39 +0530 Message-ID: <20250814140943.22531-9-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141041epcas5p2b281659391a8e45c95e8db21d9867f98 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141041epcas5p2b281659391a8e45c95e8db21d9867f98 References: <20250814140943.22531-1-inbaraj.e@samsung.com> Extend support to dump all 4 virtual channel register. Signed-off-by: Inbaraj E --- drivers/media/platform/nxp/imx-mipi-csis.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/pla= tform/nxp/imx-mipi-csis.c index 4f6c417fdf58..c1653a738854 100644 --- a/drivers/media/platform/nxp/imx-mipi-csis.c +++ b/drivers/media/platform/nxp/imx-mipi-csis.c @@ -876,11 +876,26 @@ static int mipi_csis_dump_regs(struct mipi_csis_devic= e *csis) { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" }, { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" }, { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" }, + { MIPI_CSIS_ISP_CONFIG_CH(1), "ISP_CONFIG_CH1" }, + { MIPI_CSIS_ISP_CONFIG_CH(2), "ISP_CONFIG_CH2" }, + { MIPI_CSIS_ISP_CONFIG_CH(3), "ISP_CONFIG_CH3" }, { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" }, + { MIPI_CSIS_ISP_RESOL_CH(1), "ISP_RESOL_CH1" }, + { MIPI_CSIS_ISP_RESOL_CH(2), "ISP_RESOL_CH2" }, + { MIPI_CSIS_ISP_RESOL_CH(3), "ISP_RESOL_CH3" }, { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" }, + { MIPI_CSIS_SDW_CONFIG_CH(1), "SDW_CONFIG_CH1" }, + { MIPI_CSIS_SDW_CONFIG_CH(2), "SDW_CONFIG_CH2" }, + { MIPI_CSIS_SDW_CONFIG_CH(3), "SDW_CONFIG_CH3" }, { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" }, + { MIPI_CSIS_SDW_RESOL_CH(1), "SDW_RESOL_CH1" }, + { MIPI_CSIS_SDW_RESOL_CH(2), "SDW_RESOL_CH2" }, + { MIPI_CSIS_SDW_RESOL_CH(3), "SDW_RESOL_CH3" }, { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" }, { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" }, + { MIPI_CSIS_FRAME_COUNTER_CH(1), "FRAME_COUNTER_CH1" }, + { MIPI_CSIS_FRAME_COUNTER_CH(2), "FRAME_COUNTER_CH2" }, + { MIPI_CSIS_FRAME_COUNTER_CH(3), "FRAME_COUNTER_CH3" }, }; =20 unsigned int i; --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61DF126D4DA for ; Mon, 18 Aug 2025 04:38:16 +0000 (UTC) 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20250814141042epsmtip282557f34e7ca313b2fa072250b331b84~bp36tp36g1818718187epsmtip2Z; Thu, 14 Aug 2025 14:10:42 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 09/12] media: imx-mipi-csis: Add support for FSD CSI Rx Date: Thu, 14 Aug 2025 19:39:40 +0530 Message-ID: <20250814140943.22531-10-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141046epcas5p3fd09b7e4ab34f521cf5ab548c41fb1d2 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141046epcas5p3fd09b7e4ab34f521cf5ab548c41fb1d2 References: <20250814140943.22531-1-inbaraj.e@samsung.com> The FSD SoC features a newer version(v4.3) of the CSI-2 receiver IP, similar to the one found in the i.MX7 and i.MX8MM, with the following differences. - Ability to select any one VC for streaming from the four available VCs. - Built-in DMA support Signed-off-by: Inbaraj E --- drivers/media/platform/nxp/imx-mipi-csis.c | 304 +++++++++++++++++++-- 1 file changed, 276 insertions(+), 28 deletions(-) diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/pla= tform/nxp/imx-mipi-csis.c index c1653a738854..2ff2693dacf7 100644 --- a/drivers/media/platform/nxp/imx-mipi-csis.c +++ b/drivers/media/platform/nxp/imx-mipi-csis.c @@ -35,6 +35,8 @@ #include #include #include +#include +#include =20 #define CSIS_DRIVER_NAME "imx-mipi-csis" =20 @@ -45,6 +47,9 @@ #define MIPI_CSIS_DEF_PIX_WIDTH 640 #define MIPI_CSIS_DEF_PIX_HEIGHT 480 =20 +/* CSIS V4_3 SYSREG macros */ +#define FSD_NO_CSI_PER_PHY_V4_3 4 +#define FSD_CSIS_RESETEN_DPHY_MASK_V4_3(phy) BIT_MASK(phy) /* Register map definition */ =20 /* CSIS version */ @@ -55,7 +60,11 @@ /* CSIS common control */ #define MIPI_CSIS_CMN_CTRL 0x04 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n) BIT(((n) + 16)) -#define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) +#define MIPI_CSIS_CMN_CTRL_DESKEW_ENABLE BIT(12) +#define MIPI_CSIS_CMN_CTRL_INTER_MODE(n) ((n) << 10) +#define MIPI_CSIS_CMN_CTRL_INTER_MODE_MASK GENMASK(11, 10) +#define MIPI_CSIS_CMN_CTRL_LANE_NUM(n) ((n) << 8) +#define MIPI_CSIS_CMN_CTRL_LANE_NUM_MASK GENMASK(9, 8) #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) @@ -64,13 +73,11 @@ #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) =20 /* CSIS clock control */ -#define MIPI_CSIS_CLK_CTRL 0x08 -#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28) -#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24) -#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20) -#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16) -#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) -#define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) +#define MIPI_CSIS_CLK_CTRL 0x08 +#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH(n, val) ((val) << (16 + ((n) *= 4))) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN(n) (1 << ((n) + 4)) +#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) +#define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) =20 /* CSIS Interrupt mask */ #define MIPI_CSIS_INT_MSK 0x10 @@ -100,9 +107,9 @@ #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) -#define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) -#define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) -#define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) +#define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n) BIT((16 + (n))) +#define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n) BIT((12 + (n))) +#define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n) BIT((8 + (n))) #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) @@ -110,6 +117,12 @@ #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff =20 +/* CSIS Interrupt mask1 */ +#define MIPI_CSIS_INT_MSK1 0x18 + +/* CSIS Interrupt source1 */ +#define MIPI_CSIS_INT_SRC1 0x1C + /* D-PHY status control */ #define MIPI_CSIS_DPHY_STATUS 0x20 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) @@ -123,6 +136,7 @@ #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) +#define MIPI_CSIS_DPHY_CMN_CTRL_S_BYTE_CLK_EN BIT(21) #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) @@ -170,7 +184,10 @@ /* D-PHY Slave Control register Low */ #define MIPI_CSIS_DPHY_SCTRL_L 0x38 /* D-PHY Slave Control register High */ -#define MIPI_CSIS_DPHY_SCTRL_H 0x3c +#define MIPI_CSIS_DPHY_SCTRL_H 0x3c +#define MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_MAX_SKEW_CODE_CTRL (0x24 << 2) +#define MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_MAX_SKEW_CODE_CTRL_MASK GENMASK(7,= 2) +#define MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_EN BIT(1) =20 /* ISP Configuration register */ #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) @@ -223,6 +240,12 @@ =20 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) =20 +/* VC Passing register */ +#define MIPI_CSIS_VC_PASSING_REG 0x120 +#define MIPI_CSIS_VC_PASSING(n) ((n) << 8) +#define MIPI_CSIS_VC_PASSING_MASK GENMASK(9, 8) +#define MIPI_CSIS_VC_PASSING_EN BIT(7) + /* Non-image packet data buffers */ #define MIPI_CSIS_PKTDATA_ODD 0x2000 #define MIPI_CSIS_PKTDATA_EVEN 0x3000 @@ -239,9 +262,18 @@ struct mipi_csis_event { =20 static const struct mipi_csis_event mipi_csis_events[] =3D { /* Errors */ - { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, + { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0), "SOT Lane0 Error" }, + { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1), "SOT Lane1 Error" }, + { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2), "SOT Lane2 Error" }, + { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3), "SOT Lane3 Error" }, + { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS(0), "Lost Frame Start Error vc0" }, + { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS(1), "Lost Frame Start Error v= c1" }, + { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS(2), "Lost Frame Start Error v= c2" }, + { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS(3), "Lost Frame Start Error v= c3" }, + { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE(0), "Lost Frame End Error vc0" }, + { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE(1), "Lost Frame End Error vc1= " }, + { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE(2), "Lost Frame End Error vc2= " }, + { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE(3), "Lost Frame End Error vc3= " }, { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, @@ -266,6 +298,7 @@ static const struct mipi_csis_event mipi_csis_events[] = =3D { }; =20 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) +#define MIPI_CSIS_INT_SRC_NUM_EVENTS_V4_3 17 =20 #define MIPI_CSIS_MAX_CLOCKS 4 =20 @@ -279,6 +312,7 @@ enum mipi_csis_clk { enum mipi_csis_version { MIPI_CSIS_V3_3, MIPI_CSIS_V3_6_3, + MIPI_CSIS_V4_3, }; =20 struct mipi_csis_info { @@ -292,6 +326,8 @@ struct mipi_csis_info { struct mipi_csis_device { struct device *dev; void __iomem *regs; + struct regmap *sysreg_map; + unsigned int phy_rst_off; struct clk_bulk_data *clks; struct reset_control *mrst; struct regulator *mipi_phy_regulator; @@ -352,6 +388,11 @@ static const struct csis_pix_format mipi_csis_formats[= ] =3D { .output =3D MEDIA_BUS_FMT_RGB888_1X24, .data_type =3D MIPI_CSI2_DT_RGB888, .width =3D 24, + }, { + .code =3D MEDIA_BUS_FMT_RGB888_1X24, + .output =3D MEDIA_BUS_FMT_RGB888_1X24, + .data_type =3D MIPI_CSI2_DT_RGB888, + .width =3D 24, }, /* RAW (Bayer and greyscale) formats. */ { @@ -508,7 +549,11 @@ static inline void mipi_csis_write(struct mipi_csis_de= vice *csis, u32 reg, static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, boo= l on) { mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); - mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); + + if (csis->info->version =3D=3D MIPI_CSIS_V4_3) + mipi_csis_write(csis, MIPI_CSIS_INT_MSK1, on ? 0xffffffff : 0); + else + mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); } =20 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) @@ -537,6 +582,8 @@ static void mipi_csis_system_enable(struct mipi_csis_de= vice *csis, int on) mask =3D (1 << (csis->bus.num_data_lanes + 1)) - 1; val |=3D (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); } + if (csis->info->version =3D=3D MIPI_CSIS_V4_3) + val |=3D MIPI_CSIS_DPHY_CMN_CTRL_S_BYTE_CLK_EN; mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); } =20 @@ -549,7 +596,10 @@ static void __mipi_csis_set_format(struct mipi_csis_de= vice *csis, =20 /* Color format */ val =3D mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(vc)); - val &=3D ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK + if (csis->info->version =3D=3D MIPI_CSIS_V4_3) + val &=3D ~(MIPI_CSIS_ISPCFG_FMT_MASK | MIPI_CSIS_ISPCFG_PIXEL_MASK); + else + val &=3D ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK | MIPI_CSIS_ISPCFG_PIXEL_MASK); =20 /* @@ -595,7 +645,7 @@ static int mipi_csis_calculate_params(struct mipi_csis_= device *csis, =20 lane_rate =3D link_freq * 2; =20 - if (lane_rate < 80000000 || lane_rate > 1500000000) { + if (lane_rate < 80000000 || lane_rate > 1600000000) { dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); return -EINVAL; } @@ -639,7 +689,11 @@ static void mipi_csis_set_params(struct mipi_csis_devi= ce *csis, val &=3D ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; val |=3D (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; if (csis->info->version =3D=3D MIPI_CSIS_V3_3) - val |=3D MIPI_CSIS_CMN_CTRL_INTER_MODE; + val |=3D MIPI_CSIS_CMN_CTRL_INTER_MODE(1); + else if (csis->info->version =3D=3D MIPI_CSIS_V4_3) { + val |=3D MIPI_CSIS_CMN_CTRL_INTER_MODE(3); + val |=3D MIPI_CSIS_CMN_CTRL_DESKEW_ENABLE; + } mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); =20 __mipi_csis_set_format(csis, format, csis_fmt); @@ -648,15 +702,23 @@ static void mipi_csis_set_params(struct mipi_csis_dev= ice *csis, MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); =20 - val =3D (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) - | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) - | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); + if (csis->info->version =3D=3D MIPI_CSIS_V4_3) + val =3D 0x20 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET; + else + val =3D (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) + | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) + | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(vc), val); =20 val =3D mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); - val |=3D MIPI_CSIS_CLK_CTRL_WCLK_SRC; - val |=3D MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); - val &=3D ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; + if (csis->info->version =3D=3D MIPI_CSIS_V4_3) { + val |=3D MIPI_CSIS_CLK_CTRL_CLKGATE_EN(vc); + val |=3D MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH(vc, 0x07); + } else { + val |=3D MIPI_CSIS_CLK_CTRL_WCLK_SRC; + val |=3D MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH(vc, 15); + val &=3D ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; + } mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); =20 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, @@ -676,6 +738,24 @@ static void mipi_csis_set_params(struct mipi_csis_devi= ce *csis, MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); } =20 +static int mipi_csis_get_sysreg(struct mipi_csis_device *csis) +{ + unsigned int args; + + if (csis->info->version !=3D MIPI_CSIS_V4_3) + return 0; + + csis->sysreg_map =3D syscon_regmap_lookup_by_phandle_args( + csis->dev->of_node, "samsung,syscon-csis", 1, &args); + + if (IS_ERR(csis->sysreg_map)) + return PTR_ERR(csis->sysreg_map); + + csis->phy_rst_off =3D args; + + return 0; +} + static int mipi_csis_clk_enable(struct mipi_csis_device *csis) { return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); @@ -715,11 +795,71 @@ static int mipi_csis_clk_get(struct mipi_csis_device = *csis) return ret; } =20 +static void mipi_csis_dphy_reset_release_v4_3(struct mipi_csis_device *csi= s) +{ + unsigned int idx =3D 0, val =3D 0x0; + + /* There are 4 CSIs per each D-PHY i/f */ + idx =3D csis->vc; + + regmap_read(csis->sysreg_map, csis->phy_rst_off, &val); + + val &=3D ~FSD_CSIS_RESETEN_DPHY_MASK_V4_3(idx); + regmap_write(csis->sysreg_map, csis->phy_rst_off, val); + + usleep_range(500, 1000); + + val |=3D FSD_CSIS_RESETEN_DPHY_MASK_V4_3(idx); + regmap_write(csis->sysreg_map, csis->phy_rst_off, val); +} + +static void mipi_csis_dphy_init_v4_3(struct mipi_csis_device *csis) +{ + u32 val =3D 0; + + mipi_csis_dphy_reset_release_v4_3(csis); + + val =3D readl(csis->regs + MIPI_CSIS_DPHY_SCTRL_H); + + val |=3D MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_EN; + val |=3D MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_MAX_SKEW_CODE_CTRL; + writel(val, csis->regs + MIPI_CSIS_DPHY_SCTRL_H); +} + +static void mipi_csis_set_vc_passing(struct mipi_csis_device *csis) +{ + u32 val; + unsigned int vc =3D csis->vc; + + val =3D readl(csis->regs + MIPI_CSIS_VC_PASSING_REG); + + val &=3D ~MIPI_CSIS_VC_PASSING_MASK; + val |=3D MIPI_CSIS_VC_PASSING(vc); + val |=3D MIPI_CSIS_VC_PASSING_EN; + writel(val, csis->regs + MIPI_CSIS_VC_PASSING_REG); +} + +static void mipi_csis_get_irq_status(struct mipi_csis_device *csis, + unsigned int *sts) +{ + *sts =3D readl(csis->regs + MIPI_CSIS_INT_SRC1); +} + +static void mipi_csis_clear_irq_status(struct mipi_csis_device *csis, + unsigned int *sts) +{ + writel(*sts, csis->regs + MIPI_CSIS_INT_SRC1); +} + static void mipi_csis_start_stream(struct mipi_csis_device *csis, const struct v4l2_mbus_framefmt *format, const struct csis_pix_format *csis_fmt) { mipi_csis_sw_reset(csis); + if (csis->info->version =3D=3D MIPI_CSIS_V4_3) { + mipi_csis_dphy_init_v4_3(csis); + mipi_csis_set_vc_passing(csis); + } mipi_csis_set_params(csis, format, csis_fmt); mipi_csis_system_enable(csis, true); mipi_csis_enable_interrupts(csis, true); @@ -743,6 +883,31 @@ static void mipi_csis_queue_event_sof(struct mipi_csis= _device *csis) v4l2_event_queue(csis->sd.devnode, &event); } =20 +static irqreturn_t mipi_csis_irq_handler_v4_3(int irq, void *dev_id) +{ + struct mipi_csis_device *csis =3D dev_id; + unsigned long flags; + u32 status; + unsigned int i; + + status =3D mipi_csis_read(csis, MIPI_CSIS_INT_SRC); + + spin_lock_irqsave(&csis->slock, flags); + if ((status & MIPI_CSIS_INT_SRC_ERRORS)) { + for (i =3D 0; i < MIPI_CSIS_INT_SRC_NUM_EVENTS_V4_3; i++) { + struct mipi_csis_event *event =3D &csis->events[i]; + + if (status & event->mask) + event->counter++; + } + } + spin_unlock_irqrestore(&csis->slock, flags); + + mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); + + return IRQ_NONE; +} + static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) { struct mipi_csis_device *csis =3D dev_id; @@ -950,6 +1115,34 @@ static void mipi_csis_debugfs_exit(struct mipi_csis_d= evice *csis) * V4L2 subdev operations */ =20 +static int mipi_csis_get_vc(struct mipi_csis_device *csis) +{ + struct v4l2_mbus_frame_desc fd =3D { }; + int ret; + + ret =3D v4l2_subdev_call(csis->source.sd, pad, get_frame_desc, csis->sour= ce.pad->index, &fd); + if (ret < 0 && ret !=3D -ENOIOCTLCMD) { + dev_err(csis->dev, "get_frame_desc failed on source subdev\n"); + return ret; + } + + /* If remote subdev does not implement ..get_frame_desc default to VC0 */ + if (ret =3D=3D -ENOIOCTLCMD) + return 0; + + if (fd.type !=3D V4L2_MBUS_FRAME_DESC_TYPE_CSI2) { + dev_err(csis->dev, "get_frame_desc returned invalid bus type %d\n", fd.t= ype); + return -EINVAL; + } + + if (!fd.num_entries) { + dev_err(csis->dev, "get_frame_desc returned zero enteries\n"); + return -EINVAL; + } + + return fd.entry[0].bus.csi2.vc; +} + static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev = *sdev) { return container_of(sdev, struct mipi_csis_device, sd); @@ -963,8 +1156,6 @@ static int mipi_csis_s_stream(struct v4l2_subdev *sd, = int enable) struct v4l2_subdev_state *state; int ret; =20 - csis->vc =3D 0; - if (!enable) { v4l2_subdev_disable_streams(csis->source.sd, csis->source.pad->index, BIT(0)); @@ -1015,6 +1206,39 @@ static int mipi_csis_s_stream(struct v4l2_subdev *sd= , int enable) return ret; } =20 +static void mipi_csis_read_vc_frame_counter(struct mipi_csis_device *csis, + u32 *current_frame_counter) +{ + unsigned int vc =3D csis->vc; + *current_frame_counter =3D readl(csis->regs + MIPI_CSIS_FRAME_COUNTER_CH(= vc)); +} + +static long mipi_csis_command(struct v4l2_subdev *sd, unsigned int cmd, vo= id *arg) +{ + struct mipi_csis_device *csis =3D sd_to_mipi_csis_device(sd); + long ret =3D 0; + + switch (cmd) { + case 1: + mipi_csis_system_enable(csis, true); + break; + case 2: + mipi_csis_get_irq_status(csis, arg); + break; + case 3: + mipi_csis_clear_irq_status(csis, arg); + break; + case 5: + mipi_csis_read_vc_frame_counter(csis, arg); + break; + default: + dev_err(csis->dev, "Invalid command\n"); + ret =3D -1; + } + + return ret; +} + static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) @@ -1122,6 +1346,7 @@ static int mipi_csis_set_fmt(struct v4l2_subdev *sd, static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int p= ad, struct v4l2_mbus_frame_desc *fd) { + struct mipi_csis_device *csis =3D sd_to_mipi_csis_device(sd); struct v4l2_mbus_frame_desc_entry *entry =3D &fd->entry[0]; const struct csis_pix_format *csis_fmt; const struct v4l2_mbus_framefmt *fmt; @@ -1143,7 +1368,7 @@ static int mipi_csis_get_frame_desc(struct v4l2_subde= v *sd, unsigned int pad, =20 entry->flags =3D 0; entry->pixelcode =3D csis_fmt->code; - entry->bus.csi2.vc =3D 0; + entry->bus.csi2.vc =3D csis->vc; entry->bus.csi2.dt =3D csis_fmt->data_type; =20 return 0; @@ -1198,6 +1423,7 @@ static const struct v4l2_subdev_core_ops mipi_csis_co= re_ops =3D { .log_status =3D mipi_csis_log_status, .subscribe_event =3D mipi_csis_subscribe_event, .unsubscribe_event =3D v4l2_event_subdev_unsubscribe, + .command =3D mipi_csis_command, }; =20 static const struct v4l2_subdev_video_ops mipi_csis_video_ops =3D { @@ -1232,6 +1458,7 @@ static int mipi_csis_link_setup(struct media_entity *= entity, struct v4l2_subdev *sd =3D media_entity_to_v4l2_subdev(entity); struct mipi_csis_device *csis =3D sd_to_mipi_csis_device(sd); struct v4l2_subdev *remote_sd; + int ret; =20 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, local_pad->entity->name); @@ -1248,6 +1475,14 @@ static int mipi_csis_link_setup(struct media_entity = *entity, =20 csis->source.sd =3D remote_sd; csis->source.pad =3D remote_pad; + + ret =3D mipi_csis_get_vc(csis); + + if (ret < 0) + return -EBUSY; + + csis->vc =3D ret; + } else { csis->source.sd =3D NULL; csis->source.pad =3D NULL; @@ -1472,6 +1707,10 @@ static int mipi_csis_probe(struct platform_device *p= dev) if (irq < 0) return irq; =20 + ret =3D mipi_csis_get_sysreg(csis); + if (ret < 0) + return ret; + ret =3D mipi_csis_phy_init(csis); if (ret < 0) return ret; @@ -1570,6 +1809,15 @@ static const struct of_device_id mipi_csis_of_match[= ] =3D { .irq_flag =3D 0, .irq_handler =3D mipi_csis_irq_handler, }, + }, { + .compatible =3D "tesla,fsd-mipi-csi2", + .data =3D &(const struct mipi_csis_info){ + .version =3D MIPI_CSIS_V4_3, + .num_clocks =3D 2, + .clk_names =3D { "aclk", "pclk"}, + .irq_flag =3D IRQF_SHARED, + .irq_handler =3D mipi_csis_irq_handler_v4_3, + }, }, { /* sentinel */ }, }; --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with 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20250814141047epsmtip2d40283acf8de0531ae8149c6c2120968~bp3-gNYA41818718187epsmtip2a; Thu, 14 Aug 2025 14:10:47 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller Date: Thu, 14 Aug 2025 19:39:41 +0530 Message-ID: <20250814140943.22531-11-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141051epcas5p14dccee388087372973988aeebcb872cf X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141051epcas5p14dccee388087372973988aeebcb872cf References: <20250814140943.22531-1-inbaraj.e@samsung.com> Document bindings for the FSD CSIS DMA controller. Signed-off-by: Inbaraj E --- .../bindings/media/tesla,fsd-csis-media.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/tesla,fsd-csis-= media.yaml diff --git a/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.y= aml b/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml new file mode 100644 index 000000000000..ce6c2e58ed4e --- /dev/null +++ b/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/tesla,fsd-csis-media.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD SoC MIPI CSI-2 DMA (Bridge device) receiver + +maintainers: + - Inbaraj E + +description: |- + The FSD MIPI CSI-2 (Camera Serial Interface 2) have internal DMA engine = to + capture frames originating from the sensor. + +properties: + compatible: + const: tesla,fsd-csis-media + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: aclk + - const: pclk + - const: pll + + iommus: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - iommus + - port + +additionalProperties: false + +examples: + - | + #include + #include + + csi0: csi@12641000 { + compatible =3D "tesla,fsd-csis-media"; + reg =3D <0x12661000 0x44c>; + interrupts =3D ; + clocks =3D <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>, + <&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>, + <&clock_csi CAM_CSI_PLL>; + clock-names =3D "aclk", "pclk", "pll"; + iommus =3D <&smmu_isp 0x0 0x0>; + + port { + csi_in_0: endpoint { + remote-endpoint =3D <&mipi_csis_0_out>; + }; + }; + }; + +... --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34D0D26FA7B for ; Mon, 18 Aug 2025 04:38:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755491904; cv=none; b=HjwraNngv7x9dGE2KuV1fo0icpmf+FACRXO6PcrhACT67u47gbxLX9yuEvL/26+Ap+nPPCmHHNWw1bO48F5C0wbJkEig9VK0XeWQ9B5ZNaMK/b3gzQo+rL7F0yCMESTw9/R1AA+g4cv3XM4yPhg+Rur/jMgyQt7xgDr8wIeb/zM= ARC-Message-Signature: i=1; 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Thu, 14 Aug 2025 14:10:57 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250814141053epsmtip2b31baf764fde081c646d3e1c84b1b4d6~bp4EsmoYH1850318503epsmtip2S; Thu, 14 Aug 2025 14:10:52 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 11/12] arm64: defconfig: Enable FSD CSIS DMA driver Date: Thu, 14 Aug 2025 19:39:42 +0530 Message-ID: <20250814140943.22531-12-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141057epcas5p21ca33641e42164886dc1bf404237876d X-Msg-Generator: CA Content-Type: text/plain; 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Signed-off-by: Inbaraj E --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58f87d09366c..7f7e1fadb74f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -878,6 +878,7 @@ CONFIG_VIDEO_RENESAS_VSP1=3Dm CONFIG_VIDEO_RCAR_DRIF=3Dm CONFIG_VIDEO_ROCKCHIP_RGA=3Dm CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=3Dm +CONFIG_VIDEO_FSD_CSIS=3Dm CONFIG_VIDEO_SAMSUNG_S5P_JPEG=3Dm CONFIG_VIDEO_SAMSUNG_S5P_MFC=3Dm CONFIG_VIDEO_SUN6I_CSI=3Dm --=20 2.49.0 From nobody Sat Oct 4 15:59:03 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 976B0271445 for ; Mon, 18 Aug 2025 04:38:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 18 Aug 2025 04:38:24 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.90]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4c50Mg5Gk7z6B9mK; Mon, 18 Aug 2025 04:38:23 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250814141103epcas5p14516cbe45c21d28ba9e231da99940aa1~bp4OIZ_Uc1324813248epcas5p1-; Thu, 14 Aug 2025 14:11:03 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250814141058epsmtip27fc64b097a08fb133f27985964aeaf16~bp4KKtC_91850318503epsmtip2T; Thu, 14 Aug 2025 14:10:58 +0000 (GMT) From: Inbaraj E To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, s.hauer@pengutronix.de, shawnguo@kernel.org, cw00.choi@samsung.com, rmfrfs@gmail.com, laurent.pinchart@ideasonboard.com, martink@posteo.de, mchehab@kernel.org, linux-fsd@tesla.com, will@kernel.org, catalin.marinas@arm.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alim.akhtar@samsung.com, linux-samsung-soc@vger.kernel.org, kernel@puri.sm, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Inbaraj E Subject: [PATCH v2 12/12] media: fsd-csis: Add support for FSD CSIS DMA Date: Thu, 14 Aug 2025 19:39:43 +0530 Message-ID: <20250814140943.22531-13-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250814140943.22531-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250814141103epcas5p14516cbe45c21d28ba9e231da99940aa1 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250814141103epcas5p14516cbe45c21d28ba9e231da99940aa1 References: <20250814140943.22531-1-inbaraj.e@samsung.com> FSD CSIS IP bundles DMA engine for receiving frames from MIPI-CSI2 bus. Add support internal DMA controller to capture the frames. Signed-off-by: Inbaraj E --- MAINTAINERS | 8 + drivers/media/platform/samsung/Kconfig | 1 + drivers/media/platform/samsung/Makefile | 1 + .../media/platform/samsung/fsd-csis/Kconfig | 18 + .../media/platform/samsung/fsd-csis/Makefile | 3 + .../platform/samsung/fsd-csis/fsd-csis.c | 1709 +++++++++++++++++ 6 files changed, 1740 insertions(+) create mode 100644 drivers/media/platform/samsung/fsd-csis/Kconfig create mode 100644 drivers/media/platform/samsung/fsd-csis/Makefile create mode 100644 drivers/media/platform/samsung/fsd-csis/fsd-csis.c diff --git a/MAINTAINERS b/MAINTAINERS index bd62ad58a47f..1e17fb0581d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3334,6 +3334,14 @@ S: Maintained F: Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml F: drivers/media/platform/samsung/s5p-mfc/ =20 +ARM/SAMSUNG FSD BRIDGE DRIVER +M: Inbaraj E +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml +F: drivers/media/platform/samsung/fsd-csis/fsd-csis.c + ARM/SOCFPGA ARCHITECTURE M: Dinh Nguyen S: Maintained diff --git a/drivers/media/platform/samsung/Kconfig b/drivers/media/platfor= m/samsung/Kconfig index 0e34c5fc1dfc..4cebe2ae24a3 100644 --- a/drivers/media/platform/samsung/Kconfig +++ b/drivers/media/platform/samsung/Kconfig @@ -4,6 +4,7 @@ comment "Samsung media platform drivers" =20 source "drivers/media/platform/samsung/exynos-gsc/Kconfig" source "drivers/media/platform/samsung/exynos4-is/Kconfig" +source "drivers/media/platform/samsung/fsd-csis/Kconfig" source "drivers/media/platform/samsung/s3c-camif/Kconfig" source "drivers/media/platform/samsung/s5p-g2d/Kconfig" source "drivers/media/platform/samsung/s5p-jpeg/Kconfig" diff --git a/drivers/media/platform/samsung/Makefile b/drivers/media/platfo= rm/samsung/Makefile index 21fea3330e4b..fde1b9626713 100644 --- a/drivers/media/platform/samsung/Makefile +++ b/drivers/media/platform/samsung/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y +=3D exynos-gsc/ obj-y +=3D exynos4-is/ +obj-y +=3D fsd-csis/ obj-y +=3D s3c-camif/ obj-y +=3D s5p-g2d/ obj-y +=3D s5p-jpeg/ diff --git a/drivers/media/platform/samsung/fsd-csis/Kconfig b/drivers/medi= a/platform/samsung/fsd-csis/Kconfig new file mode 100644 index 000000000000..99803e924682 --- /dev/null +++ b/drivers/media/platform/samsung/fsd-csis/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# FSD MIPI CSI-2 Rx controller configurations + +config VIDEO_FSD_CSIS + tristate "FSD SoC MIPI-CSI2 media controller driver" + depends on VIDEO_DEV && VIDEO_V4L2_SUBDEV_API + depends on HAS_DMA + depends on OF + select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE + help + This is a video4linux2 driver for FSD SoC MIPI-CSI2 Rx. + The driver provides interface for capturing frames. + + To compile this driver as a module, choose M here. The module + will be called fsd-csis. + diff --git a/drivers/media/platform/samsung/fsd-csis/Makefile b/drivers/med= ia/platform/samsung/fsd-csis/Makefile new file mode 100644 index 000000000000..eba8c0c6a7cc --- /dev/null +++ b/drivers/media/platform/samsung/fsd-csis/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_VIDEO_FSD_CSIS) +=3D fsd-csis.o diff --git a/drivers/media/platform/samsung/fsd-csis/fsd-csis.c b/drivers/m= edia/platform/samsung/fsd-csis/fsd-csis.c new file mode 100644 index 000000000000..74f46038d506 --- /dev/null +++ b/drivers/media/platform/samsung/fsd-csis/fsd-csis.c @@ -0,0 +1,1709 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * + * FSD CSIS V4L2 Capture driver for FSD SoC. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define FSD_CSIS_DMA_COHERENT_MASK_SIZE 32 +#define FSD_CSIS_NB_MIN_CH 2 +#define FSD_CSIS_NB_VC 4 +#define FSD_CSIS_MEDIA_NUM_PADS 2 +#define FSD_CSIS_NB_DMA_OUT_CH 8 +#define FSD_CSIS_MAX_VC 4 +#define FSD_CSIS_NB_CLOCK 2 +#define FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS 2 +#define FSD_CSIS_DMA_LINE_ALIGN_SIZE 128 +#define FSD_CSIS_DMA_CH_OFFSET 0x100 + +/** + * (Interrupt Source & mask register 1) + */ +#define FSD_CSIS_DMA_OTF_OVERLAP_MASK GENMASK(17, 14) +#define FSD_CSIS_DMA_ABORT_DONE_MASK BIT(13) +#define FSD_CSIS_DMA_ERROR_MASK BIT(12) +#define FSD_CSIS_INT_SRC1_ERR_ALL_MASK (FSD_CSIS_DMA_ERROR_MASK | \ + FSD_CSIS_DMA_ABORT_DONE_MASK | \ + FSD_CSIS_DMA_ERROR_MASK) +#define FDS_CSIS_DMA_FRM_END_MASK GENMASK(11, 8) +#define FSD_CSIS_DMA_FRM_START_MASK GENMASK(7, 4) +#define FSD_CSIS_LINE_END_MASK GENMASK(3, 0) +#define FSD_CSIS_DMA_CH0_MASK 0x4111U + +/* DMA Reg offsets */ +#define FSD_CSIS_DMA0_CTRL 0x0 +#define FSD_CSIS_DMA_CTRL(vc) (FSD_CSIS_DMA0_CTRL + (vc) * FSD_CSIS_DMA_CH= _OFFSET) +#define FSD_CSIS_DMA_DISABLE BIT(0) + +#define FSD_CSIS_DMA0_FMT 0x4 +#define FSD_CSIS_DMA_FMT(vc) (FSD_CSIS_DMA0_FMT + (vc) * FSD_CSIS_DMA_CH_O= FFSET) +#define FSD_CSIS_DMA_DIM BIT(15) +#define FSD_CSIS_DMA_DUMP BIT(13) + +#define FSD_CSIS_DMA0_ADDR1 0x10 +#define FSD_CSIS_DMA_ADDR1(vc) (FSD_CSIS_DMA0_ADDR1 + (vc) * FSD_CSIS_DMA_= CH_OFFSET) + +#define FSD_CSIS_DMA0_ACT_CTRL 0x30 +#define FSD_CSIS_DMA_ACT_CTRL(vc) (FSD_CSIS_DMA0_ACT_CTRL + (vc) * FSD_CSI= S_DMA_CH_OFFSET) +#define FSD_CSIS_ACTIVE_DMA_PACK_MASK GENMASK(17, 16) +#define FSD_CSIS_ACTIVE_DMA_PACK(n) ((n) << 16) +#define FSD_CSIS_ACTIVE_DMA_FRAMEPTR_MASK GENMASK(4, 2) + +#define FSD_CSIS_DMA_ERR_CODE 0x404 +#define FSD_CSIS_DMAFIFO_FULL_MASK BIT_MASK(5) +#define FSD_CSIS_TRXFIFO_FULL_MASK BIT_MASK(4) + +#define FSD_CSIS_DMA_CLK_CTRL 0x408 +#define FSD_CSIS_DMA_CLK_GATE_TRAIL_MASK GENMASK(4, 1) +#define FSD_CSIS_DMA_CLK_GATE_TRAIL(n) ((n) << 1) +#define FSD_CSIS_DMA_CLK_GATE_EN BIT(0) + +enum CSIS_DMA_PACK { + DMA_PACK_NORMAL, + DMA_PACK_10, + DMA_PACK_12, + DMA_PACK_14, + DMA_PACK_18, + DMA_PACK_20, +}; + +static const char * const fsd_csis_clk_id[] =3D { + "aclk", + "pclk", +}; + +struct fsd_csis_pixfmt { + u32 fourcc; + const u32 *codes; + int bpp; + bool is_yuv; +}; + +struct fsd_csis_vb2_buffer { + struct vb2_v4l2_buffer vb; + struct list_head list; + const struct fsd_csis_pixfmt *fmt; + unsigned long sequence_num; +}; + +struct fsd_csis { + struct device *dev; + const struct fsd_csis_info *info; + struct clk_bulk_data *clks; + struct clk *pll; + struct media_device mdev; + struct v4l2_device v4l2_dev; + struct v4l2_async_notifier notifier; + struct media_pipeline pipe; + + /* source node */ + struct { + struct v4l2_subdev *subdev; + struct media_pad *pad; + } source; + + /* Internal subdev */ + struct { + struct v4l2_subdev sd; + struct media_pad pad[FSD_CSIS_MEDIA_NUM_PADS]; + } subdev; + + struct video_device *vdev; + struct media_pad vdev_pad; + struct vb2_queue q; + struct mutex vdev_mutex; + struct mutex mutex_csis_dma_reg; + spinlock_t lock_buf; + void __iomem *dma_base; + int irq; + u64 frame_addr[FSD_CSIS_NB_DMA_OUT_CH]; + struct fsd_csis_vb2_buffer *frame[FSD_CSIS_NB_DMA_OUT_CH]; + struct v4l2_pix_format vdev_fmt; + const struct fsd_csis_pixfmt *vdev_cc; + struct v4l2_rect vdev_compose; + u32 num_reqbufs; + u8 prev_dma_ptr; + u8 current_dma_ptr; + u8 number_of_ready_bufs; + u32 prev_frame_counter; + u32 current_frame_counter; + unsigned int num_active_fmt; + struct list_head ready_q; + spinlock_t q_lock; + unsigned int current_vc; + unsigned long sequence; + u32 dma_error; + struct mutex mutex; + int is_streaming; +}; + +static inline u32 get_bits(u32 value, u32 mask) +{ + return (((value) & (mask)) >> (ffs(mask) - 1)); +} + +static inline u32 bytes_per_line(u32 width, int bpp) +{ + return (ALIGN((width * bpp), FSD_CSIS_DMA_LINE_ALIGN_SIZE) >> 3); +} + +static inline uint8_t fsd_csis_current_dma_ptr(struct fsd_csis *csis) + +{ + return (readl(csis->dma_base + FSD_CSIS_DMA_ACT_CTRL(csis->current_vc)) + & 0x01C) >> 2; +} + +#define FSD_CSIS_MODULE_NAME "fsd-csis-media" +#define FSD_CSIS_MODULE_VERSION "0.0.1" + +#define FSD_CSIS_DEF_MBUS_CODE MEDIA_BUS_FMT_RGB888_1X24 +#define FSD_CSIS_DEF_PIX_FORMAT V4L2_PIX_FMT_RGB24 +#define FSD_CSIS_DEF_PIX_WIDTH 1280 +#define FSD_CSIS_DEF_PIX_HEIGHT 964 + +#define FSD_CSIS_PAD_SINK 0 +#define FSD_CSIS_PAD_SRC 1 +#define FSD_CSIS_PADS_NUM 2 + +#define FSD_CSIS_BUS_FMTS(fmt...) ((const u32[]) {fmt, 0 }) + +static const struct v4l2_mbus_framefmt fsd_csis_default_format =3D { + .width =3D 640, + .height =3D 480, + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .field =3D V4L2_FIELD_NONE, +}; + +static const struct fsd_csis_pixfmt pixel_formats[] =3D { + /* YUV formats start here */ + { + .fourcc =3D V4L2_PIX_FMT_UYVY, + .codes =3D FSD_CSIS_BUS_FMTS( + MEDIA_BUS_FMT_UYVY8_2X8, + MEDIA_BUS_FMT_UYVY8_1X16 + ), + .is_yuv =3D true, + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_YUYV, + .codes =3D FSD_CSIS_BUS_FMTS( + MEDIA_BUS_FMT_YUYV8_2X8, + MEDIA_BUS_FMT_YUYV8_1X16 + ), + .is_yuv =3D true, + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SBGGR8, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SBGGR8_1X8), + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_SGBRG8, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGBRG8_1X8), + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_SGRBG8, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGRBG8_1X8), + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_SRGGB8, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SRGGB8_1X8), + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_SBGGR10, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SBGGR10_1X10), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SGBRG10, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGBRG10_1X10), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SGRBG10, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGRBG10_1X10), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SRGGB10, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SRGGB10_1X10), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SBGGR12, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SBGGR12_1X12), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SGBRG12, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGBRG12_1X12), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SGRBG12, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGRBG12_1X12), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SRGGB12, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SRGGB12_1X12), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SBGGR14, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SBGGR14_1X14), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SGBRG14, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGBRG14_1X14), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SGRBG14, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGRBG14_1X14), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_SRGGB14, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SRGGB14_1X14), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_GREY, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_Y8_1X8), + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_Y10, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_Y10_1X10), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_Y12, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_Y12_1X12), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_Y14, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_Y14_1X14), + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_RGB24, + .codes =3D FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_RGB888_1X24), + .bpp =3D 24, + } +}; + +static void fsd_csis_dma_enable(struct fsd_csis *csis, bool en_dma) +{ + unsigned int dma_ctrl, vc =3D csis->current_vc; + + dma_ctrl =3D readl(csis->dma_base + FSD_CSIS_DMA_CTRL(vc)); + dma_ctrl |=3D FSD_CSIS_DMA_DISABLE; + + if (en_dma) + dma_ctrl &=3D ~FSD_CSIS_DMA_DISABLE; + + writel(dma_ctrl, csis->dma_base + FSD_CSIS_DMA_CTRL(vc)); +} + +static void fsd_csis_set_dma_clk(struct fsd_csis *csis) +{ + unsigned int dma_clk_ctrl; + + dma_clk_ctrl =3D readl(csis->dma_base + FSD_CSIS_DMA_CLK_CTRL); + + dma_clk_ctrl &=3D ~FSD_CSIS_DMA_CLK_GATE_EN; + dma_clk_ctrl &=3D ~FSD_CSIS_DMA_CLK_GATE_TRAIL_MASK; + dma_clk_ctrl |=3D FSD_CSIS_DMA_CLK_GATE_TRAIL(0x7); + + writel(dma_clk_ctrl, csis->dma_base + FSD_CSIS_DMA_CLK_CTRL); +} + +static void fsd_csis_set_pack(struct fsd_csis *csis, u32 vc, + enum CSIS_DMA_PACK dma_pack) +{ + u32 dma_fmt; + + dma_fmt =3D readl(csis->dma_base + FSD_CSIS_DMA_CTRL(vc)); + dma_fmt &=3D ~FSD_CSIS_ACTIVE_DMA_PACK_MASK; + dma_fmt |=3D FSD_CSIS_ACTIVE_DMA_PACK(dma_pack); + writel(dma_fmt, csis->dma_base + FSD_CSIS_DMA_CTRL(vc)); +} + +static void fsd_csis_set_dma_dump(struct fsd_csis *csis, unsigned int vc, + bool set_dump) +{ + u32 dma_fmt; + + dma_fmt =3D readl(csis->dma_base + FSD_CSIS_DMA_CTRL(vc)); + dma_fmt &=3D ~FSD_CSIS_DMA_DUMP; + + if (set_dump) + dma_fmt |=3D FSD_CSIS_DMA_DUMP; + + writel(dma_fmt, csis->dma_base + FSD_CSIS_DMA_CTRL(vc)); +} + +static void fsd_csis_set_dma_dimension(struct fsd_csis *csis, u32 vc, bool= set_dim) +{ + u32 dma_fmt; + + dma_fmt =3D readl(csis->dma_base + FSD_CSIS_DMA_FMT(vc)); + dma_fmt &=3D ~FSD_CSIS_DMA_DIM; + + if (set_dim) + dma_fmt |=3D FSD_CSIS_DMA_DIM; + + writel(dma_fmt, csis->dma_base + FSD_CSIS_DMA_FMT(vc)); +} + +static void fsd_csis_set_dma_format(struct fsd_csis *csis, + const struct fsd_csis_pixfmt *cc) +{ + unsigned int fourcc =3D cc->fourcc; + + switch (fourcc) { + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_10); + break; + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_12); + break; + case V4L2_PIX_FMT_SBGGR14P: + fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_14); + break; + case V4L2_PIX_FMT_BGR666: + fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_18); + break; + case V4L2_PIX_FMT_UYVY: + fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_NORMAL); + break; + default: + dev_err(csis->dev, "Set DMA format %x not supported\n", fourcc); + break; + } + + fsd_csis_set_dma_dump(csis, csis->current_vc, false); + fsd_csis_set_dma_dimension(csis, csis->current_vc, false); +} + +static inline struct fsd_csis *notifier_to_csis(struct v4l2_async_notifier= *n) +{ + return container_of(n, struct fsd_csis, notifier); +} + +static int fsd_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct fsd_csis *csis =3D vb2_get_drv_priv(vq); + struct v4l2_pix_format *pix =3D &csis->vdev_fmt; + unsigned int size =3D pix->sizeimage; + + if (*nplanes) { + if (sizes[0] < size) + return -EINVAL; + size =3D sizes[0]; + } + + *nplanes =3D 1; + sizes[0] =3D size; + + dev_info(csis->dev, "nbuffers %d size %d\n", *nbuffers, sizes[0]); + + return 0; +} + +static int fsd_buffer_prepare(struct vb2_buffer *vb) +{ + struct fsd_csis *csis =3D vb2_get_drv_priv(vb->vb2_queue); + struct fsd_csis_vb2_buffer *buf =3D container_of(vb, struct fsd_csis_vb2_= buffer, + vb.vb2_buf); + unsigned long size; + + if (WARN_ON(!csis->vdev_cc)) + return -EINVAL; + + if (vb2_plane_size(vb, 0) < size) { + dev_info(csis->dev, "Data will not fit into plane (%lu < %lu)\n", + vb2_plane_size(vb, 0), size); + return -EINVAL; + } + + vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size); + + return 0; +} + +static void fsd_buffer_queue(struct vb2_buffer *vb) +{ + unsigned long flags; + struct fsd_csis *csis =3D vb2_get_drv_priv(vb->vb2_queue); + struct fsd_csis_vb2_buffer *buf =3D + container_of(vb, struct fsd_csis_vb2_buffer, vb.vb2_buf); + + spin_lock_irqsave(&csis->q_lock, flags); + list_add_tail(&buf->list, &csis->ready_q); + buf->sequence_num =3D csis->sequence++; + spin_unlock_irqrestore(&csis->q_lock, flags); +} + +static void fsd_csis_dma_set_vid_base_addr(struct fsd_csis *csis, int frm_= no, + unsigned long addr) +{ + unsigned int dma_addr; + + dma_addr =3D FSD_CSIS_DMA_ADDR1(csis->current_vc); + dma_addr =3D dma_addr + (frm_no * 4); + mutex_lock(&csis->mutex_csis_dma_reg); + writel(addr, csis->dma_base + dma_addr); + mutex_unlock(&csis->mutex_csis_dma_reg); +} + +static void fsd_csis_add_to_ring_buffer(struct fsd_csis *csis, + struct fsd_csis_vb2_buffer *buf, uint8_t index) +{ + uint8_t modulo_addr; + unsigned int i; + + for (i =3D 0; i < FSD_CSIS_NB_DMA_OUT_CH; + i +=3D FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS) { + modulo_addr =3D (index + i) % FSD_CSIS_NB_DMA_OUT_CH; + csis->frame[modulo_addr] =3D buf; + csis->frame_addr[modulo_addr] =3D + vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); + fsd_csis_dma_set_vid_base_addr(csis, modulo_addr, + csis->frame_addr[modulo_addr]); + } +} + +static int fsd_csis_get_vc(struct fsd_csis *csis) +{ + struct v4l2_mbus_frame_desc fd =3D { }; + struct media_pad *remote_pad; + int ret; + + remote_pad =3D media_pad_remote_pad_unique(&csis->subdev.pad[FSD_CSIS_PAD= _SINK]); + ret =3D v4l2_subdev_call(csis->source.subdev, pad, get_frame_desc, remote= _pad->index, &fd); + if (ret < 0 && ret !=3D -ENOIOCTLCMD) { + dev_err(csis->dev, "get_frame_desc failed on source subdev\n"); + return ret; + } + + /* If remote subdev does not implement ..get_frame_desc default to VC0 */ + if (ret =3D=3D -ENOIOCTLCMD) + return 0; + + if (!fd.num_entries) { + dev_err(csis->dev, "get_frame_desc returned zero entries\n"); + return -EINVAL; + } + + return fd.entry[0].bus.csi2.vc; +} + +static int fsd_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct fsd_csis *csis =3D vb2_get_drv_priv(q); + struct fsd_csis_vb2_buffer *buf, *tmp; + unsigned long flags; + uint8_t i; + int ret; + + mutex_lock(&csis->mdev.graph_mutex); + + ret =3D __video_device_pipeline_start(csis->vdev, &csis->pipe); + if (ret) + goto err_unlock; + + ret =3D fsd_csis_get_vc(csis); + + if (ret < 0) + goto err_unlock; + + csis->current_vc =3D ret; + + ret =3D v4l2_subdev_enable_streams(&csis->subdev.sd, FSD_CSIS_PAD_SRC, + BIT(0)); + if (ret) { + dev_err(csis->dev, "stream on failed in subdev\n"); + goto err_stop; + } + + mutex_unlock(&csis->mdev.graph_mutex); + fsd_csis_set_dma_clk(csis); + fsd_csis_set_dma_format(csis, csis->vdev_cc); + + for (i =3D 0; i < FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS; i++) { + + spin_lock_irqsave(&csis->q_lock, flags); + if (list_empty(&csis->ready_q)) { + spin_unlock_irqrestore(&csis->q_lock, flags); + dev_err(csis->dev, "Failed to fill buffer address!\n"); + return -EIO; + } + + buf =3D list_entry(csis->ready_q.next, struct fsd_csis_vb2_buffer, list); + list_del(&buf->list); + fsd_csis_add_to_ring_buffer(csis, buf, i); + spin_unlock_irqrestore(&csis->q_lock, flags); + } + + fsd_csis_dma_enable(csis, true); + + return 0; +err_stop: + v4l2_subdev_disable_streams(&csis->subdev.sd, FSD_CSIS_PAD_SRC, + BIT(0)); + __video_device_pipeline_stop(csis->vdev); +err_unlock: + mutex_unlock(&csis->mdev.graph_mutex); + + spin_lock_irqsave(&csis->q_lock, flags); + list_for_each_entry_safe(buf, tmp, &csis->ready_q, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + } + spin_unlock_irqrestore(&csis->q_lock, flags); + + dev_err(csis->dev, "pipeline start failed with %d\n", ret); + return ret; +} + +/** + * fsd_stop_streaming() - stop streaming for CSI context + * @q: pointer to vb2_queue in use + * Return: none + */ +static void fsd_stop_streaming(struct vb2_queue *q) +{ + unsigned long flags; + struct fsd_csis *csis =3D vb2_get_drv_priv(q); + struct fsd_csis_vb2_buffer *buf, *tmp; + unsigned int timeout_cnt =3D 0; + int i; + void __iomem *dma_act_ctrl =3D 0; + + fsd_csis_dma_enable(csis, false); + + dma_act_ctrl =3D csis->dma_base + FSD_CSIS_DMA_ACT_CTRL(csis->current_vc); + + while ((readl(dma_act_ctrl) & 0x1) =3D=3D 0x0) { + if (timeout_cnt > 50) { + dev_dbg(csis->dev, "DMA did not finish in 500ms.\n"); + break; + } + usleep_range(10000, 20000); /* Wait min 10ms, max 20ms */ + timeout_cnt++; + } + + mutex_lock(&csis->mdev.graph_mutex); + v4l2_subdev_disable_streams(&csis->subdev.sd, FSD_CSIS_PAD_SRC, + BIT(0)); + __video_device_pipeline_stop(csis->vdev); + mutex_unlock(&csis->mdev.graph_mutex); + /* + * If still DMA operation exists after disabled irq, it will + * update dma_done part in interrupt source register. For next + * streaming session, this could be interpreted as current session's + * first frame done. To prevent this incorrect dma_done receiving, + * clearing interrupt source register here. + */ + + /* Release all active buffers */ + spin_lock_irqsave(&csis->q_lock, flags); + list_for_each_entry_safe(buf, tmp, &csis->ready_q, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } + spin_unlock_irqrestore(&csis->q_lock, flags); + + for (i =3D 0; i < FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS; i++) { + buf =3D csis->frame[i]; + if (buf) + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } +} + +static int fsd_csis_video_open(struct file *file) +{ + struct fsd_csis *csis =3D video_drvdata(file); + int ret; + struct vb2_queue *q =3D &csis->q; + + if (vb2_is_busy(q)) { + dev_err(csis->dev, "device busy\n"); + return -EBUSY; + } + + ret =3D pm_runtime_resume_and_get(csis->dev); + if (ret < 0) + return ret; + + ret =3D v4l2_fh_open(file); + + if (ret) { + dev_err(csis->dev, "v4l2_fh_open failed\n"); + goto err; + } + + return ret; + +err: + pm_runtime_put(csis->dev); + return ret; +} + +static void fsd_csis_irq_worker(struct fsd_csis *csis) +{ + struct fsd_csis_vb2_buffer *buf_from; + struct fsd_csis_vb2_buffer *buf_to; + struct v4l2_subdev *subdev =3D csis->source.subdev; + uint8_t i; + void __iomem *dma_act_ctrl; + unsigned long flags; + + dma_act_ctrl =3D csis->dma_base + FSD_CSIS_DMA_ACT_CTRL(csis->current_vc); + csis->current_dma_ptr =3D readl(dma_act_ctrl); + csis->current_dma_ptr =3D get_bits(csis->current_dma_ptr, + FSD_CSIS_ACTIVE_DMA_FRAMEPTR_MASK); + + v4l2_subdev_call(subdev, core, command, 5, + &csis->current_frame_counter); + + if (csis->dma_error) { + dev_err(csis->dev, "prev_dma: %d, cur_dma: %d, prev_frm: %d, cur_frm: %d= \n", + csis->prev_dma_ptr, csis->current_dma_ptr, + csis->prev_frame_counter, csis->current_frame_counter); + csis->prev_dma_ptr =3D csis->current_dma_ptr; + goto update_prev_counters; + } + + if (csis->current_dma_ptr >=3D csis->prev_dma_ptr) + csis->number_of_ready_bufs =3D + csis->current_dma_ptr - csis->prev_dma_ptr; + else + csis->number_of_ready_bufs =3D + FSD_CSIS_NB_DMA_OUT_CH - csis->prev_dma_ptr + + csis->current_dma_ptr; + + + if ((csis->number_of_ready_bufs >=3D FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS) + || ((csis->current_frame_counter - csis->prev_frame_counter) + >=3D FSD_CSIS_NB_DMA_OUT_CH)) { + /* In case of CSIS_NB_OF_BUFS_ON_DMA_CHANNELS or CSIS_NUM_DMA_OUT_CH num= ber + * of frames delays or more, set how many recent frames are ready to be = read + * in the next interrupt. This cannot be more than + * CSIS_NB_OF_BUFS_ON_DMA_CHANNELS-1 frames. + */ + csis->number_of_ready_bufs =3D FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS - 1; + csis->prev_dma_ptr =3D (csis->current_dma_ptr - + FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS) + & (FSD_CSIS_NB_DMA_OUT_CH - 1); + dev_err(csis->dev, "interrupt delayed %d frames\n", + csis->number_of_ready_bufs); + } + + if (csis->number_of_ready_bufs =3D=3D 0) { + dev_err(csis->dev, "Interrupt burst number_of_ready_bufs: %d\n", + csis->number_of_ready_bufs); + goto update_prev_counters; + } else { + if (csis->number_of_ready_bufs > 1) { + /* + * Interrupt has been missed. Do not populate DMA_ACT_CTRL pointer. + * Notify buffers ready until (DMA_ACT_CTRL - 1) pointer. + * Because,the delayed interrupt might be arrived in DMA active + * time. + */ + csis->number_of_ready_bufs--; + dev_err(csis->dev, "interrupt got delayed %d frames\n", + csis->number_of_ready_bufs); + } + } + + for (i =3D 0; i < csis->number_of_ready_bufs; i++) { + bool is_same_modulo; + + csis->prev_dma_ptr =3D (csis->prev_dma_ptr + 1) % FSD_CSIS_NB_DMA_OUT_CH; + is_same_modulo =3D !((csis->prev_dma_ptr - (csis->current_dma_ptr + 1)) % + FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS); + + spin_lock_irqsave(&csis->q_lock, flags); + + /* + * Before dequeuing buffer from DMA at least + * one buffer should be ready in vb2_queue + */ + if (list_empty(&csis->ready_q)) { + spin_unlock_irqrestore(&csis->q_lock, flags); + csis->prev_dma_ptr =3D csis->current_dma_ptr; + goto update_prev_counters; + + } else { + + buf_from =3D list_entry(csis->ready_q.next, + struct fsd_csis_vb2_buffer, list); + list_del(&buf_from->list); + } + + spin_unlock_irqrestore(&csis->q_lock, flags); + + buf_to =3D csis->frame[csis->prev_dma_ptr]; + + if (is_same_modulo) { + if (csis->current_dma_ptr !=3D fsd_csis_current_dma_ptr(csis)) { + spin_lock_irqsave(&csis->q_lock, flags); + list_add_tail(&buf_from->list, &csis->ready_q); + spin_unlock_irqrestore(&csis->q_lock, flags); + continue; + } + } + + fsd_csis_add_to_ring_buffer(csis, buf_from, csis->prev_dma_ptr); + + if (buf_to) { + buf_to->vb.vb2_buf.timestamp =3D ktime_get_ns(); + vb2_buffer_done(&buf_to->vb.vb2_buf, + VB2_BUF_STATE_DONE); + } + + } + +update_prev_counters: + csis->prev_frame_counter =3D csis->current_frame_counter; + +} + +static irqreturn_t csis_irq_handler(int irq_csis, void *data) +{ + struct fsd_csis *csis =3D data; + struct v4l2_subdev *subdev =3D csis->source.subdev; + unsigned int vc; + unsigned int int_src1 =3D 0x0; + unsigned int int1_err =3D 0x0; + unsigned int dma_error =3D 0x0, dma_err_code =3D 0x0, dma_error_vc =3D 0x= 0; + unsigned int err =3D 0x0; + unsigned int dma_frame_end =3D 0x0, dma_frame_end_vc =3D 0x0, dma_frame_s= tart =3D 0x0; + int i; + + vc =3D csis->current_vc; + + v4l2_subdev_call(subdev, core, command, 2, &int_src1); + int1_err =3D get_bits(int_src1, FSD_CSIS_INT_SRC1_ERR_ALL_MASK); + + dma_frame_start =3D get_bits(int_src1, FSD_CSIS_DMA_FRM_START_MASK); + dma_frame_end =3D get_bits(int_src1, FDS_CSIS_DMA_FRM_END_MASK); + + if (int1_err) { + err =3D get_bits(int_src1, FSD_CSIS_DMA_OTF_OVERLAP_MASK); + if (err) + dev_err(csis->dev, "DMA OTF OVERLAP %x\n", err); + + dma_error =3D get_bits(int_src1, FSD_CSIS_DMA_ERROR_MASK); + + if (dma_error) { + dev_err(csis->dev, "DMA ERROR %x\n", dma_error); + dma_err_code =3D readl(csis->dma_base + FSD_CSIS_DMA_ERR_CODE); + dev_err(csis->dev, "Error code %x", dma_err_code); + } + } + + if (dma_frame_end || dma_error) { + + for (i =3D 0; i < FSD_CSIS_MAX_VC; i++) { + dma_frame_end_vc =3D (dma_frame_end >> i) & 0x01; + if (dma_error) { + dma_error_vc =3D int_src1 & (FSD_CSIS_DMA_CH0_MASK << i); + dma_error_vc |=3D ((dma_err_code & (FSD_CSIS_DMAFIFO_FULL_MASK | + FSD_CSIS_TRXFIFO_FULL_MASK | + 0x01 << i)) << 18); + } + + if (dma_frame_end_vc || dma_error_vc) { + csis->dma_error =3D dma_error_vc; + fsd_csis_irq_worker(csis); + } + } + } + + v4l2_subdev_call(subdev, core, command, 3, &int_src1); + + return IRQ_HANDLED; +} + +static int fsd_csis_video_release(struct file *file) +{ + struct fsd_csis *csis =3D video_drvdata(file); + int ret; + + ret =3D vb2_fop_release(file); + + if (ret) + return ret; + + pm_runtime_put(csis->dev); + + return ret; +} + +static int fsd_csis_video_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct fsd_csis *csis =3D video_drvdata(file); + + strscpy(cap->driver, FSD_CSIS_MODULE_NAME, sizeof(cap->driver)); + strscpy(cap->card, FSD_CSIS_MODULE_NAME, sizeof(cap->card)); + + snprintf(cap->bus_info, sizeof(cap->bus_info), + "platform:%s", dev_name(csis->dev)); + return 0; +} + +static int fsd_csis_video_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + unsigned int index =3D f->index; + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(pixel_formats); i++) { + const struct fsd_csis_pixfmt *fmt =3D &pixel_formats[i]; + + if (f->mbus_code) { + unsigned int j; + + if (!fmt->codes) + continue; + + for (j =3D 0; fmt->codes[j]; j++) { + if (f->mbus_code =3D=3D fmt->codes[j]) + break; + } + + if (!fmt->codes[j]) + continue; + } + + if (index =3D=3D 0) { + f->pixelformat =3D fmt->fourcc; + return 0; + } + + index--; + } + + return -EINVAL; +} + +/* + * Search in the pixel_formats[] array for an entry with the given fourcc + * return it. + */ +static const struct fsd_csis_pixfmt *fsd_csis_find_pixel_format(u32 fourcc) +{ + const struct fsd_csis_pixfmt *fmt; + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(pixel_formats); i++) { + fmt =3D &pixel_formats[i]; + + if (fmt->fourcc =3D=3D fourcc) + return fmt; + } + + return NULL; +} + +/* + * Search in the pixel_formats[] array for an entry with the given media + * bus code and return it. + */ +static const struct fsd_csis_pixfmt *fsd_csis_find_mbus_format(u32 code) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(pixel_formats); i++) { + const struct fsd_csis_pixfmt *fmt =3D &pixel_formats[i]; + unsigned int j; + + if (!fmt->codes) + continue; + + for (j =3D 0; fmt->codes[j]; j++) { + if (code =3D=3D fmt->codes[j]) + return fmt; + } + } + + return NULL; +} + +static int fsd_csis_mbus_fmt_to_pix_fmt(struct v4l2_pix_format *pix, + const struct v4l2_mbus_framefmt *mbus, + const struct fsd_csis_pixfmt *cc) +{ + u32 width; + u32 stride; + + if (!cc) { + cc =3D fsd_csis_find_mbus_format(mbus->code); + if (!cc) + return -EINVAL; + } + + /* Round up width for minimum burst size */ + width =3D round_up(mbus->width, 8); + + /* Round up stride for IDMAC line start address alignment */ + stride =3D round_up((width * cc->bpp) >> 3, 8); + + pix->width =3D width; + pix->height =3D mbus->height; + pix->pixelformat =3D cc->fourcc; + pix->colorspace =3D mbus->colorspace; + pix->xfer_func =3D mbus->xfer_func; + pix->ycbcr_enc =3D mbus->ycbcr_enc; + pix->quantization =3D mbus->quantization; + pix->field =3D mbus->field; + pix->bytesperline =3D stride; + pix->sizeimage =3D stride * pix->height; + + return 0; +} + +static const struct fsd_csis_pixfmt *__fsd_csis_video_try_fmt_vid_cap( + struct fsd_csis *csis, struct v4l2_pix_format *pixfmt) +{ + struct v4l2_mbus_framefmt fmt_src; + const struct fsd_csis_pixfmt *cc; + struct v4l2_rect *compose =3D &csis->vdev_compose; + + /* + * Find the pixel format, default to the first supported format if not + * found. + */ + cc =3D fsd_csis_find_pixel_format(pixfmt->pixelformat); + + if (!cc) { + pixfmt->pixelformat =3D FSD_CSIS_DEF_PIX_FORMAT; + pixfmt->height =3D FSD_CSIS_DEF_PIX_HEIGHT; + pixfmt->width =3D FSD_CSIS_DEF_PIX_WIDTH; + pixfmt->colorspace =3D V4L2_COLORSPACE_SRGB; + pixfmt->field =3D V4L2_FIELD_NONE; + cc =3D fsd_csis_find_pixel_format(pixfmt->pixelformat); + } + + v4l2_fill_mbus_format(&fmt_src, pixfmt, cc->codes[0]); + fsd_csis_mbus_fmt_to_pix_fmt(pixfmt, &fmt_src, cc); + + compose->width =3D fmt_src.width; + compose->height =3D fmt_src.height; + + csis->vdev_fmt =3D *pixfmt; + return cc; +} + +static int fsd_csis_video_try_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct fsd_csis *csis =3D video_drvdata(file); + + __fsd_csis_video_try_fmt_vid_cap(csis, &f->fmt.pix); + return 0; +} + +static int fsd_csis_video_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct fsd_csis *csis =3D video_drvdata(file); + struct v4l2_subdev *sd =3D &csis->subdev.sd; + const struct fsd_csis_pixfmt *cc; + struct vb2_queue *q =3D &csis->q; + int ret; + struct v4l2_subdev_format fmt =3D { + .which =3D V4L2_SUBDEV_FORMAT_ACTIVE, + .pad =3D 0, + }; + + if (vb2_is_busy(q)) { + dev_err(csis->dev, "%s queue busy\n", __func__); + return -EBUSY; + } + + cc =3D __fsd_csis_video_try_fmt_vid_cap(csis, &f->fmt.pix); + v4l2_fill_mbus_format(&fmt.format, &f->fmt.pix, cc->codes[0]); + ret =3D v4l2_subdev_call(sd, pad, set_fmt, sd->active_state, &fmt); + + if (ret < 0) { + dev_err(csis->dev, "subdev format set failed %d\n", ret); + return ret; + } + + csis->vdev_cc =3D cc; + csis->vdev_fmt =3D f->fmt.pix; + return 0; +} + +static int fsd_csis_video_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct fsd_csis *csis =3D video_drvdata(file); + + f->fmt.pix =3D csis->vdev_fmt; + + return 0; +} + +static const struct vb2_ops fsd_csis_video_qops =3D { + .queue_setup =3D fsd_queue_setup, + .buf_prepare =3D fsd_buffer_prepare, + .buf_queue =3D fsd_buffer_queue, + .start_streaming =3D fsd_start_streaming, + .stop_streaming =3D fsd_stop_streaming, + .wait_prepare =3D vb2_ops_wait_prepare, + .wait_finish =3D vb2_ops_wait_finish, +}; + +static const struct v4l2_ioctl_ops fsd_csis_video_ioctl_ops =3D { + .vidioc_querycap =3D fsd_csis_video_querycap, + + .vidioc_enum_fmt_vid_cap =3D fsd_csis_video_enum_fmt_vid_cap, + + .vidioc_try_fmt_vid_cap =3D fsd_csis_video_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap =3D fsd_csis_video_s_fmt_vid_cap, + .vidioc_g_fmt_vid_cap =3D fsd_csis_video_g_fmt_vid_cap, + + .vidioc_reqbufs =3D vb2_ioctl_reqbufs, + .vidioc_querybuf =3D vb2_ioctl_querybuf, + .vidioc_qbuf =3D vb2_ioctl_qbuf, + .vidioc_expbuf =3D vb2_ioctl_expbuf, + .vidioc_dqbuf =3D vb2_ioctl_dqbuf, + .vidioc_prepare_buf =3D vb2_ioctl_prepare_buf, + .vidioc_create_bufs =3D vb2_ioctl_create_bufs, + .vidioc_streamon =3D vb2_ioctl_streamon, + .vidioc_streamoff =3D vb2_ioctl_streamoff, +}; + +/** + * V4L2 File operations + */ +static const struct v4l2_file_operations fsd_csis_video_fops =3D { + .owner =3D THIS_MODULE, + .open =3D fsd_csis_video_open, + .release =3D fsd_csis_video_release, + .read =3D vb2_fop_read, + .poll =3D vb2_fop_poll, + .unlocked_ioctl =3D video_ioctl2, + .mmap =3D vb2_fop_mmap, +}; + +static int fsd_csi_notify_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_connection *asd) +{ + struct fsd_csis *csis =3D notifier_to_csis(notifier); + struct media_pad *sink =3D &csis->subdev.pad[FSD_CSIS_PAD_SINK]; + struct media_pad *source; + int ret; + + dev_dbg(csis->dev, "Hooked csis subdevice: %s to parent\n", + subdev->name); + + ret =3D v4l2_create_fwnode_links_to_pad(subdev, sink, MEDIA_LNK_FL_ENABLE= D); + + if (ret) + return ret; + + source =3D media_pad_remote_pad_unique(sink); + if (IS_ERR(source)) { + dev_err(csis->dev, "No connected source pad\n"); + return PTR_ERR(source); + } + + csis->source.subdev =3D subdev; + csis->source.pad =3D source; + + return 0; +} + +static const struct v4l2_async_notifier_operations fsd_csi_notify_ops =3D { + .bound =3D fsd_csi_notify_bound, +}; + +static const struct media_device_ops fsd_csis_media_ops =3D { + .link_notify =3D v4l2_pipeline_link_notify, +}; + +static const struct media_entity_operations fsd_csis_entity_ops =3D { + .link_validate =3D v4l2_subdev_link_validate, + .get_fwnode_pad =3D v4l2_subdev_get_fwnode_pad_1_to_1, +}; + +static int fsd_csis_media_dev_init(struct fsd_csis *csis) +{ + int ret; + + + strscpy(csis->mdev.model, "fsd-csis-media", sizeof(csis->mdev.model)); + csis->mdev.ops =3D &fsd_csis_media_ops; + csis->mdev.dev =3D csis->dev; + + csis->v4l2_dev.mdev =3D &csis->mdev; + strscpy(csis->v4l2_dev.name, "fsd-csis-media", + sizeof(csis->v4l2_dev.name)); + snprintf(csis->mdev.bus_info, sizeof(csis->mdev.bus_info), + "platform:%s", dev_name(csis->mdev.dev)); + + media_device_init(&csis->mdev); + + ret =3D v4l2_device_register(csis->dev, &csis->v4l2_dev); + + if (ret < 0) { + v4l2_err(&csis->v4l2_dev, + "Failed to register v4l2_device: %d\n", ret); + goto cleanup; + } + + return 0; + +cleanup: + media_device_cleanup(&csis->mdev); + + return ret; +} + +static void fsd_csis_media_cleanup(struct fsd_csis *csis) +{ + v4l2_device_unregister(&csis->v4l2_dev); + media_device_unregister(&csis->mdev); + v4l2_subdev_cleanup(&csis->subdev.sd); + media_device_cleanup(&csis->mdev); +} + +static int fsd_csis_video_init(struct fsd_csis *csis) +{ + struct video_device *vdev; + struct vb2_queue *vq; + int ret; + + mutex_init(&csis->vdev_mutex); + INIT_LIST_HEAD(&csis->ready_q); + spin_lock_init(&csis->q_lock); + + /* Allocate and initialize the video device.*/ + vdev =3D video_device_alloc(); + if (!vdev) + return -ENOMEM; + + vdev->fops =3D &fsd_csis_video_fops; + vdev->ioctl_ops =3D &fsd_csis_video_ioctl_ops; + vdev->minor =3D -1; + vdev->release =3D video_device_release; + vdev->device_caps =3D V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + vdev->lock =3D &csis->vdev_mutex; + vdev->queue =3D &csis->q; + + snprintf(vdev->name, sizeof(vdev->name), "%s capture", csis->subdev.sd.na= me); + + video_set_drvdata(vdev, csis); + csis->vdev =3D vdev; + + /* Initialize the video device pad. */ + csis->vdev_pad.flags =3D MEDIA_PAD_FL_SINK; + + ret =3D media_entity_pads_init(&vdev->entity, 1, &csis->vdev_pad); + if (ret) { + video_device_release(vdev); + return ret; + } + + /* Initialize the vb2 queue. */ + vq =3D &csis->q; + vq->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE; + vq->io_modes =3D VB2_MMAP | VB2_USERPTR | VB2_DMABUF; + vq->drv_priv =3D csis; + vq->buf_struct_size =3D sizeof(struct fsd_csis_vb2_buffer); + vq->ops =3D &fsd_csis_video_qops; + vq->mem_ops =3D &vb2_dma_contig_memops; + vq->timestamp_flags =3D V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + vq->lock =3D &csis->vdev_mutex; + vq->min_reqbufs_allocation =3D FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS + 1; + vq->min_queued_buffers =3D FSD_CSIS_NB_MIN_CH; + vq->dev =3D csis->dev; + + ret =3D vb2_queue_init(vq); + if (ret) { + dev_err(csis->dev, "vb2_queue_init failed\n"); + video_device_release(vdev); + return ret; + } + + return 0; +} + +static void fsd_csis_video_init_format(struct fsd_csis *csis) +{ + + csis->vdev_fmt.width =3D FSD_CSIS_DEF_PIX_WIDTH; + csis->vdev_fmt.height =3D FSD_CSIS_DEF_PIX_HEIGHT; + csis->vdev_fmt.pixelformat =3D FSD_CSIS_DEF_PIX_FORMAT; + csis->vdev_fmt.colorspace =3D V4L2_COLORSPACE_SRGB; + csis->vdev_fmt.field =3D V4L2_FIELD_NONE; + + csis->vdev_cc =3D fsd_csis_find_pixel_format(csis->vdev_fmt.pixelformat); + + csis->vdev_fmt.bytesperline =3D bytes_per_line(FSD_CSIS_DEF_PIX_WIDTH, + csis->vdev_cc->bpp); + csis->vdev_fmt.sizeimage =3D csis->vdev_fmt.bytesperline * + csis->vdev_fmt.height; +} + +static int fsd_csis_video_register(struct fsd_csis *csis) +{ + struct v4l2_subdev *sd =3D &csis->subdev.sd; + struct v4l2_device *v4l2_dev =3D sd->v4l2_dev; + struct video_device *vdev =3D csis->vdev; + int ret; + + vdev->v4l2_dev =3D v4l2_dev; + + /* Initialize the default format and compose rectangle. */ + fsd_csis_video_init_format(csis); + + /* Register the video device. */ + ret =3D video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret) { + dev_err(csis->dev, "Failed to register video device\n"); + return ret; + } + + dev_info(csis->dev, "Registered %s as /dev/%s\n", vdev->name, + video_device_node_name(vdev)); + + /* Create the link from the CSI subdev to the video device. */ + ret =3D media_create_pad_link(&sd->entity, FSD_CSIS_PAD_SRC, + &vdev->entity, 0, MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + if (ret) { + dev_err(csis->dev, "failed to create link to device node\n"); + video_unregister_device(vdev); + return ret; + } + + return 0; +} + +static void fsd_csis_video_unregister(struct fsd_csis *csis) +{ + media_entity_cleanup(&csis->vdev->entity); + video_unregister_device(csis->vdev); +} + +static int fsd_csis_registered(struct v4l2_subdev *sd) +{ + struct fsd_csis *csis =3D v4l2_get_subdevdata(sd); + int ret; + + ret =3D fsd_csis_video_init(csis); + if (ret) + return ret; + + ret =3D fsd_csis_video_register(csis); + if (ret) + return ret; + + ret =3D v4l2_device_register_subdev_nodes(&csis->v4l2_dev); + if (ret) + goto err_unregister; + + ret =3D media_device_register(&csis->mdev); + if (ret) + goto err_unregister; + + return 0; + +err_unregister: + fsd_csis_video_unregister(csis); + + return ret; +} + +static void fsd_csis_unregistered(struct v4l2_subdev *sd) +{ + struct fsd_csis *csis =3D v4l2_get_subdevdata(sd); + + fsd_csis_video_unregister(csis); +} + +static int fsd_csis_sd_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *sdformat) +{ + struct fsd_csis *csis =3D v4l2_get_subdevdata(sd); + struct v4l2_subdev *subdev =3D csis->source.subdev; + struct v4l2_mbus_framefmt *fmt; + const struct fsd_csis_pixfmt *cc; + + if (sdformat->which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE && csis->is_streamin= g) + return -EBUSY; + + if (sdformat->pad =3D=3D FSD_CSIS_PAD_SRC) + return v4l2_subdev_get_fmt(sd, sd_state, sdformat); + + if (sdformat->pad !=3D FSD_CSIS_PAD_SINK) + return -EINVAL; + + cc =3D fsd_csis_find_mbus_format(sdformat->format.code); + if (!cc) + cc =3D fsd_csis_find_mbus_format(FSD_CSIS_DEF_MBUS_CODE); + + fmt =3D v4l2_subdev_state_get_format(sd_state, sdformat->pad); + + fmt->code =3D cc->codes[0]; + fmt->width =3D sdformat->format.width; + fmt->height =3D sdformat->format.height; + fmt->field =3D V4L2_FIELD_NONE; + + sdformat->format =3D *fmt; + + /* Propagate the format from sink to source. */ + fmt =3D v4l2_subdev_state_get_format(sd_state, FSD_CSIS_PAD_SRC); + *fmt =3D sdformat->format; + + return v4l2_subdev_call(subdev, pad, set_fmt, subdev->active_state, sdfor= mat); +} + +static int __fsd_csis_sd_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_krouting *routing) +{ + struct v4l2_subdev_route *route; + int ret; + + ret =3D v4l2_subdev_routing_validate(sd, routing, + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); + if (ret) + return ret; + + ret =3D v4l2_subdev_set_routing(sd, state, routing); + if (ret) + return ret; + + for_each_active_route(&state->routing, route) { + const struct v4l2_mbus_framefmt *def_fmt; + struct v4l2_mbus_framefmt *fmt; + + def_fmt =3D &fsd_csis_default_format; + + fmt =3D v4l2_subdev_state_get_format(state, route->sink_pad, + route->sink_stream); + *fmt =3D *def_fmt; + fmt =3D v4l2_subdev_state_get_format(state, route->source_pad, + route->source_stream); + *fmt =3D *def_fmt; + } + + return 0; +} + +static int fsd_csis_sd_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *routing) +{ + struct fsd_csis *csis =3D v4l2_get_subdevdata(sd); + + if (which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE && csis->is_streaming) + return -EBUSY; + + return __fsd_csis_sd_set_routing(sd, state, routing); +} + +static int fsd_csis_sd_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + + struct fsd_csis *csis =3D v4l2_get_subdevdata(sd); + + return v4l2_subdev_enable_streams(csis->source.subdev, + FSD_CSIS_PAD_SRC, BIT(0)); +} + +static int fsd_csis_sd_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + u32 pad, u64 streams_mask) +{ + struct fsd_csis *csis =3D v4l2_get_subdevdata(sd); + + return v4l2_subdev_disable_streams(csis->source.subdev, + FSD_CSIS_PAD_SRC, BIT(0)); +} + +static int fsd_csis_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct v4l2_subdev_route routes[] =3D { + { + .sink_pad =3D FSD_CSIS_PAD_SINK, + .sink_stream =3D 0, + .source_pad =3D FSD_CSIS_PAD_SRC, + .source_stream =3D 0, + .flags =3D V4L2_SUBDEV_ROUTE_FL_ACTIVE, + }, + }; + + struct v4l2_subdev_krouting routing =3D { + .len_routes =3D ARRAY_SIZE(routes), + .num_routes =3D ARRAY_SIZE(routes), + .routes =3D routes, + }; + + return __fsd_csis_sd_set_routing(sd, state, &routing); +} + +static const struct v4l2_subdev_internal_ops fsd_csis_internal_ops =3D { + .init_state =3D fsd_csis_init_state, + .registered =3D fsd_csis_registered, + .unregistered =3D fsd_csis_unregistered, +}; + +static const struct v4l2_subdev_pad_ops fsd_csis_pad_ops =3D { + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D fsd_csis_sd_set_fmt, + .set_routing =3D fsd_csis_sd_set_routing, + .enable_streams =3D fsd_csis_sd_enable_streams, + .disable_streams =3D fsd_csis_sd_disable_streams, +}; + +static const struct v4l2_subdev_ops fsd_csis_subdev_ops =3D { + .pad =3D &fsd_csis_pad_ops, +}; + +static int fsd_csis_media_init(struct fsd_csis *csis) +{ + struct v4l2_subdev *sd =3D &csis->subdev.sd; + int ret, i; + + /* add media device */ + ret =3D fsd_csis_media_dev_init(csis); + if (ret) + return ret; + + v4l2_subdev_init(sd, &fsd_csis_subdev_ops); + v4l2_set_subdevdata(sd, csis); + sd->internal_ops =3D &fsd_csis_internal_ops; + sd->entity.ops =3D &fsd_csis_entity_ops; + sd->entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; + sd->dev =3D csis->dev; + sd->owner =3D THIS_MODULE; + sd->flags =3D V4L2_SUBDEV_FL_HAS_DEVNODE; + snprintf(sd->name, sizeof(sd->name), "csis"); + + for (i =3D 0; i < FSD_CSIS_PADS_NUM; i++) + csis->subdev.pad[i].flags =3D (i =3D=3D FSD_CSIS_PAD_SINK) ? + MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE; + + ret =3D media_entity_pads_init(&sd->entity, FSD_CSIS_PADS_NUM, + csis->subdev.pad); + + if (ret) + goto error; + + ret =3D v4l2_subdev_init_finalize(sd); + if (ret) + goto error; + + ret =3D v4l2_device_register_subdev(&csis->v4l2_dev, sd); + if (ret) + goto error; + + return 0; +error: + fsd_csis_media_cleanup(csis); + return ret; +} + +static int fsd_csis_async_register(struct fsd_csis *csis) +{ + struct v4l2_async_connection *asd; + struct fwnode_handle *ep; + int ret; + + v4l2_async_nf_init(&csis->notifier, &csis->v4l2_dev); + + ep =3D fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, + FWNODE_GRAPH_ENDPOINT_NEXT); + + if (ep) { + asd =3D v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, + struct v4l2_async_connection); + fwnode_handle_put(ep); + + if (IS_ERR(asd)) { + ret =3D PTR_ERR(asd); + /* OK if asd already exists */ + if (ret !=3D -EEXIST) + goto error; + } + } + + csis->notifier.ops =3D &fsd_csi_notify_ops; + + ret =3D v4l2_async_nf_register(&csis->notifier); + if (ret) + goto error; + + return 0; + +error: + v4l2_async_nf_cleanup(&csis->notifier); + return ret; +} + +static int fsd_csis_enable_pll(struct fsd_csis *csis) +{ + csis->pll =3D devm_clk_get(csis->dev, "pll"); + + if (IS_ERR(csis->pll)) + return PTR_ERR(csis->pll); + + return clk_prepare_enable(csis->pll); +} + +static int fsd_csis_clk_get(struct fsd_csis *csis) +{ + int i; + + csis->clks =3D devm_kcalloc(csis->dev, FSD_CSIS_NB_CLOCK, sizeof(*csis->c= lks), GFP_KERNEL); + + if (!csis->clks) + return -ENOMEM; + + for (i =3D 0; i < FSD_CSIS_NB_CLOCK; i++) + csis->clks[i].id =3D fsd_csis_clk_id[i]; + + return devm_clk_bulk_get(csis->dev, FSD_CSIS_NB_CLOCK, csis->clks); +} + +static int fsd_csis_runtime_suspend(struct device *dev) +{ + struct fsd_csis *csis =3D dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(FSD_CSIS_NB_CLOCK, csis->clks); + + return 0; +} + +static int fsd_csis_runtime_resume(struct device *dev) +{ + struct fsd_csis *csis =3D dev_get_drvdata(dev); + + return clk_bulk_prepare_enable(FSD_CSIS_NB_CLOCK, csis->clks); +} + +static const struct dev_pm_ops fsd_csis_pm_ops =3D { + SET_RUNTIME_PM_OPS(fsd_csis_runtime_suspend, fsd_csis_runtime_resume, + NULL) +}; + +static int fsd_csis_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct fsd_csis *csis; + int ret =3D 0; + int irq; + + csis =3D devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); + if (!csis) + return -ENOMEM; + + csis->dev =3D dev; + csis->info =3D of_device_get_match_data(dev); + + csis->dma_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(csis->dma_base)) + return PTR_ERR(csis->dma_base); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret =3D devm_request_irq(dev, irq, + csis_irq_handler, IRQF_SHARED, pdev->name, csis); + + ret =3D fsd_csis_clk_get(csis); + if (ret < 0) + return ret; + + pm_runtime_enable(dev); + if (!pm_runtime_enabled(dev)) { + ret =3D fsd_csis_runtime_resume(dev); + if (ret < 0) + return ret; + } + + platform_set_drvdata(pdev, csis); + + ret =3D fsd_csis_enable_pll(csis); + if (ret) + return ret; + + ret =3D fsd_csis_media_init(csis); + if (ret) + return ret; + + ret =3D fsd_csis_async_register(csis); + if (ret) + goto err_media_cleanup; + + return 0; + +err_media_cleanup: + fsd_csis_media_cleanup(csis); + + return ret; +} + +static void fsd_csis_remove(struct platform_device *pdev) +{ + struct fsd_csis *csis =3D platform_get_drvdata(pdev); + + fsd_csis_media_cleanup(csis); + + v4l2_async_nf_unregister(&csis->notifier); + v4l2_async_nf_cleanup(&csis->notifier); + v4l2_async_unregister_subdev(&csis->subdev.sd); + + if (!pm_runtime_enabled(csis->dev)) + fsd_csis_runtime_suspend(csis->dev); + + pm_runtime_disable(csis->dev); + pm_runtime_set_suspended(csis->dev); +} + +static const struct of_device_id fsd_csis_of_match[] =3D { + { .compatible =3D "tesla,fsd-csis-media", }, + { }, +}; + +MODULE_DEVICE_TABLE(of, fsd_csis_of_match); + +static struct platform_driver fsd_csis_driver =3D { + .probe =3D fsd_csis_probe, + .remove =3D fsd_csis_remove, + .driver =3D { + .name =3D FSD_CSIS_MODULE_NAME, + .of_match_table =3D of_match_ptr(fsd_csis_of_match), + .pm =3D &fsd_csis_pm_ops, + }, +}; + +module_platform_driver(fsd_csis_driver); + +MODULE_DESCRIPTION("FSD CSIS Driver"); +MODULE_AUTHOR("Inbaraj E "); +MODULE_LICENSE("GPL"); + --=20 2.49.0