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[31.53.6.191]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c466838sm53497380f8f.49.2025.08.14.05.48.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Aug 2025 05:48:36 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 2/4] clk: renesas: rzv2h: Add support for parent mod clocks Date: Thu, 14 Aug 2025 13:48:25 +0100 Message-ID: <20250814124832.76266-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814124832.76266-1-biju.das.jz@bp.renesas.com> References: <20250814124832.76266-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for parent mod clock to register core clocks that has a parent module clock on the Renesas RZ/G3E SoC (eg: GPT has two clocks bus clock and core clock. The core clock is controlled by the bus clock). Signed-off-by: Biju Das --- drivers/clk/renesas/rzv2h-cpg.c | 11 +++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 22 +++++++++++++++++----- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index 8511b7154e90..43fd3fadc5f7 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -823,6 +823,17 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk = *mod, } =20 priv->clks[id] =3D clock->hw.clk; + if (mod->child_name) { + WARN_DEBUG(mod->child >=3D priv->num_core_clks); + WARN_DEBUG(PTR_ERR(priv->clks[mod->child]) !=3D -ENOENT); + + clk =3D rzv2h_cpg_mod_status_clk_register(priv, mod->child_name, mod->na= me, 1, 1, + FIXED_MOD_CONF_PACK(mod->mon_index, + mod->mon_bit)); + if (IS_ERR_OR_NULL(clk)) + goto fail; + priv->clks[mod->child] =3D clk; + } =20 /* * Ensure the module clocks and MSTOP bits are synchronized when they are diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 840eed25aeda..c4205c8fd426 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -235,8 +235,10 @@ enum clk_types { */ struct rzv2h_mod_clk { const char *name; + const char *child_name; u32 mstop_data; u16 parent; + u16 child; bool critical; bool no_pm; u8 on_index; @@ -247,11 +249,13 @@ struct rzv2h_mod_clk { }; =20 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \ - _onbit, _monindex, _monbit, _ext_clk_mux_index) \ + _onbit, _monindex, _monbit, _ext_clk_mux_index, _childname, _child)= \ { \ .name =3D (_name), \ + .child_name =3D (_childname), \ .mstop_data =3D (_mstop), \ .parent =3D (_parent), \ + .child =3D (_child), \ .critical =3D (_critical), \ .no_pm =3D (_no_pm), \ .on_index =3D (_onindex), \ @@ -262,18 +266,26 @@ struct rzv2h_mod_clk { } =20 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mst= op) \ - DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit, -1) + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, \ + _monbit, -1, NULL, 0) =20 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _mon= bit, _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _moni= ndex, _monbit, -1) + DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _moni= ndex, \ + _monbit, -1, NULL, 0) =20 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit= , _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _moni= ndex, _monbit, -1) + DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _moni= ndex, \ + _monbit, -1, NULL, 0) =20 #define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, = _monbit, _mstop, \ _ext_clk_mux_index) \ DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit, \ - _ext_clk_mux_index) + _ext_clk_mux_index, NULL, 0) + +#define DEF_MOD_PARENT(_name, _parent, _onindex, _onbit, _monindex, _monbi= t, _mstop, \ + _child_name, _child) \ + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit, \ + -1, _child_name, _child) =20 /** * struct rzv2h_reset - Reset definitions --=20 2.43.0