From nobody Sat Oct 4 19:17:41 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44CAA2EAB66; Thu, 14 Aug 2025 08:56:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755161819; cv=none; b=KxHe0c91C1yUM9/UTGLqleiIJxK91pM5u2TK8GIpMvZBYEq36W6o6RpxUkbw3oQSNpTk8h0wIHMB+ftcf8/KkXEmQxvz0b6xRTgm/9kaEN4/0gXO4V0hgWwNjuMs5TG7YgP+Wx1NcgH+9fbqtTWF8cgYJacm1IrC2kZKsgjK/VY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755161819; c=relaxed/simple; bh=bunu5DfTKyvt3c/ptKXEvzuyt1It3hXGXDsAwX2pfsE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iJhtZBNUsL0MQJfPrxTgilrj6g7NoEyu5GWVGpDLDPPG9srdOWO3SPuTa37CJktYhbfKWlZxvC2QBP9o175NAtxM1pZCoG2Eclgu0rX/v0Ah5yX7bMOUZVbOurLpx+G6XUDqQANmGeI+Tjy8eC/Q2/sLujg76AkL+3FGF92vahM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=LQb3hIGl; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="LQb3hIGl" X-UUID: 9ead980a78ec11f0b33aeb1e7f16c2b6-20250814 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=xy4AutsWSzEV9WgoSC/90TKzvC8h5+PuLT7188L0doA=; b=LQb3hIGl1xsXCgZKS4AJnGywFwC1c+hFno6DxQCiSSdk9LdkDvf4V3+9BHMOoMHhEywSgurtYDv9rBTuFYKYdrDM3FsHPRx8E4n80uBJCbo2vt5uX6Lu+koAuF1q/rSLa2xaIvknGCf2SyvQ5ALagibk72ZdmnD+1ENs5XQi1Tg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:54e67ccd-9913-4895-8134-d5c4a423d77d,IP:0,UR L:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:f1326cf,CLOUDID:09a3edf3-66cd-4ff9-9728-6a6f64661009,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 9ead980a78ec11f0b33aeb1e7f16c2b6-20250814 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1422991359; Thu, 14 Aug 2025 16:56:51 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 14 Aug 2025 16:56:50 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 14 Aug 2025 16:56:49 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Christophe JAILLET , Sebastian Fricke , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz Subject: [PATCH v3 2/6] media: mediatek: encoder: Add support for common firmware interface Date: Thu, 14 Aug 2025 16:56:38 +0800 Message-ID: <20250814085642.17343-3-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250814085642.17343-1-kyrie.wu@mediatek.com> References: <20250814085642.17343-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" From: Irui Wang The existing encoder firmware interface implied just one type of codec: H.264. Future encoders may support additional codecs; however adding entire sets of interfaces for them is not scalable. Instead, a new "common" firmware interface is defined for non codec specific messages. The new messages encapsulate the old ones for backward compatibility. This patch adds support for these new messages. Signed-off-by: Irui Wang --- .../vcodec/encoder/mtk_vcodec_enc_drv.h | 3 ++ .../mediatek/vcodec/encoder/venc_drv_if.c | 3 +- .../mediatek/vcodec/encoder/venc_ipi_msg.h | 26 +++++++++++++ .../mediatek/vcodec/encoder/venc_vpu_if.c | 37 ++++++++++++------- 4 files changed, 54 insertions(+), 15 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h index b1277bcfcf53..426b1398f815 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h @@ -16,6 +16,7 @@ =20 #define MTK_ENC_CTX_IS_EXT(ctx) ((ctx)->dev->venc_pdata->uses_ext) #define MTK_ENC_IOVA_IS_34BIT(ctx) ((ctx)->dev->venc_pdata->uses_34bit) +#define MTK_ENC_DRV_IS_COMM(ctx) (((ctx)->dev->venc_pdata->uses_common_fw_= iface)) =20 /** * struct mtk_vcodec_enc_pdata - compatible data for each IC @@ -29,6 +30,7 @@ * @num_output_formats: number of entries in output_formats * @core_id: stand for h264 or vp8 encode index * @uses_34bit: whether the encoder uses 34-bit iova + * @uses_common_fw_iface: whether the encoder uses common driver interface */ struct mtk_vcodec_enc_pdata { bool uses_ext; @@ -40,6 +42,7 @@ struct mtk_vcodec_enc_pdata { size_t num_output_formats; u8 core_id; bool uses_34bit; + bool uses_common_fw_iface; }; =20 /* diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c b= /drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c index e83747b8d69a..f8c9349c18c0 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c @@ -19,13 +19,14 @@ int venc_if_init(struct mtk_vcodec_enc_ctx *ctx, unsigned int fourcc) { int ret =3D 0; + const bool uses_common_fw_iface =3D MTK_ENC_DRV_IS_COMM(ctx); =20 switch (fourcc) { case V4L2_PIX_FMT_VP8: ctx->enc_if =3D &venc_vp8_if; break; case V4L2_PIX_FMT_H264: - ctx->enc_if =3D &venc_h264_if; + ctx->enc_if =3D uses_common_fw_iface ? &venc_if : &venc_h264_if; break; default: return -EINVAL; diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h = b/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h index bb16d96a7f57..ce3c2c8059fb 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_ipi_msg.h @@ -45,6 +45,20 @@ struct venc_ap_ipi_msg_init { uint64_t venc_inst; }; =20 +/** + * struct venc_ap_ipi_msg_init_comm - AP to VPU init cmd structure + * @base: AP to VPU init cmd structure + * @codec_type: encoder type + * @reserved: reserved field + * @shared_iova: shared iova + */ +struct venc_ap_ipi_msg_init_comm { + struct venc_ap_ipi_msg_init base; + u32 codec_type; + u32 reserved; + u64 shared_iova; +}; + /** * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure * @msg_id: message id (AP_IPIMSG_XXX_ENC_SET_PARAM) @@ -175,6 +189,18 @@ struct venc_vpu_ipi_msg_init { uint32_t venc_abi_version; }; =20 +/** + * struct venc_vpu_ipi_msg_init_comm - VPU ack AP init cmd structure + * @init_ack: AP init cmd structure + * @vpu_vsi_addr: VSI address from VPU + * @reserved: reserved field + */ +struct venc_vpu_ipi_msg_init_comm { + struct venc_vpu_ipi_msg_init init_ack; + u32 vpu_vsi_addr; + u32 reserved; +}; + /** * struct venc_vpu_ipi_msg_set_param - VPU ack AP set_param cmd structure * @msg_id: message id (VPU_IPIMSG_XXX_ENC_SET_PARAM_DONE) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c b= /drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c index 51bb7ee141b9..537b9955932e 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c @@ -10,24 +10,25 @@ =20 static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *dat= a) { - const struct venc_vpu_ipi_msg_init *msg =3D data; + const struct venc_vpu_ipi_msg_init_comm *msg =3D data; + struct mtk_vcodec_fw *fw =3D vpu->ctx->dev->fw_handler; =20 - vpu->inst_addr =3D msg->vpu_inst_addr; - vpu->vsi =3D mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, - msg->vpu_inst_addr); + vpu->inst_addr =3D msg->init_ack.vpu_inst_addr; + vpu->vsi =3D mtk_vcodec_fw_map_dm_addr(fw, vpu->inst_addr); =20 /* Firmware version field value is unspecified on MT8173. */ - if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) =3D=3D VPU) + if (mtk_vcodec_fw_get_type(fw) =3D=3D VPU) return; =20 /* Check firmware version. */ - mtk_venc_debug(vpu->ctx, "firmware version: 0x%x\n", msg->venc_abi_versio= n); - switch (msg->venc_abi_version) { + mtk_venc_debug(vpu->ctx, "firmware version: 0x%x\n", + msg->init_ack.venc_abi_version); + switch (msg->init_ack.venc_abi_version) { case 1: break; default: mtk_venc_err(vpu->ctx, "unhandled firmware version 0x%x\n", - msg->venc_abi_version); + msg->init_ack.venc_abi_version); vpu->failure =3D 1; break; } @@ -132,7 +133,8 @@ static int vpu_enc_send_msg(struct venc_vpu_inst *vpu, = void *msg, int vpu_enc_init(struct venc_vpu_inst *vpu) { int status; - struct venc_ap_ipi_msg_init out; + size_t msg_size; + struct venc_ap_ipi_msg_init_comm out; =20 init_waitqueue_head(&vpu->wq_hd); vpu->signaled =3D 0; @@ -149,9 +151,16 @@ int vpu_enc_init(struct venc_vpu_inst *vpu) } =20 memset(&out, 0, sizeof(out)); - out.msg_id =3D AP_IPIMSG_ENC_INIT; - out.venc_inst =3D (unsigned long)vpu; - if (vpu_enc_send_msg(vpu, &out, sizeof(out))) { + out.base.msg_id =3D AP_IPIMSG_ENC_INIT; + out.base.venc_inst =3D (unsigned long)vpu; + if (MTK_ENC_DRV_IS_COMM(vpu->ctx)) { + out.codec_type =3D vpu->ctx->q_data[MTK_Q_DATA_DST].fmt->fourcc; + msg_size =3D sizeof(struct venc_ap_ipi_msg_init_comm); + } else { + msg_size =3D sizeof(struct venc_ap_ipi_msg_init); + } + + if (vpu_enc_send_msg(vpu, &out, msg_size)) { mtk_venc_err(vpu->ctx, "AP_IPIMSG_ENC_INIT fail"); return -EINVAL; } @@ -260,7 +269,7 @@ static int vpu_enc_encode_32bits(struct venc_vpu_inst *= vpu, sizeof(struct venc_ap_ipi_msg_enc); struct venc_ap_ipi_msg_enc_ext out; =20 - mtk_venc_debug(vpu->ctx, "bs_mode %d ->", bs_mode); + mtk_venc_debug(vpu->ctx, "%s, bs_mode %d ->", __func__, bs_mode); =20 memset(&out, 0, sizeof(out)); out.base.msg_id =3D AP_IPIMSG_ENC_ENCODE; @@ -305,7 +314,7 @@ static int vpu_enc_encode_34bits(struct venc_vpu_inst *= vpu, struct venc_ap_ipi_msg_enc_ext_34 out; size_t msg_size =3D sizeof(struct venc_ap_ipi_msg_enc_ext_34); =20 - mtk_venc_debug(vpu->ctx, "bs_mode %d ->", bs_mode); + mtk_venc_debug(vpu->ctx, "%s, bs_mode %d ->", __func__, bs_mode); =20 memset(&out, 0, sizeof(out)); out.msg_id =3D AP_IPIMSG_ENC_ENCODE; --=20 2.46.0