From nobody Sat Oct 4 17:34:15 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 467AF25C80D; Thu, 14 Aug 2025 07:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755157030; cv=none; b=VvMuqyrjR2rL1adARzRPFq5DaBjynYUR7WuYel1+Mn1lWPe5eeycbXT7YXPmcwUemLsdsxZnK2hNh4Knl7hgxWrieFTUYaEv/xZcvDfT1oMeA4+u0WoTzYASIOJzkKKAMnxQkB4ZwNZRV5sa4/a0vWOE4r44bQ5YCOZQjuAGw1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755157030; c=relaxed/simple; bh=sx6hlBHBeNHTb6+Vae9NAlYaBET/EXtzzpTp0PmsiCU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rBMkpsC0r1IlnLbYUrxjsV+W3ur7ALaAFQqe6bxt97SkgVCEYT1hORCyB12r54JJLhhdHpUoPOjEHfVTmagAezpnps5+g/kDCj9WU8/IBjC1/T3MeYhmognqcokdF69SrhXIKZ3qmExX6MP6Dmd0oGcHlnnU0UFqd5jsKBoNbKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KX6e2ou2; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KX6e2ou2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755157029; x=1786693029; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sx6hlBHBeNHTb6+Vae9NAlYaBET/EXtzzpTp0PmsiCU=; b=KX6e2ou23M+VNEX1O3619uoOwZI11sdAQVkcHXaKkRjrKMkQr1AD1gLm kwISGZ6/+n15B0cVTSUEfYsgDloROhddv8urQouGCKTNkhFHNSWk7yWaW CsiJR3jjVwNk/Qgh4ySS5LN58/0ktpaWBm8B20MviRcBDMIdcdLU41GeI 6WsjgubMxqGBRgOVaDhC51teTmyXqM9lgRy6PYMgjpiXUC8TrDINHt3/e 5ffOlOeXeUxeqdAi6sDw6FBs0kDI15QXYuu2Gw45tyKeKIN7iW8VqL82z bczcb8Bj/8hrQITh9FLEsJKWvlpFeZxXvMOqfAz9ZuS+/gpUX1Z0iODtx Q==; X-CSE-ConnectionGUID: 7OcNNH2PSVqsyZicK54FAA== X-CSE-MsgGUID: xX36joOMQXCr3SiB/cdlGA== X-IronPort-AV: E=McAfee;i="6800,10657,11520"; a="82899352" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="82899352" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2025 00:37:08 -0700 X-CSE-ConnectionGUID: 6tnd4XOCT/q+mDWt83MPpA== X-CSE-MsgGUID: Q2XpgmLqTcOaga7/t0pb9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="171927363" Received: from foboril-desk.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.138]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2025 00:37:04 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v14 1/5] x86/sgx: Introduce functions to count the sgx_(vepc_)open() Date: Thu, 14 Aug 2025 10:34:21 +0300 Message-ID: <20250814073640.1507050-2-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250814073640.1507050-1-elena.reshetova@intel.com> References: <20250814073640.1507050-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, when SGX is compromised and the microcode update fix is applied, the machine needs to be rebooted to invalidate old SGX crypto-assets and make SGX be in an updated safe state. It's not friendly for the cloud. To avoid having to reboot, a new ENCLS[EUPDATESVN] is introduced to update SGX environment at runtime. This process needs to be done when there's no SGX users to make sure no compromised enclaves can survive from the update and allow the system to regenerate crypto-assets. For now there's no counter to track the active SGX users of host enclave and virtual EPC. Introduce such counter mechanism so that the EUPDATESVN can be done only when there's no SGX users. Define placeholder functions sgx_inc/dec_usage_count() that are used to increment and decrement such a counter. Also, wire the call sites for these functions. Encapsulate the current sgx_(vepc_)open() to __sgx_(vepc_)open() to make the new sgx_(vepc_)open() easy to read. The definition of the counter itself and the actual implementation of sgx_inc/dec_usage_count() functions come next. Note: The EUPDATESVN, which may fail, will be done in sgx_inc_usage_count(). Make it return 'int' to make subsequent patches which implement EUPDATESVN easier to review. For now it always returns success. Suggested-by: Sean Christopherson Reviewed-by: Kai Huang Reviewed-by: Jarkko Sakkinen Signed-off-by: Elena Reshetova --- arch/x86/kernel/cpu/sgx/driver.c | 19 ++++++++++++++++++- arch/x86/kernel/cpu/sgx/encl.c | 1 + arch/x86/kernel/cpu/sgx/main.c | 10 ++++++++++ arch/x86/kernel/cpu/sgx/sgx.h | 3 +++ arch/x86/kernel/cpu/sgx/virt.c | 20 +++++++++++++++++++- 5 files changed, 51 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/sgx/driver.c b/arch/x86/kernel/cpu/sgx/dri= ver.c index 7f8d1e11dbee..79d6020dfe9c 100644 --- a/arch/x86/kernel/cpu/sgx/driver.c +++ b/arch/x86/kernel/cpu/sgx/driver.c @@ -14,7 +14,7 @@ u64 sgx_attributes_reserved_mask; u64 sgx_xfrm_reserved_mask =3D ~0x3; u32 sgx_misc_reserved_mask; =20 -static int sgx_open(struct inode *inode, struct file *file) +static int __sgx_open(struct inode *inode, struct file *file) { struct sgx_encl *encl; int ret; @@ -41,6 +41,23 @@ static int sgx_open(struct inode *inode, struct file *fi= le) return 0; } =20 +static int sgx_open(struct inode *inode, struct file *file) +{ + int ret; + + ret =3D sgx_inc_usage_count(); + if (ret) + return ret; + + ret =3D __sgx_open(inode, file); + if (ret) { + sgx_dec_usage_count(); + return ret; + } + + return 0; +} + static int sgx_release(struct inode *inode, struct file *file) { struct sgx_encl *encl =3D file->private_data; diff --git a/arch/x86/kernel/cpu/sgx/encl.c b/arch/x86/kernel/cpu/sgx/encl.c index 308dbbae6c6e..cf149b9f4916 100644 --- a/arch/x86/kernel/cpu/sgx/encl.c +++ b/arch/x86/kernel/cpu/sgx/encl.c @@ -765,6 +765,7 @@ void sgx_encl_release(struct kref *ref) WARN_ON_ONCE(encl->secs.epc_page); =20 kfree(encl); + sgx_dec_usage_count(); } =20 /* diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 2de01b379aa3..3a5cbd1c170e 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -917,6 +917,16 @@ int sgx_set_attribute(unsigned long *allowed_attribute= s, } EXPORT_SYMBOL_GPL(sgx_set_attribute); =20 +int sgx_inc_usage_count(void) +{ + return 0; +} + +void sgx_dec_usage_count(void) +{ + return; +} + static int __init sgx_init(void) { int ret; diff --git a/arch/x86/kernel/cpu/sgx/sgx.h b/arch/x86/kernel/cpu/sgx/sgx.h index d2dad21259a8..f5940393d9bd 100644 --- a/arch/x86/kernel/cpu/sgx/sgx.h +++ b/arch/x86/kernel/cpu/sgx/sgx.h @@ -102,6 +102,9 @@ static inline int __init sgx_vepc_init(void) } #endif =20 +int sgx_inc_usage_count(void); +void sgx_dec_usage_count(void); + void sgx_update_lepubkeyhash(u64 *lepubkeyhash); =20 #endif /* _X86_SGX_H */ diff --git a/arch/x86/kernel/cpu/sgx/virt.c b/arch/x86/kernel/cpu/sgx/virt.c index 7aaa3652e31d..b649c0610019 100644 --- a/arch/x86/kernel/cpu/sgx/virt.c +++ b/arch/x86/kernel/cpu/sgx/virt.c @@ -255,10 +255,11 @@ static int sgx_vepc_release(struct inode *inode, stru= ct file *file) xa_destroy(&vepc->page_array); kfree(vepc); =20 + sgx_dec_usage_count(); return 0; } =20 -static int sgx_vepc_open(struct inode *inode, struct file *file) +static int __sgx_vepc_open(struct inode *inode, struct file *file) { struct sgx_vepc *vepc; =20 @@ -273,6 +274,23 @@ static int sgx_vepc_open(struct inode *inode, struct f= ile *file) return 0; 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d="scan'208";a="171927373" Received: from foboril-desk.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.138]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2025 00:37:09 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova , Dave Hansen Subject: [PATCH v14 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag Date: Thu, 14 Aug 2025 10:34:22 +0300 Message-ID: <20250814073640.1507050-3-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250814073640.1507050-1-elena.reshetova@intel.com> References: <20250814073640.1507050-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction is supported. This will be used by SGX driver to perform CPU SVN updates. Reviewed-by: Jarkko Sakkinen Reviewed-by: Kai Huang Reviewed-by: Dave Hansen Signed-off-by: Elena Reshetova --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 602957dd2609..830d24ff1ada 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -494,6 +494,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+14) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 46efcbd6afa4..3d9f49ad0efd 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -79,6 +79,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, + { X86_FEATURE_SGX_EUPDATESVN, X86_FEATURE_SGX1 }, { X86_FEATURE_SGX_EDECCSSA, X86_FEATURE_SGX1 }, { X86_FEATURE_XFD, X86_FEATURE_XSAVES }, { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index b4a1f6732a3a..d13444d11ba0 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 }, { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 }, { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 }, + { X86_FEATURE_SGX_EUPDATESVN, CPUID_EAX, 10, 0x00000012, 0 }, { X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 }, { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index ee176236c2be..78c3894c17c1 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -487,6 +487,7 @@ #define X86_FEATURE_PREFER_YMM (21*32+ 8) /* Avoid ZMM registers due to d= ownclocking */ #define X86_FEATURE_APX (21*32+ 9) /* Advanced Performance Extensions */ #define X86_FEATURE_INDIRECT_THUNK_ITS (21*32+10) /* Use thunk for indirec= t branches in lower half of cacheline */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+14) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) --=20 2.45.2 From nobody Sat Oct 4 17:34:15 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A0FD26A08A; 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a="82899373" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="82899373" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2025 00:37:18 -0700 X-CSE-ConnectionGUID: 6qN9i1tjQUeC0Vige/fg8w== X-CSE-MsgGUID: 5nGPWQU2R36MpCBia6xbLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="171927392" Received: from foboril-desk.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.138]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2025 00:37:13 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v14 3/5] x86/sgx: Define error codes for use by ENCLS[EUPDATESVN] Date: Thu, 14 Aug 2025 10:34:23 +0300 Message-ID: <20250814073640.1507050-4-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250814073640.1507050-1-elena.reshetova@intel.com> References: <20250814073640.1507050-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add error codes for ENCLS[EUPDATESVN], then SGX CPUSVN update process can know the execution state of EUPDATESVN and notify userspace. EUPDATESVN will be called when no active SGX users is guaranteed. Only add the error codes that can legally happen. E.g., it could also fail due to "SGX not ready" when there's SGX users but it wouldn't happen in this implementation. Reviewed-by: Kai Huang Reviewed-by: Jarkko Sakkinen Signed-off-by: Elena Reshetova --- arch/x86/include/asm/sgx.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h index 6a0069761508..73348cf4fd78 100644 --- a/arch/x86/include/asm/sgx.h +++ b/arch/x86/include/asm/sgx.h @@ -73,6 +73,10 @@ enum sgx_encls_function { * public key does not match IA32_SGXLEPUBKEYHASH. * %SGX_PAGE_NOT_MODIFIABLE: The EPC page cannot be modified because it * is in the PENDING or MODIFIED state. + * %SGX_INSUFFICIENT_ENTROPY: Insufficient entropy in RNG. + * %SGX_NO_UPDATE: EUPDATESVN could not update the CPUSVN because the + * current SVN was not newer than CPUSVN. This is the most + * common error code returned by EUPDATESVN. * %SGX_UNMASKED_EVENT: An unmasked event, e.g. INTR, was received */ enum sgx_return_code { @@ -81,6 +85,8 @@ enum sgx_return_code { SGX_CHILD_PRESENT =3D 13, SGX_INVALID_EINITTOKEN =3D 16, SGX_PAGE_NOT_MODIFIABLE =3D 20, + SGX_INSUFFICIENT_ENTROPY =3D 29, + SGX_NO_UPDATE =3D 31, SGX_UNMASKED_EVENT =3D 128, }; =20 --=20 2.45.2 From nobody Sat Oct 4 17:34:15 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A619926E6FA; Thu, 14 Aug 2025 07:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755157044; cv=none; b=kPGYmCYUbDuQSnoE4C05NBQJAoyX5MLnYW/MXB1B5UIVMvkSe6+C66bc3w0k8twCAhemcyjg8nAeE+gLyQzwSfOZ5+TXpiwbG9PZgTXE43FE1QDYMKqGZLV47JZPhhTaPYKIIgs/8tTJ8n4SQiCBh5rogoDnNUGfxhpvHxEWZv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755157044; c=relaxed/simple; bh=Q0UikNNKWhU9lwVX6LG35CRzooO0wDgnF6BjTRSFFuw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Bk/0ZLfXGP6mdjxlJFbjVAUUkxmQ2fE4FDnOyr6hNGo4YVimLGFgJIxyFg28CenLkWSeCXRDzlE+mBfejJbL5owNNArkDk9HquqzhbhEGPr4o6K9Czsmkbw9hi8UeIXTGos+UMmB0ZdaowNIRlAcwUhoFRYDzA6lI/L1MteVDd4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JdfgBXzk; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JdfgBXzk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755157042; x=1786693042; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q0UikNNKWhU9lwVX6LG35CRzooO0wDgnF6BjTRSFFuw=; b=JdfgBXzkAYtA/IINJdZWUDc1we2iDAaGh+rV7hdiOjVdEX4hJWrgqXS0 ob/l/ojhh/zjbpRFmZt2sL9xb2q/CbuiVqIeN6lJBJVkqou3ScP3KqSQs MU4yumA+wwRKqDb9EADW6TVpGezyumI7yD/DPRK5iTI2WqiyTy1yzgh++ SmykTLOXuSVNXL+fDfZAGcfIdIhZqXkusKmjZXuoNuobxYV3yY/w3/xGE 4/bi0FUn3ODOGeoLdH6leA8OaOPjI4h4BqgXt+Fb/AFnNOP142KLo8qb/ FEW6KJII9jrzYg/v7pg2fdMtbAaeeWU1CWoBxh/MBI0rVa8lLRsWdGnP/ g==; X-CSE-ConnectionGUID: ulq7aNNDRHCAcpIos/2XKQ== X-CSE-MsgGUID: nG1zJldpTP6M+YyV1BVXqg== X-IronPort-AV: E=McAfee;i="6800,10657,11520"; a="82899385" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="82899385" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2025 00:37:22 -0700 X-CSE-ConnectionGUID: +XO+oGZrT06LLAN3wIuYYQ== X-CSE-MsgGUID: fyHuI/ocSau5WGKZbYUk9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="171927395" Received: from foboril-desk.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.138]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2025 00:37:18 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v14 4/5] x86/sgx: Implement ENCLS[EUPDATESVN] Date: Thu, 14 Aug 2025 10:34:24 +0300 Message-ID: <20250814073640.1507050-5-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250814073640.1507050-1-elena.reshetova@intel.com> References: <20250814073640.1507050-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All running enclaves and cryptographic assets (such as internal SGX encryption keys) are assumed to be compromised whenever an SGX-related microcode update occurs. To mitigate this assumed compromise the new supervisor SGX instruction ENCLS[EUPDATESVN] can generate fresh cryptographic assets. Before executing EUPDATESVN, all SGX memory must be marked as unused. This requirement ensures that no potentially compromised enclave survives the update and allows the system to safely regenerate cryptographic assets. Add the method to perform ENCLS[EUPDATESVN]. However, until the follow up patch that wires calling sgx_update_svn() from sgx_inc_usage_count(), this code is not reachable. Reviewed-by: Jarkko Sakkinen Signed-off-by: Elena Reshetova Reviewed-by: Kai Huang --- arch/x86/include/asm/sgx.h | 31 +++++++------- arch/x86/kernel/cpu/sgx/encls.h | 5 +++ arch/x86/kernel/cpu/sgx/main.c | 75 +++++++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h index 73348cf4fd78..c2c4c0d22ca4 100644 --- a/arch/x86/include/asm/sgx.h +++ b/arch/x86/include/asm/sgx.h @@ -28,21 +28,22 @@ #define SGX_CPUID_EPC_MASK GENMASK(3, 0) =20 enum sgx_encls_function { - ECREATE =3D 0x00, - EADD =3D 0x01, - EINIT =3D 0x02, - EREMOVE =3D 0x03, - EDGBRD =3D 0x04, - EDGBWR =3D 0x05, - EEXTEND =3D 0x06, - ELDU =3D 0x08, - EBLOCK =3D 0x09, - EPA =3D 0x0A, - EWB =3D 0x0B, - ETRACK =3D 0x0C, - EAUG =3D 0x0D, - EMODPR =3D 0x0E, - EMODT =3D 0x0F, + ECREATE =3D 0x00, + EADD =3D 0x01, + EINIT =3D 0x02, + EREMOVE =3D 0x03, + EDGBRD =3D 0x04, + EDGBWR =3D 0x05, + EEXTEND =3D 0x06, + ELDU =3D 0x08, + EBLOCK =3D 0x09, + EPA =3D 0x0A, + EWB =3D 0x0B, + ETRACK =3D 0x0C, + EAUG =3D 0x0D, + EMODPR =3D 0x0E, + EMODT =3D 0x0F, + EUPDATESVN =3D 0x18, }; =20 /** diff --git a/arch/x86/kernel/cpu/sgx/encls.h b/arch/x86/kernel/cpu/sgx/encl= s.h index 99004b02e2ed..d9160c89a93d 100644 --- a/arch/x86/kernel/cpu/sgx/encls.h +++ b/arch/x86/kernel/cpu/sgx/encls.h @@ -233,4 +233,9 @@ static inline int __eaug(struct sgx_pageinfo *pginfo, v= oid *addr) return __encls_2(EAUG, pginfo, addr); } =20 +/* Attempt to update CPUSVN at runtime. */ +static inline int __eupdatesvn(void) +{ + return __encls_ret_1(EUPDATESVN, ""); +} #endif /* _X86_ENCLS_H */ diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 3a5cbd1c170e..69ab28641e20 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "driver.h" #include "encl.h" #include "encls.h" @@ -917,6 +918,80 @@ int sgx_set_attribute(unsigned long *allowed_attribute= s, } EXPORT_SYMBOL_GPL(sgx_set_attribute); =20 +/* Counter to count the active SGX users */ +static int sgx_usage_count; + +/** + * sgx_update_svn() - Attempt to call ENCLS[EUPDATESVN]. + * + * This instruction attempts to update CPUSVN to the + * currently loaded microcode update SVN and generate new + * cryptographic assets. + * + * Return: + * * %0: - Success or not supported + * * %-EAGAIN: - Can be safely retried, failure is due to lack of + * * entropy in RNG + * * %-EIO: - Unexpected error, retries are not advisable + */ +static int __maybe_unused sgx_update_svn(void) +{ + int ret; + + /* + * If EUPDATESVN is not available, it is ok to + * silently skip it to comply with legacy behavior. + */ + if (!cpu_feature_enabled(X86_FEATURE_SGX_EUPDATESVN)) + return 0; + + /* + * EPC is guaranteed to be empty when there are no users. + * Ensure we are on our first user before proceeding further. + */ + WARN(sgx_usage_count, "Elevated usage count when calling EUPDATESVN\n"); + + for (int i =3D 0; i < RDRAND_RETRY_LOOPS; i++) { + ret =3D __eupdatesvn(); + + /* Stop on success or unexpected errors: */ + if (ret !=3D SGX_INSUFFICIENT_ENTROPY) + break; + } + + switch (ret) { + case 0: + /* + * SVN successfully updated. + * Let users know when the update was successful. + */ + pr_info("SVN updated successfully\n"); + return 0; + case SGX_NO_UPDATE: + /* + * SVN update failed since the current SVN is + * not newer than CPUSVN. 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Before an EUPDATESVN operation can be successful, all SGX memory (aka. EPC) must be marked as =E2=80=9Cunused=E2=80=9D in the SGX hardware m= etadata (aka.EPCM). This requirement ensures that no compromised enclave can survive the EUPDATESVN procedure and provides an opportunity to generate new cryptographic assets. =3D=3D Solution =3D=3D Attempt to execute ENCLS[EUPDATESVN] every time the first file descriptor is obtained via sgx_(vepc_)open(). In the most common case the microcode SVN is already up-to-date, and the operation succeeds without updating SVN. Note: while in such cases the underlying crypto assets are regenerated, it does not affect enclaves' visible keys obtained via EGETKEY instruction. If it fails with any other error code than SGX_INSUFFICIENT_ENTROPY, this is considered unexpected and the *open() returns an error. This should not happen in practice. On contrary, SGX_INSUFFICIENT_ENTROPY might happen due to a pressure on the system's DRNG (RDSEED) and therefore the *open() can be safely retried to allow normal enclave operation. [1] Runtime Microcode Updates with Intel Software Guard Extensions, https://cdrdv2.intel.com/v1/dl/getContent/648682 Reviewed-by: Jarkko Sakkinen Signed-off-by: Elena Reshetova Reviewed-by: Kai Huang --- arch/x86/kernel/cpu/sgx/main.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 69ab28641e20..cff5c4d22ac2 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -934,7 +934,7 @@ static int sgx_usage_count; * * entropy in RNG * * %-EIO: - Unexpected error, retries are not advisable */ -static int __maybe_unused sgx_update_svn(void) +static int sgx_update_svn(void) { int ret; =20 @@ -992,14 +992,29 @@ static int __maybe_unused sgx_update_svn(void) return -EIO; } =20 +/* Mutex to ensure no concurrent EPC accesses during EUPDATESVN */ +static DEFINE_MUTEX(sgx_svn_lock); + int sgx_inc_usage_count(void) { + int ret; + + guard(mutex)(&sgx_svn_lock); + + if (!sgx_usage_count) { + ret =3D sgx_update_svn(); + if (ret) + return ret; + } + + sgx_usage_count++; + return 0; } =20 void sgx_dec_usage_count(void) { - return; + sgx_usage_count--; } =20 static int __init sgx_init(void) --=20 2.45.2