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Wed, 13 Aug 2025 18:00:14 -0700 (PDT) Received: from harrison-Surface-Pro-12in-1st-Ed-with-Snapdragon.lan ([101.178.35.31]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76be9143983sm28875783b3a.1.2025.08.13.18.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Aug 2025 18:00:13 -0700 (PDT) From: Harrison Vanderbyl To: marcus@nazgul.ch, kirill@korins.ky, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mani@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, andersson@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org Cc: Harrison Vanderbyl Subject: [PATCH 3/3] dts: describe x1e80100 ufs Date: Thu, 14 Aug 2025 10:59:04 +1000 Message-ID: <20250814005904.39173-4-harrison.vanderbyl@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250814005904.39173-1-harrison.vanderbyl@gmail.com> References: <20250814005904.39173-1-harrison.vanderbyl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe device tree entry for x1e80100 ufs device Signed-off-by: Harrison Vanderbyl --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 91 ++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index a9a7bb676c6f..effa776e3dd0 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2819,6 +2819,97 @@ tsens3: thermal-sensor@c274000 { #thermal-sensor-cells =3D <1>; }; =20 + + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,x1e80100-ufshc", + "qcom,ufshc", "jedec,ufs-2.0"; + reg =3D <0 0x01d84000 0 0x3000>; =20 + =09 + =09 + interrupts =3D ; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + lanes-per-direction =3D <2>; + + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + + reset-gpios =3D <&tlmm 238 GPIO_ACTIVE_LOW>; + reset-names =3D "rst"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + + iommus =3D <&apps_smmu 0x1a0 0x0>; + + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + freq-table-hz =3D <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ufs-ddr", "cpu-ufs"; + + qcom,ice =3D <&ice>; + + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d80000 { + compatible =3D "qcom,x1e80100-qmp-ufs-phy"; + reg =3D <0 0x01d80000 0 0x2000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + clock-names =3D "ref", + "ref_aux", + "qref"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ice: crypto@1d90000 { + compatible =3D "qcom,x1e80100-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0 0x1d88000 0 0x8000>; + + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + usb_1_ss0_hsphy: phy@fd3000 { compatible =3D "qcom,x1e80100-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; --=20 2.48.1