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Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 57 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index b66bc13c0b5e337bf9a95b4da4af33b691c14fb5..917d67a6a237a0aee3445212e34= 57cc723ab4276 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include +#include #include +#include +#include #include #include #include @@ -1659,6 +1663,19 @@ data-pins { }; }; =20 + gpucc: clock-controller@5090000 { + compatible =3D "qcom,qcs615-gpucc"; + reg =3D <0 0x05090000 0 0x9000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + stm@6002000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0x0 0x06002000 0x0 0x1000>, @@ -3520,6 +3537,46 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + videocc: clock-controller@ab00000 { + compatible =3D "qcom,qcs615-videocc"; + reg =3D <0 0x0ab00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@ad00000 { + compatible =3D "qcom,qcs615-camcc"; + reg =3D <0 0x0ad00000 0 0x10000>; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index 917d67a6a237a0aee3445212e3457cc723ab4276..50cd9275e4028eb8f689eae215b= f47a9e06d4cfb 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -36,6 +36,8 @@ cpu0: cpu@0 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_0>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 l2_0: l2-cache { @@ -56,6 +58,8 @@ cpu1: cpu@100 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_100>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_100: l2-cache { compatible =3D "cache"; @@ -75,6 +79,8 @@ cpu2: cpu@200 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_200>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_200: l2-cache { compatible =3D "cache"; @@ -94,6 +100,8 @@ cpu3: cpu@300 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_300>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_300: l2-cache { compatible =3D "cache"; @@ -113,6 +121,8 @@ cpu4: cpu@400 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_400>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_400: l2-cache { compatible =3D "cache"; @@ -132,6 +142,8 @@ cpu5: cpu@500 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_500>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_500: l2-cache { compatible =3D "cache"; @@ -151,6 +163,8 @@ cpu6: cpu@600 { capacity-dmips-mhz =3D <1740>; dynamic-power-coefficient =3D <404>; next-level-cache =3D <&l2_600>; + clocks =3D <&cpufreq_hw 1>; + qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; =20 l2_600: l2-cache { @@ -171,6 +185,8 @@ cpu7: cpu@700 { capacity-dmips-mhz =3D <1740>; dynamic-power-coefficient =3D <404>; next-level-cache =3D <&l2_700>; + clocks =3D <&cpufreq_hw 1>; + qcom,freq-domain =3D <&cpufreq_hw 1>; =20 l2_700: l2-cache { compatible =3D "cache"; @@ -4137,6 +4153,19 @@ compute-cb@6 { }; }; }; + + cpufreq_hw: cpufreq@18323000 { + compatible =3D "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; + reg =3D <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names =3D "freq-domain0", "freq-domain1"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + }; =20 arch_timer: timer { --=20 2.34.1