From nobody Sat Oct 4 15:59:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0836A2FCC04; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; cv=none; b=BEw4O13D8QmYy63jbdyRa3pKgo6UJ61zTaOg1ND3Rd/J4P3Be56pPNiRz37sWI+zygXWoBGyzoZda4dCvoTr3gPhxVNGD/bDz6XJdLjs1rogk3T1MrYvbiBmQ9YORYWpx5tNDj7e1YwjBiPYBSPU/9iYKg98x6cx3E3HKfsnxe0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; c=relaxed/simple; bh=2jFiYxsc1WNyJnCv5lLuEcDugJS6KmrHs3sFZz6rVfE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oOgh+eI7l0hVRhHCd5JQ2qbBArsiDtK2tzD7GZRepQr7ARd0OWtYSa43hi3C3iLbB//RKxvQCkp4KIL0sFHDQWERrgd+Qi+H/es863tWTNGlZoFlA+8CLte4VxABXMXEoMLG4hI09M0N14Ort9i5ROCNx1lBWjpi9tlammmWDpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DYYTFTce; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DYYTFTce" Received: by smtp.kernel.org (Postfix) with ESMTPS id A6088C4CEF1; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755168733; bh=2jFiYxsc1WNyJnCv5lLuEcDugJS6KmrHs3sFZz6rVfE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DYYTFTceJjguCMyW+98E7fR+ugsPYgZyNN55gxpIR8IMn965+MXlfyXG0z966TLkj k2xL2q1nAkIKWEXnZp8Nf4NJ6qOXN3idVjdSZEifVYPFzXui42cYj1qDSv1P9Q6f/M zwI+REKg9AttYpJu/v9+j663Vvsz4S2eKY9f7yJZcnZ62QYwVnOvkSpyADVLus0C+D PZgrdr3KPIm2gt+clOaiNqtiHoIlPpp7WpibKsAOOLWHgGdkCnsZBG7LLqRE7IvFBc hnOKMNcfuCkbSsohnTonqWRyaJ5UgJtPEl2g9POQqBgzEQCy1ry46sW8eVVKgHg1/R DU45GSiGKrBug== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94E42CA0EDC; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Thu, 14 Aug 2025 11:52:23 +0100 Subject: [PATCH 1/6] dt-binbings: mfd: Add bindings for the LTC4283 Swap Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-ltc4283-support-v1-1-88b2cef773f2@analog.com> References: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> In-Reply-To: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> To: linux-hwmon@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jean Delvare , Guenter Roeck , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755168752; l=3762; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=jZczKELD9tr25sgoyyPTOyUqiGRTqVv0NPtNl4m1Aps=; b=x3h8XfOKIQ6nRfIb0Dexb7UHnFFxW4fEypnSf0LYhdxBmnaR8xSL/pbeFnelzNOpzH7C3BAX2 GOt4VD2POJQDt2PWoijtrlPD0qnZ7eMuRYmcXo+PoImyoe4kLVbPXCQ X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno S=C3=A1 The LTC4283 is a negative voltage hot swap controller that drives an external N-channel MOSFET to allow a board to be safely inserted and removed from a live backplane. Main usage is as an Hardware Monitoring device. However, it has up to 8 pins that can be configured and used as GPIOs and hence, the device can also be a GPIO controller. Signed-off-by: Nuno S=C3=A1 --- .../devicetree/bindings/mfd/adi,ltc4283.yaml | 85 ++++++++++++++++++= ++++ MAINTAINERS | 7 ++ 2 files changed, 92 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml b/Docum= entation/devicetree/bindings/mfd/adi,ltc4283.yaml new file mode 100644 index 0000000000000000000000000000000000000000..c5e8aec887d9cfad9052a7c2878= 3396efd6804a9 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/adi,ltc4283.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LTC4283 I2C Negative Voltage Hot Swap Controller + +maintainers: + - Nuno S=C3=A1 + +description: | + The LTC4283 negative voltage hot swap controller drives an external N-ch= annel + MOSFET to allow a board to be safely inserted and removed from a live + backplane. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4= 283.pdf + +properties: + compatible: + enum: + - adi,ltc4283 + + reg: + maxItems: 1 + + gpio: + $ref: /schemas/gpio/adi,ltc4283.yaml + hwmon: + $ref: /schemas/hwmon/adi,ltc4283.yaml + + adi,gpio-pins: + description: + The pins to use as GPIOs. The device has 4 ADIO and 4 PGIO + pins than can be used as GPIOs. The ADIO pins are numbered from 0 to= 3 + and the PGIO pins are numbered from 4 to 7. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + items: + minimum: 0 + maximum: 7 + +dependencies: + gpio: + - adi,gpio-pins + +required: + - compatible + - reg + - hwmon + +additionalProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + swap-controller@15 { + compatible =3D "adi,ltc4283"; + reg =3D <0x15>; + + /* pgio1 to pgio4 as gpios */ + adi,gpio-pins =3D <0 1 2 3>; + + gpio { + compatible =3D "adi,ltc4283-gpio"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + hwmon { + compatible =3D "adi,ltc4283-hwmon"; + + adi,rsense-nano-ohms =3D <500>; + adi,current-limit-sense-microvolt =3D <25000>; + adi,current-limit-foldback-factor =3D <10>; + adi,cooling-delay-ms =3D <8190>; + adi,fet-bad-timer-delay-ms =3D <512>; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index e90710a9b40d7b32c151472a9ac3b02efd95f346..413bb77d5eebe2b51aa9c3af86e= 7cfd5ab142044 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14500,6 +14500,13 @@ F: Documentation/devicetree/bindings/hwmon/adi,ltc= 4282.yaml F: Documentation/hwmon/ltc4282.rst F: drivers/hwmon/ltc4282.c =20 +lTC4283 HARDWARE MONITOR AND GPIO DRIVER +M: Nuno S=C3=A1 +L: linux-hwmon@vger.kernel.org +L: linux-gpio@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml + LTC4286 HARDWARE MONITOR DRIVER M: Delphine CC Chiu L: linux-hwmon@vger.kernel.org --=20 2.50.1 From nobody Sat Oct 4 15:59:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 175A52FD1A9; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; cv=none; b=EJo4SxHuRBUl+/I3tGKeaLUX966x2EnRfK3uYE83VTrwBOP2dOEgzgo+q7FAtjQLaitLM5/PglLqWBVtHuvOA7xq7RYYyoQLMn/QjD9ZbqToOpTckAoC8Jnah1JlSufK747djSAZv5bbrof+FkUofEm5AwUTNyphMOzE2HE92/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; c=relaxed/simple; bh=cCEgYLnJf+5grhqhoUEvF8DCQ1F3ij1AI1rFPHd0Smw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IJZ/Msndjjga2YfGq6A2w6oEaC/Qjl0ZCFmTe7HEQVkPi7Fh0IHY8g20K3W8M/3N+5i+SZGmN4MLYHCynjxxmjUz2Fnjji9LTz5H1oSfpsgDyntT3/QpTDZ4rDNS5bpuMUjhb5j5uPjUyaki3w3mxmvnbco/U0hJwghpkoqs6fg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YTuyRrM2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YTuyRrM2" Received: by smtp.kernel.org (Postfix) with ESMTPS id B1723C4CEEF; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755168733; bh=cCEgYLnJf+5grhqhoUEvF8DCQ1F3ij1AI1rFPHd0Smw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YTuyRrM2AJbmp+987JBvu/I4lRFyBopz/rHTXPOcqz+j/02nE2Y4XGH/VKick5eV1 tyylKzd36Deg0waMzw5JbF2DgG+zTjtuwFclZDC/5ckAcUOjnkpZwsOrOv4QlCIr/U WWXTt6xj/Wy+ldcve3b/CxwKFyMuAtOY1ARq5ImPpDnPSMIOaDD5GpEwEyoLg56TqG Jia9ARGGM9RgzkWwigT7CSy0du2SRyzURsfqk/gXJYh4ODiP5kaEBTVK35ugLwyq6N 1/wC8PahfGLWuw3irOMKUqopE4RpL3Bw6X9K32xYICDF4glNIE1Ww3NOufB54g64mz Nw+H2UWRuwzMg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3AC8CA0EE6; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Thu, 14 Aug 2025 11:52:24 +0100 Subject: [PATCH 2/6] mfd: ltc4283: Add support for the LTC4283 Swap Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-ltc4283-support-v1-2-88b2cef773f2@analog.com> References: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> In-Reply-To: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> To: linux-hwmon@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jean Delvare , Guenter Roeck , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755168752; l=7869; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=YJEiTHe9kb+DC8FT96u8vbrt9euhbvLgsuaavOLJvd0=; b=tNjM9wTGeiBzHFn7funqVFxJYEEVNZPoI1tUkvZkprAg+plh0sz0LBZQlK5MJ7vjcFs3+I0VC 6AbVLXGzHEbCL4PQXQ2qz3GfaV3ev+GdoXiqRvVB3MhlrL17E4cglFh X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno S=C3=A1 The LTC4283 is a negative voltage hot swap controller that drives an external N-channel MOSFET to allow a board to be safely inserted and removed from a live backplane. Main usage is as an Hardware Monitoring device. However, it has up to 8 pins that can be configured and used as GPIOs and hence, the device can also be a GPIO controller (and so being added as MFD device). Signed-off-by: Nuno S=C3=A1 --- MAINTAINERS | 2 + drivers/mfd/Kconfig | 11 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/ltc4283.c | 140 ++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/mfd/ltc4283.h | 33 +++++++++++ 5 files changed, 187 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 413bb77d5eebe2b51aa9c3af86e7cfd5ab142044..b5f4f1c41c64b738d57c1fb5552= a60b4c6b9985c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14506,6 +14506,8 @@ L: linux-hwmon@vger.kernel.org L: linux-gpio@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml +F: drivers/mfd/ltc4283.c +F: include/linux/mfd/ltc4283.h =20 LTC4286 HARDWARE MONITOR DRIVER M: Delphine CC Chiu diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 425c5fba6cb1e7848dcea05bd77c729a71d48e2c..ec3e02d40fd17a0bba29e315772= 3055feedebd11 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -900,6 +900,17 @@ config MFD_MAX14577 additional drivers must be enabled in order to use the functionality of the device. =20 +config MFD_LTC4283 + tristate "LTC4283 Hot Swap Controller" + depends on I2C + select MFD_CORE + select REGMAP_I2C + help + This enables support for the LTC4283 Negative Voltage Hot Swap + Controller. This driver provides common support for accessing the + device; additional drivers must be enabled in order to use the + functionality of the device. + config MFD_MAX77541 tristate "Analog Devices MAX77541/77540 PMIC Support" depends on I2C=3Dy diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index f7bdedd5a66d16bf8ccee0da1236a441e6f085b0..4a3bcd30ab7e12aed4bc5e48294= 500c77cb61aa7 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_MFD_EXYNOS_LPASS) +=3D exynos-lpass.o obj-$(CONFIG_MFD_GATEWORKS_GSC) +=3D gateworks-gsc.o obj-$(CONFIG_MFD_MACSMC) +=3D macsmc.o =20 +obj-$(CONFIG_MFD_LTC4283) +=3D ltc4283.o obj-$(CONFIG_MFD_TI_LP873X) +=3D lp873x.o obj-$(CONFIG_MFD_TI_LP87565) +=3D lp87565.o obj-$(CONFIG_MFD_TI_AM335X_TSCADC) +=3D ti_am335x_tscadc.o diff --git a/drivers/mfd/ltc4283.c b/drivers/mfd/ltc4283.c new file mode 100644 index 0000000000000000000000000000000000000000..a45c01278f884630984790c922c= 057c4f2db9c82 --- /dev/null +++ b/drivers/mfd/ltc4283.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices LTC4283 I2C Negative Voltage Hot Swap Controller + * + * Copyright 2025 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static const struct mfd_cell ltc4283_cells[] =3D { + MFD_CELL_OF("ltc4283-hwmon", NULL, NULL, 0, 0, "adi,ltc4283-hwmon"), + MFD_CELL_OF("ltc4283-gpio", NULL, NULL, 0, 0, "adi,ltc4283-gpio"), +}; + +static bool ltc4283_writable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0x00 ... 0x03: + return false; + case 0x3c: + return false; + case 0x86 ... 0x8f: + return false; + case 0x91 ... 0xa1: + return false; + case 0xa3: + return false; + case 0xac: + return false; + case 0xf1 ... 0xff: + return false; + default: + return true; + } +} + +static const struct regmap_config ltc4283_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D 0xff, + .writeable_reg =3D ltc4283_writable_reg, +}; + +static int ltc4283_get_gpio_pins(struct i2c_client *client, u32 *n_cells) +{ + struct device *dev =3D &client->dev; + u32 pins[LTC4283_GPIO_MAX], pin; + unsigned long *gpio_mask; + int n_pins, ret; + + /* + * The device has up to 8 pins that can be configured either as GPIOS or + * for monitoring purposes. Both gpio and hwmon devices need to have + * this information in order to do proper validations and + * configurations. Hence, this property needs to be in the top level + * device. + */ + n_pins =3D device_property_count_u32(dev, "adi,gpio-pins"); + if (n_pins < 0) + return 0; + if (n_pins >=3D LTC4283_GPIO_MAX) + return dev_err_probe(dev, -EINVAL, "Too many GPIO pins specified (%d), m= ax is %d\n", + n_pins, LTC4283_GPIO_MAX); + + ret =3D device_property_read_u32_array(dev, "adi,gpio-pins", pins, n_pins= ); + if (ret) + return dev_err_probe(dev, ret, "Failed to read GPIO pins\n"); + + gpio_mask =3D devm_bitmap_zalloc(dev, LTC4283_GPIO_MAX, GFP_KERNEL); + if (!gpio_mask) + return -ENOMEM; + + for (pin =3D 0; pin < n_pins; pin++) { + if (pins[pin] >=3D LTC4283_GPIO_MAX) + return dev_err_probe(dev, -EINVAL, + "Invalid GPIO pin specified (%u), max is %d\n", + pins[pin], LTC4283_GPIO_MAX); + + __set_bit(pins[pin], gpio_mask); + } + + /* Add the GPIO cell */ + *n_cells +=3D 1; + i2c_set_clientdata(client, gpio_mask); + + return 0; +} + +static int ltc4283_probe(struct i2c_client *client) +{ + u32 n_cells =3D ARRAY_SIZE(ltc4283_cells) - 1; + struct regmap *regmap; + int ret; + + regmap =3D devm_regmap_init_i2c(client, <c4283_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret =3D ltc4283_get_gpio_pins(client, &n_cells); + if (ret) + return ret; + + return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, + ltc4283_cells, n_cells, NULL, 0, NULL); +} + +static const struct of_device_id ltc4283_of_match[] =3D { + { .compatible =3D "adi,ltc4283" }, + { } +}; +MODULE_DEVICE_TABLE(of, ltc4283_of_match); + +static const struct i2c_device_id ltc4283_i2c_id[] =3D { + { "ltc4283" }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ltc4283_i2c_id); + +static struct i2c_driver ltc4283_driver =3D { + .driver =3D { + .name =3D "ltc4283", + .of_match_table =3D ltc4283_of_match, + }, + .probe =3D ltc4283_probe, + .id_table =3D ltc4283_i2c_id, +}; +module_i2c_driver(ltc4283_driver); + +MODULE_AUTHOR("Nuno S=C3=A1 "); +MODULE_DESCRIPTION("LTC4283 MFD I2C driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/ltc4283.h b/include/linux/mfd/ltc4283.h new file mode 100644 index 0000000000000000000000000000000000000000..153594009c07b296ce5743e5e81= 7e96464d81cb3 --- /dev/null +++ b/include/linux/mfd/ltc4283.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Analog Devices LTC4283 I2C Negative Voltage Hot Swap Controller + * + * Copyright 2025 Analog Devices Inc. + */ + +#ifndef __MFD_LTC4283_H_ +#define __MFD_LTC4283_H_ + +#include +#include + +/* + * We can have up to 8 gpios. 4 PGIOs and 4 ADIOs. PGIOs start at index 4 = in the + * gpios mask. + */ +#define LTC4283_PGIOX_START_NR 4 + +#define LTC4283_PGIO_CONFIG 0x10 +#define LTC4283_PGIO_CFG_MASK(pin) \ + GENMASK(((pin) - LTC4283_PGIOX_START_NR) * 2 + 1, (((pin) - LTC4283_PGIOX= _START_NR) * 2)) +#define LTC4283_PGIO_CONFIG_2 0x11 +#define LTC4283_ADC_MASK GENMASK(2, 0) +#define LTC4283_PGIO_OUT_MASK(pin) BIT(4 + (pin)) + +#define LTC4283_GPIO_MAX 8 + +/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +#endif --=20 2.50.1 From nobody Sat Oct 4 15:59:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4E24318138; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; cv=none; b=bni/X6inJBZ8eJaF4abXH8f3MfG5bGVaP9Li0UaUZxsEEcpPdmCq7H23g3IHodM1GscZ2otXS2e0+u6SHNvLmjqQQfwo/kqXqh/iMOPfBRUPs9NiQhfeJI/ruPBIvqEUu/flKx7pcGDZgEfd+nAvZhUTP7iaCoG2Ip86kgL7gFI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; c=relaxed/simple; bh=tuNThMyK+20yfHoL5Rs3ghED3P4RDx1PE6VnCgjUVfg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=prRPgAGA8UwAwaLqBLijPGf+Neo+6kMH1Fj2p61HChWdPC7dFlS6wjbB7EACoL//dJZeUo+54MS0VEPsjgZUNeEGM2j6l0BflNqtj+278xMtdAJdTaF9/FFpwBHVLj4zta5J0JurHBZI1WZG9ei81gsCFPggMvwRo7OWLoIBLJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mlz8Xjz5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mlz8Xjz5" Received: by smtp.kernel.org (Postfix) with ESMTPS id BAD74C4CEF9; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755168733; bh=tuNThMyK+20yfHoL5Rs3ghED3P4RDx1PE6VnCgjUVfg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mlz8Xjz5GT3DDcebvIT5SkVmi+R425lYHqib6cLHMV32xbKOuf5Oej6eMtCQevu26 A1ikRwePb22yXfpIiOEGbsrnoDVAB4vFP6gGDqHmvOqbdOLPOLYXsNfhxIOLy/P5Uh 0qmp+KQIE8EuYtgWdI3+Ayg5muS/4pRMxjRgPbsCaI3ZMFhC+G+p+WRYmlLGGzQn7U TLNKGxW76WIGbZ6e8BR6UDEWkhixLbjA/jBjKeZ5jK8DHFJNWZoaDnrPf2chuxTrYH skeErxXIZa0xby/a4UEKUjK2qJ42ssQUMJWa4uvKkuNX4QHofBHTwhnKoT/uVA+O7u rYQ8raJS51AfQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3A8FCA0ED1; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Thu, 14 Aug 2025 11:52:25 +0100 Subject: [PATCH 3/6] dt-binbings: hwmon: Add bindings for the LTC4283 Swap Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-ltc4283-support-v1-3-88b2cef773f2@analog.com> References: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> In-Reply-To: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> To: linux-hwmon@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jean Delvare , Guenter Roeck , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755168752; l=6973; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=HsDdoBnjwJgf7HxiAniojdoW83Qd+owHP8CXaML6ml4=; b=27DMRJsVWDaaEnYZxcgcr1RPm+1aGmpgHyXN6+ElU4OO6MijcnZbwKuFjtle603REtvrHnXt8 6WuU+XcNdczC7Vq78GUn/aJ7QykX/fjLWcYAasrgDsFaJrrXyz4HwJ2 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno S=C3=A1 Document the bindings for the Hardware monitoring functions of the LTC4283 Hot Swap Controller. Special note for the "adi,vpower-drns-enable" property. It allows to choose between the attenuated MOSFET drain voltage or the attenuated input voltage at the RTNS pin (effectively choosing between input or output power). This is a system level decision not really intended to change at runtime and hence is being added as Firmware property. Signed-off-by: Nuno S=C3=A1 --- .../devicetree/bindings/hwmon/adi,ltc4283.yaml | 159 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 160 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml b/Doc= umentation/devicetree/bindings/hwmon/adi,ltc4283.yaml new file mode 100644 index 0000000000000000000000000000000000000000..5630623fd3dafa1d86e1877de6c= d8844e2826ed2 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,ltc4283.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HWMON LTC4283 Negative Voltage Hot Swap Controller + +maintainers: + - Nuno S=C3=A1 + +description: | + This module is part of the LTC4283 MFD device. + See Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml + This implements the HWMON bindings for the LTC4283 negative voltage hot = swap + controller. + +properties: + compatible: + enum: + - adi,ltc4283-hwmon + + adi,rsense-nano-ohms: + description: Value of the sense resistor. + + adi,current-limit-sense-microvolt: + description: + The current limit sense voltage of the chip is adjustable between + 15mV and 30mV in 1mV steps. This effectively limits the current + on the load. + minimum: 15000 + maximum: 30000 + default: 15000 + + adi,current-limit-foldback-factor: + description: + Specifies the foldback factor for the current limit. The current lim= it + can be reduced (folded back) to one of four preset levels. The value + represents the percentage of the current limit sense voltage to use + during foldback. A value of 100 means no foldback. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 50, 100] + default: 100 + + adi,cooling-delay-ms: + description: + Cooling time to apply after an overcurrent fault, FET bad or + external fault. + enum: [512, 1002, 2005, 4100, 8190, 16400, 32800, 65600] + default: 512 + + adi,fet-bad-timer-delay-ms: + description: + FET bad timer delay. After a FET bad status condition is detected, + this timer is started. If the condition persists for the + specified time, the FET is turned off and a fault is logged. + enum: [256, 512, 1002, 2005] + default: 256 + + adi,power-good-reset-on-fet: + description: + If set, resets the power good status when the MOSFET is turned off. + Otherwise, it resets when a low output voltage is detected. + type: boolean + + adi,fet-turn-off-disable: + description: + If set, the MOSFET is turned off immediately when a FET fault is det= ected. + type: boolean + + adi,tmr-pull-down-disable: + description: Disables 2uA pull-down current on the TMR pin. + type: boolean + + adi,dvdt-inrush-control-disable: + description: + Enables dV/dt inrush control during startup. In dV/dt mode, the inru= sh + current is limited by controlling a constant output voltage ramp rat= e. + If not set, the inrush control mechanism is active current limiting. + type: boolean + + adi,fault-log-enable: + description: + If set, enables logging fault registers and ADC data into EEPROM upo= n a + fault. + type: boolean + + adi,vpower-drns-enable: + description: + If set, enables the attenuated MOSFET drain voltage to be monitored.= This + effectively means that the MOSFET power is monitored. If not set, the + attenuated input voltage (and hence input power) is monitored. + type: boolean + + adi,external-fault-fet-off-enable: + description: Turns MOSFET off following an external fault. + type: boolean + + adi,undervoltage-retry-disable: + description: Do not retry to turn on the MOSFET after an undervoltage = fault. + type: boolean + + adi,overvoltage-retry-disable: + description: Do not retry to turn on the MOSFET after an overvoltage f= ault. + type: boolean + + adi,external-fault-retry-enable: + description: Retry to turn on the MOSFET retry after an external fault. + type: boolean + + adi,overcurrent-retries: + description: Configures auto-retry following an Overcurrent fault. + $ref: /schemas/types.yaml#/definitions/string + enum: [latch-off, "1", "7", unlimited] + default: latch-off + + adi,fet-bad-retries: + description: + Configures auto-retry following a FET bad fault and a consequent MOS= FET + turn off. + $ref: /schemas/types.yaml#/definitions/string + enum: [latch-off, "1", "7", unlimited] + default: latch-off + + adi,pgio1-func: + description: Configures the function of the PGIO1 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good, power_good] + default: inverted_power_good + + adi,pgio2-func: + description: Configures the function of the PGIO2 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good, power_good, active_current_limiting] + default: inverted_power_good + + adi,pgio3-func: + description: Configures the function of the PGIO3 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good_input, power_good_input] + default: inverted_power_good_input + + adi,pgio4-func: + description: Configures the function of the PGIO4 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_external_fault, external_fault] + default: inverted_external_fault + +dependencies: + adi,external-fault-retry-enable: + - adi,pgio4-func + adi,external-fault-fet-off-enable: + - adi,pgio4-func + +required: + - compatible + - adi,rsense-nano-ohms + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index b5f4f1c41c64b738d57c1fb5552a60b4c6b9985c..5f344ed81c80c9c30d6b2ee81bb= 00a44874e3b4c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14505,6 +14505,7 @@ M: Nuno S=C3=A1 L: linux-hwmon@vger.kernel.org L: linux-gpio@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml F: Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml F: drivers/mfd/ltc4283.c F: include/linux/mfd/ltc4283.h --=20 2.50.1 From nobody Sat Oct 4 15:59:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6692FF660; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; cv=none; b=Ei+QP4xPpYbzAc51fMNg2jGjZaGgMhrhfihE+XgkJbvo2mfekka1zjlVU3SS+YS23xvJTSQu3J3xNTqLoctMTpvUd/Z59LxhMe+Okznh/9tpVIAhLHwudVbOMEpDXLnFEzOlIpNoCl6URQQLhSoz8pN+j/1uP6HSa5nfnCm+tfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; c=relaxed/simple; bh=G2O0KydK4Qj9VKEQqHATjTSdJO/DrmMqHCy6HNjw5wA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SGq4lRfMpiOcO5W/W9PVNavOnCGjk9+nXJKTHiJxPokgPuikjeLRR771ZwmYJnMpmxaXdaTjN7STsPXKZfKzVuMXIgeKR8qDS7fVc8y/VsRE9aYRBJudZJS0awRNwlZ8W6hjoTsvgcOoEos7ZmdCg5n6EFaLFG1Y3CiOf82m6Bg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sxcta+TS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sxcta+TS" Received: by smtp.kernel.org (Postfix) with ESMTPS id CB71AC4CEFC; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755168733; bh=G2O0KydK4Qj9VKEQqHATjTSdJO/DrmMqHCy6HNjw5wA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=sxcta+TSx52cPC95nACbqdWpM5Zfh20r9BB0hboHHujhRVadNr54vWitlxYm9/g0e 0lSEAs3ub4/g8epXCxFdza4njYNr0iiF/aCf5YPzCTXE1AL6E1KNDOYhJg3O53mw3Q H7weymEX/gmKk7BiagGIxFwRN3xYHoo4TgdFhwTXHiUSPqgOXDI1Fj0OFmrHlZokJ1 QHEhZvQesGWdGVOhPHKAMQDl8j8vN33jtozqXc+Qz7IjYcTWoWb2kzVKN0Cc6Be+2x O02TtYyYdZPxq9MWlZmlkU0Ygtw2+gT8041kPEIGE8GkuAoYKAgqYNBayMXxHFUMaf mjty2KfD5WGOw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C42F6CA0EE4; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Thu, 14 Aug 2025 11:52:26 +0100 Subject: [PATCH 4/6] hwmon: ltc4283-hwmon: Add support for the LTC4283 Swap Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-ltc4283-support-v1-4-88b2cef773f2@analog.com> References: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> In-Reply-To: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> To: linux-hwmon@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jean Delvare , Guenter Roeck , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755168753; l=63879; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=N4/1H4p1bUK9nWtJ0teQjD5DI+2zhjcMoMIgthFORpA=; b=ZOScXy4hBwTBT7FT8Cx3jfTG6lwbF9IHiUEjXDpXPgrutQtUjTanYvzRp8gaQvZxfshAwG1b7 cpP0921SKzqAKP+yEwdvorNnd5Fk6PPQNs3LF91tDtdrYgf08ezD0SD X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno S=C3=A1 Support the LTC4283 How Swap Controller. The device features programmable current limit with foldback and independently adjustable inrush current to optimize the MOSFET safe operating area (SOA). The SOA timer limits MOSFET temperature rise for reliable protection against overstresses. An I2C interface and onboard ADC allow monitoring of board current, voltage, power, energy, and fault status. Signed-off-by: Nuno S=C3=A1 --- Documentation/hwmon/ltc4283.rst | 266 +++++++ MAINTAINERS | 1 + drivers/hwmon/Kconfig | 10 + drivers/hwmon/Makefile | 1 + drivers/hwmon/ltc4283-hwmon.c | 1658 +++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 1936 insertions(+) diff --git a/Documentation/hwmon/ltc4283.rst b/Documentation/hwmon/ltc4283.= rst new file mode 100644 index 0000000000000000000000000000000000000000..3bad3cf368fa21dfb1797f47b2a= 9154c5d285b8f --- /dev/null +++ b/Documentation/hwmon/ltc4283.rst @@ -0,0 +1,266 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +Kernel drivers ltc4283 +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Supported chips: + + * Analog Devices LTC4283 + + Prefix: 'ltc4283' + + Addresses scanned: - I2C 0x10 - 0x17 (7-bit) + Addresses scanned: - I2C 0x20 - 0x2E (8-bit) + + Datasheet: + + https://www.analog.com/media/en/technical-documentation/data-sheet= s/ltc4283.pdf + +Author: Nuno S=C3=A1 + +Description +___________ + +The LTC4283 negative voltage hot swap controller drives an external N-chan= nel +MOSFET to allow a board to be safely inserted and removed from a live back= plane. +The device features programmable current limit with foldback and independe= ntly +adjustable inrush current to optimize the MOSFET safe operating area (SOA)= . The +SOA timer limits MOSFET temperature rise for reliable protection against +overstresses. An I2C interface and onboard gear-shift ADC allow monitoring= of +board current, voltage, power, energy, and fault status. Additional featu= res +respond to input UV/OV, interrupt the host when a fault has occurred, noti= fy +when output power is good, detect insertion of a board, turn off the MOSFET +if an external supply monitor fails to indicate power good within a timeout +period, and auto-reboot after a programmable delay following a host comman= ded +turn-off. + +Sysfs entries +_____________ + +The following attributes are supported. Limits are read-write and all the = other +attributes are read-only. Note that the VADIOx channels might not be avail= able +if the ADIO pins are used as GPIOs (naturally also affects the respective +differential channels). + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +in0_lcrit_alarm Critical Undervoltage alarm +in0_crit_alarm Critical Overvoltage alarm +in0_label Channel label (VIN) + +in1_input Output voltage (mV). +in1_min Undervoltage threshold +in1_max Overvoltage threshold +in1_lowest Lowest measured voltage +in1_highest Highest measured voltage +in1_reset_history Write 1 to reset history. +in1_min_alarm Undervoltage alarm +in1_max_alarm Overvoltage alarm +in1_label Channel label (VPWR) + +in2_input Output voltage (mV). +in2_min Undervoltage threshold +in2_max Overvoltage threshold +in2_lowest Lowest measured voltage +in2_highest Highest measured voltage +in2_reset_history Write 1 to reset history. +in2_min_alarm Undervoltage alarm +in2_max_alarm Overvoltage alarm +in2_enable Enable/Disable monitoring. +in2_label Channel label (VADI1) + +in3_input Output voltage (mV). +in3_min Undervoltage threshold +in3_max Overvoltage threshold +in3_lowest Lowest measured voltage +in3_highest Highest measured voltage +in3_reset_history Write 1 to reset history. +in3_min_alarm Undervoltage alarm +in3_max_alarm Overvoltage alarm +in3_enable Enable/Disable monitoring. +in3_label Channel label (VADI2) + +in4_input Output voltage (mV). +in4_min Undervoltage threshold +in4_max Overvoltage threshold +in4_lowest Lowest measured voltage +in4_highest Highest measured voltage +in4_reset_history Write 1 to reset history. +in4_min_alarm Undervoltage alarm +in4_max_alarm Overvoltage alarm +in4_enable Enable/Disable monitoring. +in4_label Channel label (VADI3) + +in5_input Output voltage (mV). +in5_min Undervoltage threshold +in5_max Overvoltage threshold +in5_lowest Lowest measured voltage +in5_highest Highest measured voltage +in5_reset_history Write 1 to reset history. +in5_min_alarm Undervoltage alarm +in5_max_alarm Overvoltage alarm +in5_enable Enable/Disable monitoring. +in5_label Channel label (VADI4) + +in6_input Output voltage (mV). +in6_min Undervoltage threshold +in6_max Overvoltage threshold +in6_lowest Lowest measured voltage +in6_highest Highest measured voltage +in6_reset_history Write 1 to reset history. +in6_min_alarm Undervoltage alarm +in6_max_alarm Overvoltage alarm +in6_enable Enable/Disable monitoring. +in6_label Channel label (VADIO1) + +in7_input Output voltage (mV). +in7_min Undervoltage threshold +in7_max Overvoltage threshold +in7_lowest Lowest measured voltage +in7_highest Highest measured voltage +in7_reset_history Write 1 to reset history. +in7_min_alarm Undervoltage alarm +in7_max_alarm Overvoltage alarm +in7_enable Enable/Disable monitoring. +in7_label Channel label (VADIO2) + +in8_input Output voltage (mV). +in8_min Undervoltage threshold +in8_max Overvoltage threshold +in8_lowest Lowest measured voltage +in8_highest Highest measured voltage +in8_reset_history Write 1 to reset history. +in8_min_alarm Undervoltage alarm +in8_max_alarm Overvoltage alarm +in8_enable Enable/Disable monitoring. +in8_label Channel label (VADIO3) + +in9_input Output voltage (mV). +in9_min Undervoltage threshold +in9_max Overvoltage threshold +in9_lowest Lowest measured voltage +in9_highest Highest measured voltage +in9_reset_history Write 1 to reset history. +in9_min_alarm Undervoltage alarm +in9_max_alarm Overvoltage alarm +in9_enable Enable/Disable monitoring. +in9_label Channel label (VADIO4) + +in10_input Output voltage (mV). +in10_min Undervoltage threshold +in10_max Overvoltage threshold +in10_lowest Lowest measured voltage +in10_highest Highest measured voltage +in10_reset_history Write 1 to reset history. +in10_min_alarm Undervoltage alarm +in10_max_alarm Overvoltage alarm +in10_enable Enable/Disable monitoring. +in10_label Channel label (DRNS) + +in11_input Output voltage (mV). +in11_min Undervoltage threshold +in11_max Overvoltage threshold +in11_lowest Lowest measured voltage +in11_highest Highest measured voltage +in11_reset_history Write 1 to reset history. + Also clears fet bad and short fault logs. +in11_min_alarm Undervoltage alarm +in11_max_alarm Overvoltage alarm +in11_enable Enable/Disable monitoring +in11_fault Failure in the MOSFET. Either bad or shorted FET. +in11_label Channel label (DRAIN) + +in12_input Output voltage (mV). +in12_min Undervoltage threshold +in12_max Overvoltage threshold +in12_lowest Lowest measured voltage +in12_highest Highest measured voltage +in12_reset_history Write 1 to reset history. +in12_min_alarm Undervoltage alarm +in12_max_alarm Overvoltage alarm +in12_enable Enable/Disable monitoring. +in12_label Channel label (ADIN2-ADIN1) + +in13_input Output voltage (mV). +in13_min Undervoltage threshold +in13_max Overvoltage threshold +in13_lowest Lowest measured voltage +in13_highest Highest measured voltage +in13_reset_history Write 1 to reset history. +in13_min_alarm Undervoltage alarm +in13_max_alarm Overvoltage alarm +in13_enable Enable/Disable monitoring. +in13_label Channel label (ADIN4-ADIN3) + +in14_input Output voltage (mV). +in14_min Undervoltage threshold +in14_max Overvoltage threshold +in14_lowest Lowest measured voltage +in14_highest Highest measured voltage +in14_reset_history Write 1 to reset history. +in14_min_alarm Undervoltage alarm +in14_max_alarm Overvoltage alarm +in14_enable Enable/Disable monitoring. +in14_label Channel label (ADIO2-ADIO1) + +in15_input Output voltage (mV). +in15_min Undervoltage threshold +in15_max Overvoltage threshold +in15_lowest Lowest measured voltage +in15_highest Highest measured voltage +in15_reset_history Write 1 to reset history. +in15_min_alarm Undervoltage alarm +in15_max_alarm Overvoltage alarm +in15_enable Enable/Disable monitoring. +in15_label Channel label (ADIO4-ADIO3) + +curr1_input Sense current (mA) +curr1_min Undercurrent threshold +curr1_max Overcurrent threshold +curr1_lowest Lowest measured current +curr1_highest Highest measured current +curr1_reset_history Write 1 to reset curr1 history. + Also clears overcurrent fault logs. +curr1_min_alarm Undercurrent alarm +curr1_max_alarm Overcurrent alarm +curr1_crit_alarm Critical Overcurrent alarm +curr1_label Channel label (ISENSE) + +power1_input Power (in uW) +power1_min Low power threshold +power1_max High power threshold +power1_input_lowest Historical minimum power use +power1_input_highest Historical maximum power use +power1_reset_history Write 1 to reset power1 history. + Also clears power fault logs. +power1_min_alarm Low power alarm +power1_max_alarm High power alarm +power1_label Channel label (Power) + +energy1_input Measured energy over time (in microJoule) +energy1_enable Enable/Disable Energy accumulation + +DebugFs entries +_______________ + +The chip also has a fault log register where failures can be logged. Hence, +as these are logging events, we give access to them in debugfs. Note that +even if some failure is detected in these logs, it does necessarily mean +that the failure is still present. As mentioned in the proper Sysfs entrie= s, +these logs can be cleared by writing in the proper reset_history attribute. + +.. warning:: The debugfs interface is subject to change without notice + and is only available when the kernel is compiled with + ``CONFIG_DEBUG_FS`` defined. + +``/sys/kernel/debug/ltc4282-hwmon[X]/`` +contains the following attributes: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +power1_failed_fault_log Set to 1 by a power1 fault occurring. +power1_good_input_fault_log Set to 1 by a power1 good input fault occurrin= g at PGIO3. +in11_fet_short_fault_log Set to 1 when a FET-short fault occurs. +in11_fet_bad_fault_log Set to 1 when a FET-BAD fault occurs. +in0_lcrit_fault_log Set to 1 by a VIN undervoltage fault occurring. +in0_crit_fault_log Set to 1 by a VIN overvoltage fault occurring. +curr1_crit_fault_log Set to 1 by an overcurrent fault occurring. +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/MAINTAINERS b/MAINTAINERS index 5f344ed81c80c9c30d6b2ee81bb00a44874e3b4c..d5d3018b5424f403e7396f0470a= 12ce8c94a5e49 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14507,6 +14507,7 @@ L: linux-gpio@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml F: Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml +F: drivers/hwmon/ltc4283-hwmon.c F: drivers/mfd/ltc4283.c F: include/linux/mfd/ltc4283.h =20 diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 9d28fcf7cd2a6f9e2f54694a717bd85ff4047b46..4d1979e774e1698ddbf69831632= c2636594c7195 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1157,6 +1157,16 @@ config SENSORS_LTC4282 This driver can also be built as a module. If so, the module will be called ltc4282. =20 +config SENSORS_LTC4283 + tristate "Analog Devices LTC4283" + depends on MFD_LTC4283 + help + If you say yes here you get support for Analog Devices LTC4283 + Negative Voltage Hot Swap Controller I2C interface. + + This driver can also be built as a module. If so, the module will + be called ltc4283-hwmon. + config SENSORS_LTQ_CPUTEMP bool "Lantiq cpu temperature sensor driver" depends on SOC_XWAY diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index cd8bc4752b4dbf015c6eb46157626f4e8f87dfae..ee352f3084b2cc0f2109ae3e7a0= 672bef41ad27a 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -146,6 +146,7 @@ obj-$(CONFIG_SENSORS_LTC4245) +=3D ltc4245.o obj-$(CONFIG_SENSORS_LTC4260) +=3D ltc4260.o obj-$(CONFIG_SENSORS_LTC4261) +=3D ltc4261.o obj-$(CONFIG_SENSORS_LTC4282) +=3D ltc4282.o +obj-$(CONFIG_SENSORS_LTC4283) +=3D ltc4283-hwmon.o obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) +=3D ltq-cputemp.o obj-$(CONFIG_SENSORS_MAX1111) +=3D max1111.o obj-$(CONFIG_SENSORS_MAX127) +=3D max127.o diff --git a/drivers/hwmon/ltc4283-hwmon.c b/drivers/hwmon/ltc4283-hwmon.c new file mode 100644 index 0000000000000000000000000000000000000000..6c815a1e48593d8d761813f9c4d= bb4a1200b6c33 --- /dev/null +++ b/drivers/hwmon/ltc4283-hwmon.c @@ -0,0 +1,1658 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices LTC4283 I2C Negative Voltage Hot Swap Controller (HWMON) + * + * Copyright 2025 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LTC4283_FAULT_STATUS 0x03 +#define LTC4283_OV_MASK BIT(0) +#define LTC4283_UV_MASK BIT(1) +#define LTC4283_OC_MASK BIT(2) +#define LTC4283_FET_BAD_MASK BIT(3) +#define LTC4283_FET_SHORT_MASK BIT(6) +#define LTC4283_FAULT_LOG 0x04 +#define LTC4283_OV_FAULT_MASK BIT(0) +#define LTC4283_UV_FAULT_MASK BIT(1) +#define LTC4283_OC_FAULT_MASK BIT(2) +#define LTC4283_FET_BAD_FAULT_MASK BIT(3) +#define LTC4283_PGI_FAULT_MASK BIT(4) +#define LTC4283_PWR_FAIL_FAULT_MASK BIT(5) +#define LTC4283_FET_SHORT_FAULT_MASK BIT(6) +#define LTC4283_ADC_ALM_LOG_1 0x05 +#define LTC4283_POWER_LOW_ALM BIT(0) +#define LTC4283_POWER_HIGH_ALM BIT(1) +#define LTC4283_SENSE_LOW_ALM BIT(4) +#define LTC4283_SENSE_HIGH_ALM BIT(5) +#define LTC4283_ADC_ALM_LOG_2 0x06 +#define LTC4283_ADC_ALM_LOG_3 0x07 +#define LTC4283_ADC_ALM_LOG_4 0x08 +#define LTC4283_ADC_ALM_LOG_5 0x09 +#define LTC4283_CONTROL_1 0x0a +#define LTC4283_PIGIO2_ACLB_MASK BIT(2) +#define LTC4283_PWRGD_RST_CTRL_MASK BIT(3) +#define LTC4283_FET_BAD_OFF_MASK BIT(4) +#define LTC4283_THERM_TMR_MASK BIT(5) +#define LTC4283_DVDT_MASK BIT(6) +#define LTC4283_CONTROL_2 0x0b +#define LTC4283_OV_RETRY_MASK BIT(0) +#define LTC4283_UV_RETRY_MASK BIT(1) +#define LTC4283_OC_RETRY_MASK GENMASK(3, 2) +#define LTC4283_FET_BAD_RETRY_MASK GENMASK(5, 4) +#define LTC4283_EXT_FAULT_RETRY_MASK BIT(7) +#define LTC4283_CONFIG_1 0x0d +#define LTC4283_FB_MASK GENMASK(3, 2) +#define LTC4283_ILIM_MASK GENMASK(7, 4) +#define LTC4283_CONFIG_2 0x0e +#define LTC4283_COOLING_DL_MASK GENMASK(3, 0) +#define LTC4283_FTBD_DL_MASK GENMASK(5, 4) +#define LTC4283_CONFIG_3 0x0f +#define LTC4283_VPWR_DRNS_MASK BIT(6) +#define LTC4283_EXTFLT_TURN_OFF_MASK BIT(7) +#define LTC4283_ADC_SELECT(c) (0x13 + (c) / 8) +#define LTC4283_ADC_SELECT_MASK(c) BIT((c) % 8) +#define LTC4283_SENSE_MIN_TH 0x1b +#define LTC4283_SENSE_MAX_TH 0x1c +#define LTC4283_VPWR_MIN_TH 0x1d +#define LTC4283_VPWR_MAX_TH 0x1e +#define LTC4283_POWER_MIN_TH 0x1f +#define LTC4283_POWER_MAX_TH 0x20 +#define LTC4283_ADC_2_MIN_TH(c) (0x21 + (c) * 2) +#define LTC4283_ADC_2_MAX_TH(c) (0x22 + (c) * 2) +#define LTC4283_ADC_2_MIN_TH_DIFF(c) (0x39 + (c) * 2) +#define LTC4283_ADC_2_MAX_TH_DIFF(c) (0x3a + (c) * 2) +#define LTC4283_SENSE 0x41 +#define LTC4283_SENSE_MIN 0x42 +#define LTC4283_SENSE_MAX 0x43 +#define LTC4283_VPWR 0x44 +#define LTC4283_VPWR_MIN 0x45 +#define LTC4283_VPWR_MAX 0x46 +#define LTC4283_POWER 0x47 +#define LTC4283_POWER_MIN 0x48 +#define LTC4283_POWER_MAX 0x49 +/* get channels from ADC 2 */ +#define LTC4283_ADC_2(c) (0x4a + (c) * 3) +#define LTC4283_ADC_2_MIN(c) (0x4b + (c) * 3) +#define LTC4283_ADC_2_MAX(c) (0x4c + (c) * 3) +#define LTC4283_ADC_2_DIFF(c) (0x6e + (c) * 3) +#define LTC4283_ADC_2_MIN_DIFF(c) (0x6f + (c) * 3) +#define LTC4283_ADC_2_MAX_DIFF(c) (0x70 + (c) * 3) +#define LTC4283_ENERGY 0x7a +#define LTC4283_METER_CONTROL 0x84 +#define LTC4283_INTEGRATE_I_MASK BIT(0) +#define LTC4283_METER_HALT_MASK BIT(6) +#define LTC4283_FAULT_LOG_CTRL 0x90 +#define LTC4283_FAULT_LOG_EN_MASK BIT(7) + +/* also applies for differential channels */ +#define LTC4283_ADC1_FS_uV 32768 +#define LTC4283_ADC2_FS_mV 2048 +#define LTC4283_TCONV_uS 64103 +#define LTC4283_VILIM_MIN_uV 15000 +#define LTC4283_VILIM_MAX_uV 30000 +#define LTC4283_VILIM_RANGE \ + (LTC4283_VILIM_MAX_uV - LTC4283_VILIM_MIN_uV + 1) + +/* voltage channels */ +enum { + LTC4283_HWMON_VIN, + LTC4283_HWMON_VPWR, + LTC4283_HWMON_ADI_1, + LTC4283_HWMON_ADI_2, + LTC4283_HWMON_ADI_3, + LTC4283_HWMON_ADI_4, + LTC4283_HWMON_ADIO_1, + LTC4283_HWMON_ADIO_2, + LTC4283_HWMON_ADIO_3, + LTC4283_HWMON_ADIO_4, + LTC4283_HWMON_DRNS, + LTC4283_HWMON_DRAIN, + /* differential channels */ + LTC4283_HWMON_ADIN12, + LTC4283_HWMON_ADIN34, + LTC4283_HWMON_ADIO12, + LTC4283_HWMON_ADIO34, + LTC4283_HWMON_CHAN_MAX +}; + +struct ltc4283_hwmon { + struct regmap *map; + + unsigned long *gpio_mask; + /* lock to protect concurrent device accesses and shared data */ + struct mutex lock; + unsigned long ch_enable_mask; + /* in microwatt */ + long power_max; + /* in millivolt */ + u32 vsense_max; + /* in tenths of microohm*/ + u32 rsense; + bool energy_en; + bool ext_fault; +}; + +static int ltc4283_hwmon_read_voltage_word(const struct ltc4283_hwmon *st, + u32 reg, u32 fs, long *val) +{ + __be16 in; + int ret; + + ret =3D regmap_bulk_read(st->map, reg, &in, sizeof(in)); + if (ret) + return ret; + + *val =3D DIV_ROUND_CLOSEST(be16_to_cpu(in) * fs, BIT(16)); + return 0; +} + +static int ltc4283_hwmon_read_voltage_byte(const struct ltc4283_hwmon *st, + u32 reg, u32 fs, long *val) +{ + int ret; + u32 in; + + ret =3D regmap_read(st->map, reg, &in); + if (ret) + return ret; + + *val =3D DIV_ROUND_CLOSEST(in * fs, BIT(8)); + return 0; +} + +static u32 ltc4283_hwmon_in_reg(u32 attr, u32 channel) +{ + switch (attr) { + case hwmon_in_input: + if (channel =3D=3D LTC4283_HWMON_VPWR) + return LTC4283_VPWR; + if (channel >=3D LTC4283_HWMON_ADI_1 && channel <=3D LTC4283_HWMON_DRAIN) + return LTC4283_ADC_2(channel - LTC4283_HWMON_ADI_1); + return LTC4283_ADC_2_DIFF(channel - LTC4283_HWMON_ADIN12); + case hwmon_in_highest: + if (channel =3D=3D LTC4283_HWMON_VPWR) + return LTC4283_VPWR_MAX; + if (channel >=3D LTC4283_HWMON_ADI_1 && channel <=3D LTC4283_HWMON_DRAIN) + return LTC4283_ADC_2_MAX(channel - LTC4283_HWMON_ADI_1); + return LTC4283_ADC_2_MAX_DIFF(channel - LTC4283_HWMON_ADIN12); + case hwmon_in_lowest: + if (channel =3D=3D LTC4283_HWMON_VPWR) + return LTC4283_VPWR_MIN; + if (channel >=3D LTC4283_HWMON_ADI_1 && channel <=3D LTC4283_HWMON_DRAIN) + return LTC4283_ADC_2_MIN(channel - LTC4283_HWMON_ADI_1); + return LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_HWMON_ADIN12); + case hwmon_in_max: + if (channel =3D=3D LTC4283_HWMON_VPWR) + return LTC4283_VPWR_MAX_TH; + if (channel >=3D LTC4283_HWMON_ADI_1 && channel <=3D LTC4283_HWMON_DRAIN) + return LTC4283_ADC_2_MAX_TH(channel - LTC4283_HWMON_ADI_1); + return LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_HWMON_ADIN12); + default: + if (channel =3D=3D LTC4283_HWMON_VPWR) + return LTC4283_VPWR_MIN_TH; + if (channel >=3D LTC4283_HWMON_ADI_1 && channel <=3D LTC4283_HWMON_DRAIN) + return LTC4283_ADC_2_MIN_TH(channel - LTC4283_HWMON_ADI_1); + return LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_HWMON_ADIN12); + } +} + +static int ltc4283_hwmon_read_in_vals(const struct ltc4283_hwmon *st, + u32 attr, u32 channel, long *val) +{ + u32 reg =3D ltc4283_hwmon_in_reg(attr, channel); + int ret; + + if (channel < LTC4283_HWMON_ADIN12) { + if (attr !=3D hwmon_in_max && attr !=3D hwmon_in_min) + return ltc4283_hwmon_read_voltage_word(st, reg, + LTC4283_ADC2_FS_mV, + val); + + return ltc4283_hwmon_read_voltage_byte(st, reg, + LTC4283_ADC2_FS_mV, val); + } + + if (attr !=3D hwmon_in_max && attr !=3D hwmon_in_min) + ret =3D ltc4283_hwmon_read_voltage_word(st, reg, + LTC4283_ADC1_FS_uV, val); + else + ret =3D ltc4283_hwmon_read_voltage_byte(st, reg, + LTC4283_ADC1_FS_uV, val); + if (ret) + return ret; + + *val =3D DIV_ROUND_CLOSEST(*val, MILLI); + return 0; +} + +static int ltc4283_hwmon_read_alarm(struct ltc4283_hwmon *st, u32 reg, + u32 mask, long *val) +{ + u32 alarm; + int ret; + + guard(mutex)(&st->lock); + ret =3D regmap_read(st->map, reg, &alarm); + if (ret) + return ret; + + *val =3D !!(alarm & mask); + + /* If not status/fault logs, clear the alarm after reading it. */ + if (reg !=3D LTC4283_FAULT_STATUS && reg !=3D LTC4283_FAULT_LOG) + return regmap_clear_bits(st->map, reg, mask); + + return 0; +} + +static int ltc4283_hwmon_read_in_alarm(struct ltc4283_hwmon *st, u32 chann= el, + bool max_alm, long *val) +{ + if (channel =3D=3D LTC4283_HWMON_VPWR) + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_1, + BIT(2 + max_alm), val); + + if (channel >=3D LTC4283_HWMON_ADI_1 && channel <=3D LTC4283_HWMON_ADI_4)= { + u32 bit =3D (channel - LTC4283_HWMON_ADI_1) * 2; + /* + * Lower channels go to higher bits. We also want to go +1 down + * in the min_alarm case. + */ + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_2, + BIT(7 - bit - !max_alm), val); + } + + if (channel >=3D LTC4283_HWMON_ADIO_1 && channel <=3D LTC4283_HWMON_ADIO_= 4) { + u32 bit =3D (channel - LTC4283_HWMON_ADIO_1) * 2; + + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_3, + BIT(7 - bit - !max_alm), val); + } + + if (channel >=3D LTC4283_HWMON_ADIN12 && channel <=3D LTC4283_HWMON_ADIN3= 4) { + u32 bit =3D (channel - LTC4283_HWMON_ADIN12) * 2; + + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_5, + BIT(7 - bit - !max_alm), val); + } + + if (channel =3D=3D LTC4283_HWMON_DRNS) + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_4, + BIT(6 + max_alm), val); + + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_4, + BIT(4 + max_alm), val); +} + +static int ltc4283_hwmon_read_in(struct ltc4283_hwmon *st, u32 attr, + u32 channel, long *val) +{ + int ret =3D 0; + + switch (attr) { + case hwmon_in_input: + scoped_guard(mutex, &st->lock) { + if (!test_bit(channel, &st->ch_enable_mask)) + return -ENODATA; + + ret =3D ltc4283_hwmon_read_in_vals(st, attr, channel, val); + } + return ret; + case hwmon_in_highest: + case hwmon_in_lowest: + case hwmon_in_max: + case hwmon_in_min: + return ltc4283_hwmon_read_in_vals(st, attr, channel, val); + case hwmon_in_max_alarm: + return ltc4283_hwmon_read_in_alarm(st, channel, true, val); + case hwmon_in_min_alarm: + return ltc4283_hwmon_read_in_alarm(st, channel, false, val); + case hwmon_in_crit_alarm: + return ltc4283_hwmon_read_alarm(st, LTC4283_FAULT_STATUS, + LTC4283_OV_MASK, val); + case hwmon_in_lcrit_alarm: + return ltc4283_hwmon_read_alarm(st, LTC4283_FAULT_STATUS, + LTC4283_UV_MASK, val); + case hwmon_in_fault: + /* + * We report failure if we detect either a fer_bad or a + * fet_short in the status register. + */ + return ltc4283_hwmon_read_alarm(st, LTC4283_FAULT_STATUS, + LTC4283_FET_BAD_MASK | LTC4283_FET_SHORT_MASK, val); + case hwmon_in_enable: + scoped_guard(mutex, &st->lock) { + *val =3D test_bit(channel, &st->ch_enable_mask); + } + + return 0; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int ltc4283_read_current_word(const struct ltc4283_hwmon *st, u32 r= eg, + long *val) +{ + u64 temp =3D (u64)LTC4283_ADC1_FS_uV * DECA * MILLI; + __be16 curr; + int ret; + + ret =3D regmap_bulk_read(st->map, reg, &curr, sizeof(curr)); + if (ret) + return ret; + + *val =3D DIV64_U64_ROUND_CLOSEST(be16_to_cpu(curr) * temp, + BIT_ULL(16) * st->rsense); + + return 0; +} + +static int ltc4283_read_current_byte(const struct ltc4283_hwmon *st, u32 r= eg, + long *val) +{ + u64 temp =3D (u64)LTC4283_ADC1_FS_uV * DECA * MILLI; + u32 curr; + int ret; + + ret =3D regmap_read(st->map, reg, &curr); + if (ret) + return ret; + + *val =3D DIV_ROUND_CLOSEST_ULL(curr * temp, BIT(8) * st->rsense); + return 0; +} + +static int ltc4283_hwmon_read_curr(struct ltc4283_hwmon *st, u32 attr, + long *val) +{ + switch (attr) { + case hwmon_curr_input: + return ltc4283_read_current_word(st, LTC4283_SENSE, val); + case hwmon_curr_highest: + return ltc4283_read_current_word(st, LTC4283_SENSE_MAX, val); + case hwmon_curr_lowest: + return ltc4283_read_current_word(st, LTC4283_SENSE_MIN, val); + case hwmon_curr_max: + return ltc4283_read_current_byte(st, LTC4283_SENSE_MAX_TH, val); + case hwmon_curr_min: + return ltc4283_read_current_byte(st, LTC4283_SENSE_MIN_TH, val); + case hwmon_curr_max_alarm: + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_1, + LTC4283_SENSE_HIGH_ALM, val); + case hwmon_curr_min_alarm: + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_1, + LTC4283_SENSE_LOW_ALM, val); + case hwmon_curr_crit_alarm: + return ltc4283_hwmon_read_alarm(st, LTC4283_FAULT_STATUS, + LTC4283_OC_MASK, val); + default: + return -EOPNOTSUPP; + } +} + +static int ltc4283_hwmon_read_power_word(const struct ltc4283_hwmon *st, + u32 reg, long *val) +{ + u64 temp =3D (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; + __be16 raw; + int ret; + + ret =3D regmap_bulk_read(st->map, reg, &raw, sizeof(raw)); + if (ret) + return ret; + + /* + * Power is given by: + * P =3D CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense) + */ + *val =3D DIV64_U64_ROUND_CLOSEST(temp * be16_to_cpu(raw), + BIT_ULL(16) * st->rsense); + + return 0; +} + +static int ltc4283_hwmon_read_power_byte(const struct ltc4283_hwmon *st, + u32 reg, long *val) +{ + u64 temp =3D (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; + u32 power; + int ret; + + ret =3D regmap_read(st->map, reg, &power); + if (ret) + return ret; + + *val =3D DIV_ROUND_CLOSEST_ULL(power * temp, BIT(8) * st->rsense); + + return 0; +} + +static int ltc4283_hwmon_read_power(struct ltc4283_hwmon *st, u32 attr, + long *val) +{ + switch (attr) { + case hwmon_power_input: + return ltc4283_hwmon_read_power_word(st, LTC4283_POWER, val); + case hwmon_power_input_highest: + return ltc4283_hwmon_read_power_word(st, LTC4283_POWER_MAX, val); + case hwmon_power_input_lowest: + return ltc4283_hwmon_read_power_word(st, LTC4283_POWER_MIN, val); + case hwmon_power_max_alarm: + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_1, + LTC4283_POWER_HIGH_ALM, val); + case hwmon_power_min_alarm: + return ltc4283_hwmon_read_alarm(st, LTC4283_ADC_ALM_LOG_1, + LTC4283_POWER_LOW_ALM, val); + case hwmon_power_max: + return ltc4283_hwmon_read_power_byte(st, LTC4283_POWER_MAX_TH, + val); + case hwmon_power_min: + return ltc4283_hwmon_read_power_byte(st, LTC4283_POWER_MIN_TH, + val); + default: + return -EOPNOTSUPP; + } +} + +static int ltc4283_hwmon_read(struct device *dev, enum hwmon_sensor_types = type, + u32 attr, int channel, long *val) +{ + struct ltc4283_hwmon *st =3D dev_get_drvdata(dev); + + switch (type) { + case hwmon_in: + return ltc4283_hwmon_read_in(st, attr, channel, val); + case hwmon_curr: + return ltc4283_hwmon_read_curr(st, attr, val); + case hwmon_power: + return ltc4283_hwmon_read_power(st, attr, val); + case hwmon_energy: + scoped_guard(mutex, &st->lock) { + *val =3D st->energy_en; + } + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int ltc4282_write_power_byte(const struct ltc4283_hwmon *st, u32 re= g, + long val) +{ + u64 temp =3D (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; + u32 __raw; + + if (val > st->power_max) + val =3D st->power_max; + + __raw =3D DIV64_U64_ROUND_CLOSEST(val * BIT_ULL(8) * st->rsense, temp); + + return regmap_write(st->map, reg, __raw); +} + +static int ltc4283_hwmon_write_power_word(const struct ltc4283_hwmon *st, + u32 reg, long val) +{ + u64 temp =3D st->rsense * BIT_ULL(16), temp_2; + __be16 __raw; + u16 code; + + if (check_mul_overflow(val, temp, &temp_2)) { + temp =3D DIV_ROUND_CLOSEST_ULL(temp, DECA * MILLI); + code =3D DIV_ROUND_CLOSEST_ULL(temp * val, LTC4283_ADC1_FS_uV * LTC4283_= ADC2_FS_mV); + } else { + temp =3D (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; + code =3D DIV64_U64_ROUND_CLOSEST(temp_2, temp); + } + + __raw =3D cpu_to_be16(code); + return regmap_bulk_write(st->map, reg, &__raw, sizeof(__raw)); +} + +static int ltc4283_hwmon_reset_power_hist(struct ltc4283_hwmon *st) +{ + int ret; + + guard(mutex)(&st->lock); + + ret =3D ltc4283_hwmon_write_power_word(st, LTC4283_POWER_MIN, + st->power_max); + if (ret) + return ret; + + ret =3D ltc4283_hwmon_write_power_word(st, LTC4283_POWER_MAX, 0); + if (ret) + return ret; + + /* Clear possible power faults. */ + return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, + LTC4283_PWR_FAIL_FAULT_MASK | LTC4283_PGI_FAULT_MASK); +} + +static int ltc4283_hwmon_write_power(struct ltc4283_hwmon *st, u32 attr, + long val) +{ + switch (attr) { + case hwmon_power_max: + return ltc4282_write_power_byte(st, LTC4283_POWER_MAX_TH, val); + case hwmon_power_min: + return ltc4282_write_power_byte(st, LTC4283_POWER_MIN_TH, val); + case hwmon_power_reset_history: + return ltc4283_hwmon_reset_power_hist(st); + default: + return -EOPNOTSUPP; + } +} + +static int __ltc4283_hwmon_write_in_history(struct ltc4283_hwmon *st, + u32 reg, long lowest, u32 fs) +{ + __be16 __raw; + u16 tmp; + int ret; + + tmp =3D DIV_ROUND_CLOSEST(BIT(16) * lowest, fs); + if (tmp =3D=3D BIT(16)) + tmp =3D U16_MAX; + + __raw =3D cpu_to_be16(tmp); + + ret =3D regmap_bulk_write(st->map, reg, &__raw, sizeof(__raw)); + if (ret) + return ret; + + tmp =3D 0; + return regmap_bulk_write(st->map, reg + 1, &tmp, sizeof(tmp)); +} + +static int ltc4283_hwmon_write_in_history(struct ltc4283_hwmon *st, + u32 reg, long lowest, u32 fs) +{ + guard(mutex)(&st->lock); + return __ltc4283_hwmon_write_in_history(st, reg, lowest, fs); +} + +static int ltc4283_hwmon_write_in_byte(const struct ltc4283_hwmon *st, + u32 reg, u32 fs, long val) +{ + u32 __raw; + + val =3D clamp_val(val, 0, fs); + __raw =3D DIV_ROUND_CLOSEST(val * BIT(8), fs); + + return regmap_write(st->map, reg, __raw); +} + +static int ltc4283_hwmon_reset_in_hist(struct ltc4283_hwmon *st, u32 chann= el) +{ + u32 reg, fs; + int ret; + + if (channel =3D=3D LTC4283_HWMON_VPWR) + return ltc4283_hwmon_write_in_history(st, LTC4283_VPWR_MIN, + LTC4283_ADC2_FS_mV, + LTC4283_ADC2_FS_mV); + + if (channel >=3D LTC4283_HWMON_ADI_1 && channel <=3D LTC4283_HWMON_DRAIN)= { + fs =3D LTC4283_ADC2_FS_mV; + reg =3D LTC4283_ADC_2_MIN(channel - LTC4283_HWMON_ADI_1); + } else { + fs =3D LTC4283_ADC1_FS_uV; + reg =3D LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_HWMON_ADIN12); + } + + guard(mutex)(&st->lock); + ret =3D __ltc4283_hwmon_write_in_history(st, reg, fs, fs); + if (ret) + return ret; + if (channel !=3D LTC4283_HWMON_DRAIN) + return 0; + + /* Then, let's also clear possible fet faults. */ + return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, + LTC4283_FET_BAD_FAULT_MASK | LTC4283_FET_SHORT_FAULT_MASK); +} + +static int ltc4283_hwmon_write_in_en(struct ltc4283_hwmon *st, u32 channel, + bool en) +{ + unsigned int bit, adc_idx =3D channel - LTC4283_HWMON_ADI_1; + int ret; + + bit =3D LTC4283_ADC_SELECT_MASK(adc_idx); + if (channel > LTC4283_HWMON_DRAIN) + /* Account for two reserved fields after DRAIN. */ + bit <<=3D 2; + + guard(mutex)(&st->lock); + ret =3D regmap_update_bits(st->map, LTC4283_ADC_SELECT(adc_idx), + bit, field_prep(bit, en)); + if (ret) + return ret; + + __assign_bit(channel, &st->ch_enable_mask, en); + return 0; +} + +static int ltc4283_hwmon_write_minmax(struct ltc4283_hwmon *st, long val, + u32 channel, bool is_max) +{ + u32 reg; + + if (channel =3D=3D LTC4283_HWMON_VPWR) { + if (is_max) + return ltc4283_hwmon_write_in_byte(st, LTC4283_VPWR_MAX_TH, + LTC4283_ADC2_FS_mV, val); + + return ltc4283_hwmon_write_in_byte(st, LTC4283_VPWR_MIN_TH, + LTC4283_ADC2_FS_mV, val); + } + + if (channel >=3D LTC4283_HWMON_ADI_1 && channel <=3D LTC4283_HWMON_DRAIN)= { + if (is_max) { + reg =3D LTC4283_ADC_2_MAX_TH(channel - LTC4283_HWMON_ADI_1); + return ltc4283_hwmon_write_in_byte(st, reg, + LTC4283_ADC2_FS_mV, + val); + } + + reg =3D LTC4283_ADC_2_MIN_TH(channel - LTC4283_HWMON_ADI_1); + return ltc4283_hwmon_write_in_byte(st, reg, + LTC4283_ADC2_FS_mV, val); + } + + if (is_max) { + reg =3D LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_HWMON_ADIN12); + return ltc4283_hwmon_write_in_byte(st, reg, + LTC4283_ADC1_FS_uV, + val * MILLI); + } + + reg =3D LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_HWMON_ADIN12); + return ltc4283_hwmon_write_in_byte(st, reg, + LTC4283_ADC1_FS_uV, val * MILLI); +} + +static int ltc4283_hwmon_write_in(struct ltc4283_hwmon *st, u32 attr, long= val, + int channel) +{ + switch (attr) { + case hwmon_in_max: + return ltc4283_hwmon_write_minmax(st, val, channel, true); + case hwmon_in_min: + return ltc4283_hwmon_write_minmax(st, val, channel, false); + case hwmon_in_reset_history: + return ltc4283_hwmon_reset_in_hist(st, channel); + case hwmon_in_enable: + return ltc4283_hwmon_write_in_en(st, channel, !!val); + default: + return -EOPNOTSUPP; + } +} + +static int ltc4283_hwmon_write_curr_byte(const struct ltc4283_hwmon *st, + u32 reg, long val) +{ + u32 temp =3D LTC4283_ADC1_FS_uV * DECA * MILLI; + u32 reg_val; + + reg_val =3D DIV_ROUND_CLOSEST_ULL(val * BIT_ULL(8) * st->rsense, temp); + return regmap_write(st->map, reg, reg_val); +} + +static int ltc4283_hwmon_write_curr_history(struct ltc4283_hwmon *st) +{ + int ret; + + guard(mutex)(&st->lock); + + ret =3D __ltc4283_hwmon_write_in_history(st, LTC4283_SENSE_MIN, + st->vsense_max, + LTC4283_ADC1_FS_uV); + if (ret) + return ret; + + /* Now, let's also clear possible overcurrent logs. */ + return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, + LTC4283_OC_FAULT_MASK); +} + +static int ltc4283_hwmon_write_curr(struct ltc4283_hwmon *st, u32 attr, + long val) +{ + switch (attr) { + case hwmon_curr_max: + return ltc4283_hwmon_write_curr_byte(st, LTC4283_SENSE_MAX_TH, + val); + case hwmon_curr_min: + return ltc4283_hwmon_write_curr_byte(st, LTC4283_SENSE_MIN_TH, + val); + case hwmon_curr_reset_history: + return ltc4283_hwmon_write_curr_history(st); + default: + return -EOPNOTSUPP; + } +} + +static int ltc4283_hwmon_energy_enable_set(struct ltc4283_hwmon *st, long = val) +{ + int ret; + + guard(mutex)(&st->lock); + + /* Setting the bit halts the meter. */ + val =3D !!val; + ret =3D regmap_update_bits(st->map, LTC4283_METER_CONTROL, + LTC4283_METER_HALT_MASK, + FIELD_PREP(LTC4283_METER_HALT_MASK, !val)); + if (ret) + return ret; + + st->energy_en =3D val; + + return 0; +} + +static int ltc4283_hwmon_write(struct device *dev, enum hwmon_sensor_types= type, + u32 attr, int channel, long val) +{ + struct ltc4283_hwmon *st =3D dev_get_drvdata(dev); + + switch (type) { + case hwmon_power: + return ltc4283_hwmon_write_power(st, attr, val); + case hwmon_in: + return ltc4283_hwmon_write_in(st, attr, val, channel); + case hwmon_curr: + return ltc4283_hwmon_write_curr(st, attr, val); + case hwmon_energy: + return ltc4283_hwmon_energy_enable_set(st, val); + default: + return -EOPNOTSUPP; + } +} + +static umode_t ltc4283_hwmon_in_is_visible(const struct ltc4283_hwmon *st, + u32 attr, int channel) +{ + /* If ADIO is set as a GPIO, don=C2=B4t make it visible. */ + if (channel >=3D LTC4283_HWMON_ADIO_1 && channel <=3D LTC4283_HWMON_ADIO_= 4) { + /* ADIOX pins come at index 0 in the gpio mask. */ + channel -=3D LTC4283_HWMON_ADIO_1; + if (st->gpio_mask && test_bit(channel, st->gpio_mask)) + return 0; + } + + /* Also take care of differential channels. */ + if (channel >=3D LTC4283_HWMON_ADIO12 && channel <=3D LTC4283_HWMON_ADIO3= 4) { + channel -=3D LTC4283_HWMON_ADIO12; + /* If one channel in the pair is used, make it invisible. */ + if (st->gpio_mask && (test_bit(channel * 2, st->gpio_mask) || + test_bit(channel * 2 + 1, st->gpio_mask))) + return 0; + } + + switch (attr) { + case hwmon_in_input: + case hwmon_in_highest: + case hwmon_in_lowest: + case hwmon_in_max_alarm: + case hwmon_in_min_alarm: + case hwmon_in_label: + case hwmon_in_lcrit_alarm: + case hwmon_in_crit_alarm: + case hwmon_in_fault: + return 0444; + case hwmon_in_max: + case hwmon_in_min: + case hwmon_in_enable: + case hwmon_in_reset_history: + return 0644; + default: + return 0; + } +} + +static umode_t ltc4283_hwmon_curr_is_visible(u32 attr) +{ + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_highest: + case hwmon_curr_lowest: + case hwmon_curr_max_alarm: + case hwmon_curr_min_alarm: + case hwmon_curr_crit_alarm: + case hwmon_curr_label: + return 0444; + case hwmon_curr_max: + case hwmon_curr_min: + case hwmon_curr_reset_history: + return 0644; + default: + return 0; + } +} + +static umode_t ltc4283_hwmon_power_is_visible(u32 attr) +{ + switch (attr) { + case hwmon_power_input: + case hwmon_power_input_highest: + case hwmon_power_input_lowest: + case hwmon_power_label: + case hwmon_power_max_alarm: + case hwmon_power_min_alarm: + return 0444; + case hwmon_power_max: + case hwmon_power_min: + case hwmon_power_reset_history: + return 0644; + default: + return 0; + } +} + +static umode_t ltc4283_hwmon_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_in: + return ltc4283_hwmon_in_is_visible(data, attr, channel); + case hwmon_curr: + return ltc4283_hwmon_curr_is_visible(attr); + case hwmon_power: + return ltc4283_hwmon_power_is_visible(attr); + case hwmon_energy: + /* hwmon_energy_enable */ + return 0644; + default: + return 0; + } +} + +static const char * const ltc4283_hwmon_in_strs[] =3D { + "VIN", "VPWR", "VADI1", "VADI2", "VADI3", "VADI4", "VADIO1", "VADIO2", + "VADIO3", "VADIO4", "DRNS", "DRAIN", "ADIN2-ADIN1", "ADIN4-ADIN3", + "ADIO2-ADIO1", "ADIO4-ADIO3" +}; + +static int ltc4283_hwmon_read_labels(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + switch (type) { + case hwmon_in: + *str =3D ltc4283_hwmon_in_strs[channel]; + return 0; + case hwmon_curr: + *str =3D "ISENSE"; + return 0; + case hwmon_power: + *str =3D "Power"; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static ssize_t ltc4283_hwmon_energy_show(struct device *dev, + struct device_attribute *da, char *buf) +{ + u64 temp =3D LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV, energy, temp_2; + struct ltc4283_hwmon *st =3D dev_get_drvdata(dev); + __be64 raw; + int ret; + + guard(mutex)(&st->lock); + if (!st->energy_en) + return -ENODATA; + + ret =3D regmap_bulk_read(st->map, LTC4283_ENERGY, &raw, sizeof(raw)); + if (ret) + return ret; + + energy =3D be64_to_cpu(raw) >> 16; + + /* + * The formula for energy is given by: + * E =3D CODE(48b) * 32.768mV * 2.048V * Tconv / 2^24 * Rsense + * + * As Rsense can have tenths of micro-ohm resolution, we need to + * multiply by DECA to get microjoule. + */ + if (check_mul_overflow(temp * LTC4283_TCONV_uS, energy, &temp_2)) { + /* + * We multiply again by 1000 to make sure that we don't get 0 + * in the following division which could happen for big rsense + * values. OTOH, we then divide energy first by 1000 so that + * we do not overflow u64 again for very small rsense values. + * We add 100 factor for proper conversion to microjoule. + */ + temp_2 =3D DIV64_U64_ROUND_CLOSEST(temp * LTC4283_TCONV_uS * MILLI, + BIT_ULL(24) * st->rsense); + energy =3D DIV_ROUND_CLOSEST_ULL(energy, MILLI * CENTI) * temp_2; + } else { + /* Put rsense back into nanoohm so we get microjoule. */ + energy =3D DIV64_U64_ROUND_CLOSEST(temp_2, BIT_ULL(24) * st->rsense * CE= NTI); + } + + return sysfs_emit(buf, "%llu\n", energy); +} + +/* + * Set max limits for ISENSE and Power as that depends on the max voltage = on + * rsense that is defined in ILIM_ADJUST. This is specially important for = power + * because for some rsense and vfsout values, if we allow the default raw = 255 + * value, that would overflow long in 32bit archs when reading back the max + * power limit. + */ +static int ltc4283_hwmon_set_max_limits(struct ltc4283_hwmon *st, struct d= evice *dev) +{ + u32 temp =3D st->vsense_max * DECA * MICRO; + int ret; + + ret =3D ltc4283_hwmon_write_in_byte(st, LTC4283_SENSE_MAX_TH, + LTC4283_ADC1_FS_uV, + st->vsense_max * MILLI); + if (ret) + return ret; + + /* Power is given by ISENSE * Vout. */ + st->power_max =3D DIV_ROUND_CLOSEST(temp, st->rsense) * LTC4283_ADC2_FS_m= V; + return ltc4282_write_power_byte(st, LTC4283_POWER_MAX_TH, st->power_max); +} + +static int ltc4283_hwmon_set_array_prop(const struct ltc4283_hwmon *st, + struct device *dev, const char *prop, + const u32 *vals, u32 n_vals, u32 reg, + u32 mask) +{ + u32 prop_val; + int ret; + u32 i; + + ret =3D device_property_read_u32(dev, prop, &prop_val); + if (ret) + return 0; + + for (i =3D 0; i < n_vals; i++) { + if (prop_val !=3D vals[i]) + continue; + + return regmap_update_bits(st->map, reg, mask, + field_prep(mask, i)); + } + + return dev_err_probe(dev, -EINVAL, + "Invalid %s property value %u, expected one of: %*ph\n", + prop, prop_val, n_vals, vals); +} + +static int ltc4283_hwmon_get_defaults(struct ltc4283_hwmon *st) +{ + u32 reg_val, ilm_adjust, c; + int ret; + + ret =3D regmap_read(st->map, LTC4283_METER_CONTROL, ®_val); + if (ret) + return ret; + + st->energy_en =3D !FIELD_GET(LTC4283_METER_HALT_MASK, reg_val); + + ret =3D regmap_read(st->map, LTC4283_CONFIG_1, ®_val); + if (ret) + return ret; + + ilm_adjust =3D FIELD_GET(LTC4283_ILIM_MASK, reg_val); + st->vsense_max =3D LTC4283_VILIM_MIN_uV / MILLI + ilm_adjust; + + /* VPWR and VIN are always enabled */ + __set_bit(LTC4283_HWMON_VIN, &st->ch_enable_mask); + __set_bit(LTC4283_HWMON_VPWR, &st->ch_enable_mask); + for (c =3D LTC4283_HWMON_ADI_1; c < LTC4283_HWMON_CHAN_MAX; c++) { + u32 chan =3D c - LTC4283_HWMON_ADI_1, bit; + + ret =3D regmap_read(st->map, LTC4283_ADC_SELECT(chan), ®_val); + if (ret) + return ret; + + bit =3D LTC4283_ADC_SELECT_MASK(chan); + if (c > LTC4283_HWMON_DRAIN) + /* account for two reserved fields after DRAIN */ + bit <<=3D 2; + + if (!(bit & reg_val)) + continue; + + __set_bit(c, &st->ch_enable_mask); + } + + return 0; +} + +static const char * const ltc4283_pgio1_funcs[] =3D { + "inverted_power_good", "power_good" +}; + +static const char * const ltc4283_pgio2_funcs[] =3D { + "inverted_power_good", "power_good", "active_current_limiting" +}; + +static const char * const ltc4283_pgio3_funcs[] =3D { + "inverted_power_good_input", "power_good_input" +}; + +static const char * const ltc4283_pgio4_funcs[] =3D { + "inverted_external_fault", "external_fault" +}; + +enum { + LTC4283_PGIO1, + LTC4283_PGIO2, + LTC4283_PGIO3, + LTC4283_PGIO4, +}; + +struct ltc4283_pgpio { + const char *prop; + const char * const *funcs; + u32 n_funcs; +}; + +static const struct ltc4283_pgpio ltc4283_pgio_props[] =3D { + [LTC4283_PGIO1] =3D { + .prop =3D "adi,pgio1-func", + .funcs =3D ltc4283_pgio1_funcs, + .n_funcs =3D ARRAY_SIZE(ltc4283_pgio1_funcs) + }, + [LTC4283_PGIO2] =3D { + .prop =3D "adi,pgio2-func", + .funcs =3D ltc4283_pgio2_funcs, + .n_funcs =3D ARRAY_SIZE(ltc4283_pgio2_funcs) + }, + [LTC4283_PGIO3] =3D { + .prop =3D "adi,pgio3-func", + .funcs =3D ltc4283_pgio3_funcs, + .n_funcs =3D ARRAY_SIZE(ltc4283_pgio3_funcs) + }, + [LTC4283_PGIO4] =3D { + .prop =3D "adi,pgio4-func", + .funcs =3D ltc4283_pgio4_funcs, + .n_funcs =3D ARRAY_SIZE(ltc4283_pgio4_funcs) + }, +}; + +static int ltc4283_pgio_config(struct ltc4283_hwmon *st, struct device *de= v) +{ + int ret, func; + u32 pgio; + + for (pgio =3D 0; pgio < ARRAY_SIZE(ltc4283_pgio_props); pgio++) { + func =3D device_property_match_property_string(dev, ltc4283_pgio_props[p= gio].prop, + ltc4283_pgio_props[pgio].funcs, + ltc4283_pgio_props[pgio].n_funcs); + if (func < 0) { + if (func !=3D -ENOENT) + continue; + return dev_err_probe(dev, func, + "%s invalid value\n", + ltc4283_pgio_props[pgio].prop); + } + + if (st->gpio_mask && test_bit(pgio, st->gpio_mask)) + return dev_err_probe(dev, -EINVAL, + "PGIO%u already configured as GPIO\n", + pgio + 1); + + /* pgio2 as active current limiting */ + if (pgio =3D=3D LTC4283_PGIO2 && func =3D=3D 2) { + ret =3D regmap_set_bits(st->map, LTC4283_CONTROL_1, + LTC4283_PIGIO2_ACLB_MASK); + if (ret) + return ret; + + continue; + } + + ret =3D regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, + LTC4283_PGIO_CFG_MASK(pgio), + field_prep(LTC4283_PGIO_CFG_MASK(pgio), func)); + if (ret) + return ret; + + if (pgio =3D=3D LTC4283_PGIO4) + st->ext_fault =3D true; + } + + return 0; +} + +static const char * const ltc4283_oc_fet_retry[] =3D { + "latch-off", "1", "7", "unlimited" +}; + +static const u32 ltc4283_fb_factor[] =3D { + 100, 50, 20, 10 +}; + +static const u32 ltc4283_cooling_dl[] =3D { + 512, 1002, 2005, 4100, 8190, 16400, 32800, 65600 +}; + +static const u32 ltc4283_fet_bad_delay[] =3D { + 256, 512, 1002, 2005 +}; + +static int ltc4283_hwmon_setup(struct ltc4283_hwmon *st, struct device *de= v) +{ + u32 adio; + int ret; + + /* The part has an eeprom so let's get the needed defaults from it */ + ret =3D ltc4283_hwmon_get_defaults(st); + if (ret) + return ret; + + ret =3D device_property_read_u32(dev, "adi,rsense-nano-ohms", + &st->rsense); + if (ret) + return dev_err_probe(dev, ret, + "Failed to read adi,rsense-nano-ohms\n"); + if (st->rsense < CENTI) + return dev_err_probe(dev, -EINVAL, + "adi,rsense-nano-ohms too small (< %lu)\n", + CENTI); + + /* + * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which + * means we need nano in the bindings. However, to make things easier to + * handle (with respect to overflows) we divide it by 100 as we don't + * really need the last two digits. + */ + st->rsense /=3D CENTI; + + ret =3D device_property_read_u32(dev, "adi,current-limit-sense-microvolt", + &st->vsense_max); + if (!ret) { + u32 reg_val; + + if (!in_range(st->vsense_max, LTC4283_VILIM_MIN_uV, + LTC4283_VILIM_RANGE)) { + return dev_err_probe(dev, -EINVAL, + "adi,current-limit-sense-microvolt (%u) out of range [%u %u]\n", + st->vsense_max, LTC4283_VILIM_MIN_uV, + LTC4283_VILIM_MAX_uV); + } + + st->vsense_max /=3D MILLI; + reg_val =3D FIELD_PREP(LTC4283_ILIM_MASK, + st->vsense_max - LTC4283_VILIM_MIN_uV / MILLI); + ret =3D regmap_update_bits(st->map, LTC4283_CONFIG_1, + LTC4283_ILIM_MASK, reg_val); + if (ret) + return ret; + } + + ret =3D ltc4283_hwmon_set_array_prop(st, dev, "adi,current-limit-foldback= -factor", + ltc4283_fb_factor, ARRAY_SIZE(ltc4283_fb_factor), + LTC4283_CONFIG_1, LTC4283_FB_MASK); + if (ret) + return ret; + + ret =3D ltc4283_hwmon_set_array_prop(st, dev, "adi,cooling-delay-ms", + ltc4283_cooling_dl, ARRAY_SIZE(ltc4283_cooling_dl), + LTC4283_CONFIG_2, LTC4283_COOLING_DL_MASK); + if (ret) + return ret; + + ret =3D ltc4283_hwmon_set_array_prop(st, dev, "adi,fet-bad-timer-delay-ms= ", + ltc4283_fet_bad_delay, ARRAY_SIZE(ltc4283_fet_bad_delay), + LTC4283_CONFIG_2, LTC4283_FTBD_DL_MASK); + if (ret) + return ret; + + ret =3D ltc4283_hwmon_set_max_limits(st, dev); + if (ret) + return ret; + + ret =3D ltc4283_pgio_config(st, dev); + if (ret) + return ret; + + if (device_property_read_bool(dev, "adi,power-good-reset-on-fet")) { + ret =3D regmap_clear_bits(st->map, LTC4283_CONTROL_1, + LTC4283_PWRGD_RST_CTRL_MASK); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,fet-turn-off-disable")) { + ret =3D regmap_clear_bits(st->map, LTC4283_CONTROL_1, + LTC4283_FET_BAD_OFF_MASK); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,tmr-pull-down-disable")) { + ret =3D regmap_set_bits(st->map, LTC4283_CONTROL_1, + LTC4283_THERM_TMR_MASK); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,dvdt-inrush-control-disable")) { + ret =3D regmap_clear_bits(st->map, LTC4283_CONTROL_1, + LTC4283_DVDT_MASK); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) { + ret =3D regmap_clear_bits(st->map, LTC4283_CONTROL_2, + LTC4283_UV_RETRY_MASK); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) { + ret =3D regmap_clear_bits(st->map, LTC4283_CONTROL_2, + LTC4283_OV_RETRY_MASK); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,external-fault-retry-enable")) { + if (!st->ext_fault) + return dev_err_probe(dev, -EINVAL, + "adi,external-fault-retry-enable set but PGIO4 not configured\n"= ); + ret =3D regmap_set_bits(st->map, LTC4283_CONTROL_2, + LTC4283_EXT_FAULT_RETRY_MASK); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,fault-log-enable")) { + ret =3D regmap_set_bits(st->map, LTC4283_FAULT_LOG_CTRL, + LTC4283_FAULT_LOG_EN_MASK); + if (ret) + return ret; + } + + ret =3D device_property_match_property_string(dev, "adi,overcurrent-retri= es", + ltc4283_oc_fet_retry, + ARRAY_SIZE(ltc4283_oc_fet_retry)); + /* We still want to catch when an invalid string is given. */ + if (ret =3D=3D -ENOENT) + return dev_err_probe(dev, ret, + "adi,overcurrent-retries invalid value\n"); + if (ret >=3D 0) { + ret =3D regmap_update_bits(st->map, LTC4283_CONTROL_2, + LTC4283_OC_RETRY_MASK, + FIELD_PREP(LTC4283_OC_RETRY_MASK, ret)); + if (ret) + return ret; + } + + ret =3D device_property_match_property_string(dev, "adi,fet-bad-retries", + ltc4283_oc_fet_retry, + ARRAY_SIZE(ltc4283_oc_fet_retry)); + if (ret =3D=3D -ENOENT) + return dev_err_probe(dev, ret, + "adi,fet-bad-retries invalid value\n"); + if (ret >=3D 0) { + ret =3D regmap_update_bits(st->map, LTC4283_CONTROL_2, + LTC4283_FET_BAD_RETRY_MASK, + FIELD_PREP(LTC4283_FET_BAD_RETRY_MASK, ret)); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,external-fault-fet-off-enable")) { + if (!st->ext_fault) + return dev_err_probe(dev, -EINVAL, + "adi,external-fault-fet-off-enable set but PGIO4 not configured\= n"); + ret =3D regmap_set_bits(st->map, LTC4283_CONFIG_3, + LTC4283_EXTFLT_TURN_OFF_MASK); + if (ret) + return ret; + } + + if (device_property_read_bool(dev, "adi,vpower-drns-enable")) { + u32 drns_chan =3D LTC4283_HWMON_DRNS - LTC4283_HWMON_ADI_1; + + ret =3D regmap_set_bits(st->map, LTC4283_CONFIG_3, + LTC4283_VPWR_DRNS_MASK); + if (ret) + return ret; + + /* + * Then, let's by default disable the DRNS channel from the ADC2 + * as this is already being monitored by the VPWR channel. One + * can still enable it later on if needed. + */ + ret =3D regmap_clear_bits(st->map, LTC4283_ADC_SELECT(drns_chan), + LTC4283_ADC_SELECT_MASK(drns_chan)); + if (ret) + return ret; + + __clear_bit(LTC4283_HWMON_DRNS, &st->ch_enable_mask); + } + + /* Make sure the ADC has 12bit resolution since we're assuming that. */ + ret =3D regmap_update_bits(st->map, LTC4283_PGIO_CONFIG_2, + LTC4283_ADC_MASK, + FIELD_PREP(LTC4283_ADC_MASK, 3)); + if (ret) + return ret; + + /* + * Make sure we are integrating power as we only support reporting + * consumed energy. + */ + ret =3D regmap_clear_bits(st->map, LTC4283_METER_CONTROL, + LTC4283_INTEGRATE_I_MASK); + if (ret) + return ret; + + if (!st->gpio_mask) + return 0; + + /* Then, let's remove any ADIO set as GPIO from the ADC measurements. */ + for_each_set_bit(adio, st->gpio_mask, LTC4283_PGIOX_START_NR) { + u32 adc_idx =3D adio + (LTC4283_HWMON_ADIO_1 - LTC4283_HWMON_ADI_1); + + ret =3D regmap_clear_bits(st->map, LTC4283_ADC_SELECT(adc_idx), + LTC4283_ADC_SELECT_MASK(adc_idx)); + if (ret) + return ret; + } + + return 0; +} + +static const struct hwmon_channel_info * const ltc4283_hwmon_info[] =3D { + HWMON_CHANNEL_INFO(in, + HWMON_I_LCRIT_ALARM | HWMON_I_CRIT_ALARM | + HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_MAX_ALARM | HWMON_I_RESET_HISTORY | + HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_FAULT | HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | + HWMON_I_ENABLE | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(curr, + HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | + HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM | + HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM | + HWMON_C_RESET_HISTORY | HWMON_C_LABEL), + HWMON_CHANNEL_INFO(power, + HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | + HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | + HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM | + HWMON_P_RESET_HISTORY | HWMON_P_LABEL), + HWMON_CHANNEL_INFO(energy, + HWMON_E_ENABLE | HWMON_E_LABEL), + NULL +}; + +static const struct hwmon_ops ltc4283_hwmon_ops =3D { + .read =3D ltc4283_hwmon_read, + .write =3D ltc4283_hwmon_write, + .is_visible =3D ltc4283_hwmon_is_visible, + .read_string =3D ltc4283_hwmon_read_labels, +}; + +static const struct hwmon_chip_info ltc4283_hwmon_chip_info =3D { + .ops =3D <c4283_hwmon_ops, + .info =3D ltc4283_hwmon_info, +}; + +/* energy attributes are 6bytes wide so we need u64 */ +static SENSOR_DEVICE_ATTR_RO(energy1_input, ltc4283_hwmon_energy, 0); + +static struct attribute *ltc4283_hwmon_attrs[] =3D { + &sensor_dev_attr_energy1_input.dev_attr.attr, + NULL +}; +ATTRIBUTE_GROUPS(ltc4283_hwmon); + +static void ltc4282_debugfs_remove(void *dir) +{ + debugfs_remove_recursive(dir); +} + +static int ltc4283_hwmon_show_fault_log(void *arg, u64 *val, u32 mask) +{ + struct ltc4283_hwmon *st =3D arg; + long alarm; + int ret; + + ret =3D ltc4283_hwmon_read_alarm(st, LTC4283_FAULT_LOG, mask, &alarm); + if (ret) + return ret; + + *val =3D alarm; + + return 0; +} + +static int ltc4283_hwmon_show_in0_lcrit_fault_log(void *arg, u64 *val) +{ + return ltc4283_hwmon_show_fault_log(arg, val, LTC4283_UV_FAULT_MASK); +} +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_lcrit_fault_log, + ltc4283_hwmon_show_in0_lcrit_fault_log, NULL, "%llu\n"); + +static int ltc4283_hwmon_show_in0_crit_fault_log(void *arg, u64 *val) +{ + return ltc4283_hwmon_show_fault_log(arg, val, LTC4283_OV_FAULT_MASK); +} +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_crit_fault_log, + ltc4283_hwmon_show_in0_crit_fault_log, NULL, "%llu\n"); + +static int ltc4283_hwmon_show_fet_bad_fault_log(void *arg, u64 *val) +{ + return ltc4283_hwmon_show_fault_log(arg, val, LTC4283_FET_BAD_FAULT_MASK); +} +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_bad_fault_log, + ltc4283_hwmon_show_fet_bad_fault_log, NULL, "%llu\n"); + +static int ltc4283_hwmon_show_fet_short_fault_log(void *arg, u64 *val) +{ + return ltc4283_hwmon_show_fault_log(arg, val, LTC4283_FET_SHORT_FAULT_MAS= K); +} +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_short_fault_log, + ltc4283_hwmon_show_fet_short_fault_log, NULL, "%llu\n"); + +static int ltc4283_hwmon_show_curr1_crit_fault_log(void *arg, u64 *val) +{ + return ltc4283_hwmon_show_fault_log(arg, val, LTC4283_OC_FAULT_MASK); +} +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_curr1_crit_fault_log, + ltc4283_hwmon_show_curr1_crit_fault_log, NULL, "%llu\n"); + +static int ltc4283_hwmon_show_power1_failed_fault_log(void *arg, u64 *val) +{ + return ltc4283_hwmon_show_fault_log(arg, val, LTC4283_PWR_FAIL_FAULT_MASK= ); +} +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_failed_fault_log, + ltc4283_hwmon_show_power1_failed_fault_log, NULL, "%llu\n"); + +static int ltc4283_hwmon_show_power1_good_input_fault_log(void *arg, u64 *= val) +{ + return ltc4283_hwmon_show_fault_log(arg, val, LTC4283_PGI_FAULT_MASK); +} +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_good_input_fault_log, + ltc4283_hwmon_show_power1_good_input_fault_log, NULL, "%llu\n"); + +static void ltc4283_debugfs_init(struct ltc4283_hwmon *st, struct device *= dev, + const struct device *hwmon) +{ + const char *debugfs_name; + struct dentry *dentry; + int ret; + + if (!IS_ENABLED(CONFIG_DEBUG_FS)) + return; + + debugfs_name =3D devm_kasprintf(dev, GFP_KERNEL, "ltc4283-%s", + dev_name(hwmon)); + if (!debugfs_name) + return; + + dentry =3D debugfs_create_dir(debugfs_name, NULL); + if (IS_ERR(dentry)) + return; + + ret =3D devm_add_action_or_reset(dev, ltc4282_debugfs_remove, dentry); + if (ret) + return; + + debugfs_create_file_unsafe("in0_crit_fault_log", 0400, dentry, st, + <c4283_in0_crit_fault_log); + debugfs_create_file_unsafe("in0_lcrit_fault_log", 0400, dentry, st, + <c4283_in0_lcrit_fault_log); + debugfs_create_file_unsafe("in0_fet_bad_fault_log", 0400, dentry, st, + <c4283_fet_bad_fault_log); + debugfs_create_file_unsafe("in0_fet_short_fault_log", 0400, dentry, st, + <c4283_fet_short_fault_log); + debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, dentry, st, + <c4283_curr1_crit_fault_log); + debugfs_create_file_unsafe("power1_failed_fault_log", 0400, dentry, st, + <c4283_power1_failed_fault_log); + debugfs_create_file_unsafe("power1_good_input_fault_log", 0400, dentry, + st, <c4283_power1_good_input_fault_log); +} + +static int ltc4283_hwmon_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev, *hwmon; + struct ltc4283_hwmon *st; + int ret; + + st =3D devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); + if (!st) + return -ENOMEM; + + st->gpio_mask =3D dev_get_drvdata(dev->parent); + st->map =3D dev_get_regmap(dev->parent, NULL); + if (!st->map) + return dev_err_probe(dev, -ENODEV, + "Failed to get parent regmap\n"); + + ret =3D ltc4283_hwmon_setup(st, dev); + if (ret) + return ret; + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + hwmon =3D devm_hwmon_device_register_with_info(dev, "ltc4283_hwmon", st, + <c4283_hwmon_chip_info, + ltc4283_hwmon_groups); + + if (IS_ERR(hwmon)) + return PTR_ERR(hwmon); + + ltc4283_debugfs_init(st, dev, hwmon); + + return 0; +} + +static const struct of_device_id ltc4283_of_match[] =3D { + { .compatible =3D "adi,ltc4283-hwmon" }, + { } +}; + +static struct platform_driver ltc4283_hwmon_driver =3D { + .driver =3D { + .name =3D "ltc4283-hwmon", + .of_match_table =3D ltc4283_of_match, + }, + .probe =3D ltc4283_hwmon_probe, +}; +module_platform_driver(ltc4283_hwmon_driver); + +MODULE_AUTHOR("Nuno S=C3=A1 "); +MODULE_DESCRIPTION("HWMON LTC4283 How Swap Controller driver"); +MODULE_LICENSE("GPL"); --=20 2.50.1 From nobody Sat Oct 4 15:59:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 323652FC898; Thu, 14 Aug 2025 10:52:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; cv=none; b=nR3nI0y9+DebqAaMDcUo95EKUbwqlvlPnBpq3aRzB45RvaQS3wqhjE9Q+J+ib+0oyL12zGlvMYnls3Ipjg+e9VaEsyXThp3kNz5KSxth8wdRGefWAO70mh1eEjvl2VEZ/0CrfRhEKxwPgZ7zrx2lO4X/KaFVWTTJOOfNRJUcVgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; c=relaxed/simple; bh=SkZlS7jX9raYlHR3Ve0oCZpRMKEZX0aeoX+eevk1TFc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j/eBDMjd11AqseYa9nh3hqkLh/9/jryjMsAin6f+S1N3MT5DbymjuvjL8DsngrVSZMoOk+U2sRcVaJJ+uW735MM3qOsT+EYHeQNQzzsJdwn0LFW5KOD+ZNBUSwayxI/xSdny+c8nPhdNCeln76GPXSItMLVgLbIVMyLGSqmacOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cKrbPVNC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cKrbPVNC" Received: by smtp.kernel.org (Postfix) with ESMTPS id D97F8C4AF11; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755168733; bh=SkZlS7jX9raYlHR3Ve0oCZpRMKEZX0aeoX+eevk1TFc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cKrbPVNCE69MN9OMz6ZbeezUPcpxqLCeo7QDrAuH3nA1o/72G+E/vJK9oQlINYpaY OzEHAGEp5FLKId2QK0ZB6uVu9hu+2PoSace/QXe9MPYh7CWn8OlBhjZVrEyJnZIl6c AWsn7zUSUg6ROUW0UQ+jm5/YHQxkPqUVPvJeKPWSR3QQei5YV2RyQyUxrfXtoN6CJP OxpqT0YBFh8x6/4NluM03eZjGCrla4uvRoPfjyV8wjIpAgAud97BIzu47UKytll5Ye ync02qws15M8hy1p0KaVsyMUGPfseXurulY1+oWzSmJaLVIyRv8aUInxQFZCuVq3Db KDhUTYlS3cIlA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1C58CA0EE8; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Thu, 14 Aug 2025 11:52:27 +0100 Subject: [PATCH 5/6] dt-binbings: gpio: Add bindings for the LTC4283 Swap Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-ltc4283-support-v1-5-88b2cef773f2@analog.com> References: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> In-Reply-To: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> To: linux-hwmon@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jean Delvare , Guenter Roeck , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755168753; l=1989; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=Mi+0w4C770q9JTWbgxwKL384Ye5xiUh9QjGwMTrZ6Xs=; b=QLTCDnUrhQy1nxd3vzBpXvjXbpC1vLZCvqc0K7r7lTNC42scTylXuXsFZvLH4YtgHM4jB1kh7 t68Q1yWWCI1Apgec7jBBIpTgcV+bsyyGRNhhiAsbx5ajVbTTDqopUTX X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno S=C3=A1 Document the bindings for the GPIO controller functions of the LTC4283 Hot Swap Controller. Signed-off-by: Nuno S=C3=A1 --- .../devicetree/bindings/gpio/adi,ltc4283.yaml | 33 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/adi,ltc4283.yaml b/Docu= mentation/devicetree/bindings/gpio/adi,ltc4283.yaml new file mode 100644 index 0000000000000000000000000000000000000000..39ca59c53519ea3a761c75c394c= 56de885d63fea --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/adi,ltc4283.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/adi,ltc4283.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO LTC4283 Negative Voltage Hot Swap Controller + +maintainers: + - Nuno S=C3=A1 + +description: | + This module is part of the LTC4283 MFD device. + See Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml + This implements the GPIO bindings for the LTC4283 negative voltage hot s= wap + controller. + +properties: + compatible: + enum: + - adi,ltc4283-gpio + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - gpio-controller + - '#gpio-cells' + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index d5d3018b5424f403e7396f0470a12ce8c94a5e49..e492e75833564bd9065fe2422e8= 6479553ea59dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14505,6 +14505,7 @@ M: Nuno S=C3=A1 L: linux-hwmon@vger.kernel.org L: linux-gpio@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/gpio/adi,ltc4283.yaml F: Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml F: Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml F: drivers/hwmon/ltc4283-hwmon.c --=20 2.50.1 From nobody Sat Oct 4 15:59:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E4282FD7CE; Thu, 14 Aug 2025 10:52:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; cv=none; b=Ogg5BZvdVxilQ3whOtcuCTbZPjX6MmmNJF4Ln/qI4ZOYWBRXAyKjHsJaciMGq/qVLgHKFeQdt/5NpHMciJYNE0T14RYqe0VF/2PV8TUir84MnJh5mGZtbm53kVluZzfy9bxtAMkH6wYNk4XWfzFbaA64sXWWPt+ckkUuwPS5ZJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755168734; c=relaxed/simple; bh=VjTUeKO5DzaMDYjeEYA5iF9+wACGlLhG3F60oh75hSc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NYUe2u+/WaFi7Z75pRLkoLNYWloswjojJahCtvy42IaKwHn75ltFKyw89ZHjcyrYTxUioC8tzZYWsoR5fO+n3EP704xnhklKdggFlyoCmJQ1bqWWJQz13izrxTH6BZvB9SfQhoYnVKmEIe6JgmqhgsyKxPFL7ARFkZ2Su9lBZTI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KNC14W8A; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KNC14W8A" Received: by smtp.kernel.org (Postfix) with ESMTPS id E7AFEC116C6; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755168734; bh=VjTUeKO5DzaMDYjeEYA5iF9+wACGlLhG3F60oh75hSc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KNC14W8A5+6rwWWaCK9IhSljuFwveZUwinNedHP00BVcepgDPA4wXkp25ondA5jva SV53cOvY+B/7vguHcR2O8c7Jau9CvTUI/zp0avRrZVZYT2e5S8KMzdKHYZA/zaSFoA v1RRNaOLF3yn5TZIERTNURzaM8iEGzleR46TF9iq6Lmr/yC82vXMIs5gcOgqrwyCdz lHweWuY+FXUr3sTdHefKaWbq11ynPfpWPm2hjIQDHhoI23xVLLGLTrqdPHulo6Br47 WYDj6w8UAY6cMk+APct9yHVJr+Hv/2zC5jhzpwh+2xWgMhLsrBoJcBhBHZOzyYMHMl vnGZZ/bgbk6xg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEBCECA0EDC; Thu, 14 Aug 2025 10:52:13 +0000 (UTC) From: =?utf-8?q?Nuno_S=C3=A1_via_B4_Relay?= Date: Thu, 14 Aug 2025 11:52:28 +0100 Subject: [PATCH 6/6] gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-ltc4283-support-v1-6-88b2cef773f2@analog.com> References: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> In-Reply-To: <20250814-ltc4283-support-v1-0-88b2cef773f2@analog.com> To: linux-hwmon@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jean Delvare , Guenter Roeck , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755168753; l=9063; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=086cCq1l2Tj2mWktUEYQQ1Yx2N11Tx954i757Fp6GS8=; b=Df5+LPzwO2GllKw5IVHwHmIpshDRP7srrKtkaqLHYV1ft7YNDZPrlSvKEbke84e1zjoZSC5b0 6t0oRmMZgtUCrFQnOxeoKq6LZdpMz+gqwyUXt0HM1dMTCJAI/vWAGZa X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-Endpoint-Received: by B4 Relay for nuno.sa@analog.com/20231116 with auth_id=100 X-Original-From: =?utf-8?q?Nuno_S=C3=A1?= Reply-To: nuno.sa@analog.com From: Nuno S=C3=A1 The LTC4283 device has up to 8 pins that can be configured as GPIOs. Note that PGIO pins are not set as GPIOs by default so if they are configured to be used as GPIOs we need to make sure to initialize them to a sane default. They are set as inputs by default. Signed-off-by: Nuno S=C3=A1 --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-ltc4283.c | 233 ++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 245 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e492e75833564bd9065fe2422e86479553ea59dd..ae45c190920930ebe8890610bd7= f92bd628ad025 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14508,6 +14508,7 @@ S: Supported F: Documentation/devicetree/bindings/gpio/adi,ltc4283.yaml F: Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml F: Documentation/devicetree/bindings/mfd/adi,ltc4283.yaml +F: drivers/gpio/gpio-ltc4283.c F: drivers/hwmon/ltc4283-hwmon.c F: drivers/mfd/ltc4283.c F: include/linux/mfd/ltc4283.h diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e43abb322fa6e15f19f2f498aa5adea03e6cd3bf..fe1cd8c1a2f7f012ece0f207552= fd1f15df26b1d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -461,6 +461,16 @@ config GPIO_LPC32XX Select this option to enable GPIO driver for NXP LPC32XX devices. =20 +config GPIO_LTC4283 + tristate "Analog Devices LTC4283 GPIO support" + depends on MFD_LTC4283 + help + If you say yes here you want the GPIO function available in Analog + Devices LTC4283 Negative Voltage Hot Swap Controller. + + This driver can also be built as a module. If so, the module will + be called gpio-ltc4283. + config GPIO_MB86S7X tristate "GPIO support for Fujitsu MB86S7x Platforms" help diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 379f55e9ed1e69cd9c5745f8643541b85953db1c..513f2b5c82ccff3a1da855d45ab= b5ad6abf5a14e 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -99,6 +99,7 @@ obj-$(CONFIG_GPIO_LP873X) +=3D gpio-lp873x.o obj-$(CONFIG_GPIO_LP87565) +=3D gpio-lp87565.o obj-$(CONFIG_GPIO_LPC18XX) +=3D gpio-lpc18xx.o obj-$(CONFIG_GPIO_LPC32XX) +=3D gpio-lpc32xx.o +obj-$(CONFIG_GPIO_LTC4283) +=3D gpio-ltc4283.o obj-$(CONFIG_GPIO_MACSMC) +=3D gpio-macsmc.o obj-$(CONFIG_GPIO_MADERA) +=3D gpio-madera.o obj-$(CONFIG_GPIO_MAX3191X) +=3D gpio-max3191x.o diff --git a/drivers/gpio/gpio-ltc4283.c b/drivers/gpio/gpio-ltc4283.c new file mode 100644 index 0000000000000000000000000000000000000000..c2c454c3b6e4ab0fe315dafc7eb= 66c45c3ceae67 --- /dev/null +++ b/drivers/gpio/gpio-ltc4283.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices LTC4283 GPIO driver + * + * Copyright 2025 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LTC4283_INPUT_STATUS 0x02 +#define LTC4283_PGIO_CONFIG_2 0x11 + +#define LTC42823_ADIO_CONFIG 0x12 +/* starts at bit 4 */ +#define LTC4283_ADIOX_CONFIG_MASK(pin) BIT((pin) + 4) +#define LTC4283_PGIO_DIR_IN 3 + +struct ltc4283_gpio { + struct gpio_chip gpio_chip; + struct regmap *regmap; +}; + +static int ltc4283_pgio_get_direction(const struct ltc4283_gpio *st, unsig= ned int off) +{ + unsigned int val; + int ret; + + ret =3D regmap_read(st->regmap, LTC4283_PGIO_CONFIG, &val); + if (ret) + return ret; + + val =3D field_get(LTC4283_PGIO_CFG_MASK(off), val); + if (val =3D=3D LTC4283_PGIO_DIR_IN) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; +} + +static int ltc4283_gpio_get_direction(struct gpio_chip *gc, unsigned int o= ff) +{ + struct ltc4283_gpio *st =3D gpiochip_get_data(gc); + unsigned int val; + int ret; + + if (off >=3D LTC4283_PGIOX_START_NR) + return ltc4283_pgio_get_direction(st, off); + + ret =3D regmap_read(st->regmap, LTC42823_ADIO_CONFIG, &val); + if (ret) + return ret; + + if (val & LTC4283_ADIOX_CONFIG_MASK(off)) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; +} + +static int ltc4283_gpio_direction_set(const struct ltc4283_gpio *st, + unsigned int off, bool input) +{ + if (off >=3D LTC4283_PGIOX_START_NR) { + unsigned int val; + + val =3D field_prep(LTC4283_PGIO_CFG_MASK(off), input ? 3 : 2); + return regmap_update_bits(st->regmap, LTC4283_PGIO_CONFIG, + LTC4283_PGIO_CFG_MASK(off), val); + } + + return regmap_update_bits(st->regmap, LTC42823_ADIO_CONFIG, + LTC4283_ADIOX_CONFIG_MASK(off), + field_prep(LTC4283_ADIOX_CONFIG_MASK(off), input)); +} + +static int __ltc4283_gpio_set_value(const struct ltc4283_gpio *st, + unsigned int off, int val) +{ + u32 reg =3D off < LTC4283_PGIOX_START_NR ? LTC42823_ADIO_CONFIG : LTC4283= _PGIO_CONFIG_2; + + return regmap_update_bits(st->regmap, reg, BIT(off), + field_prep(BIT(off), !!val)); +} + +static int ltc4283_gpio_direction_input(struct gpio_chip *gc, unsigned int= off) +{ + struct ltc4283_gpio *st =3D gpiochip_get_data(gc); + + return ltc4283_gpio_direction_set(st, off, true); +} + +static int ltc4283_gpio_direction_output(struct gpio_chip *gc, unsigned in= t off, int val) +{ + struct ltc4283_gpio *st =3D gpiochip_get_data(gc); + int ret; + + ret =3D ltc4283_gpio_direction_set(st, off, false); + if (ret) + return ret; + + return __ltc4283_gpio_set_value(st, off, val); +} + +static int ltc4283_gpio_get_value(struct gpio_chip *gc, unsigned int off) +{ + struct ltc4283_gpio *st =3D gpiochip_get_data(gc); + unsigned int val, reg; + int ret, dir; + + dir =3D ltc4283_gpio_get_direction(gc, off); + if (dir < 0) + return dir; + + if (dir =3D=3D GPIO_LINE_DIRECTION_IN) { + ret =3D regmap_read(st->regmap, LTC4283_INPUT_STATUS, &val); + if (ret) + return ret; + + /* ADIO1 is at bit 3. */ + if (off < LTC4283_PGIOX_START_NR) + return !!(val & BIT(3 - off)); + + /* PGIO1 is at bit 7. */ + return !!(val & BIT(7 - (off - LTC4283_PGIOX_START_NR))); + } + + if (off < LTC4283_PGIOX_START_NR) + reg =3D LTC42823_ADIO_CONFIG; + else + reg =3D LTC4283_PGIO_CONFIG_2; + + ret =3D regmap_read(st->regmap, reg, &val); + if (ret) + return ret; + + return !!(val & BIT(off)); +} + +static int ltc4283_gpio_set_value(struct gpio_chip *gc, unsigned int off, = int val) +{ + struct ltc4283_gpio *st =3D gpiochip_get_data(gc); + + return __ltc4283_gpio_set_value(st, off, val); +} + +static int ltc4283_init_valid_mask(struct gpio_chip *gc, unsigned long *va= lid_mask, + unsigned int ngpios) +{ + unsigned long *mask =3D dev_get_drvdata(gc->parent->parent); + + bitmap_copy(valid_mask, mask, ngpios); + return 0; +} + +static int ltc4283_gpio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + /* Get mask from top level device. */ + unsigned long *mask =3D dev_get_drvdata(dev->parent); + struct ltc4283_gpio *st; + struct gpio_chip *gc; + unsigned int gpio; + int ret; + + st =3D devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); + if (!st) + return -ENOMEM; + + st->regmap =3D dev_get_regmap(dev->parent, NULL); + + gc =3D &st->gpio_chip; + gc->parent =3D dev; + gc->get_direction =3D ltc4283_gpio_get_direction; + gc->direction_input =3D ltc4283_gpio_direction_input; + gc->direction_output =3D ltc4283_gpio_direction_output; + gc->get =3D ltc4283_gpio_get_value; + gc->set =3D ltc4283_gpio_set_value; + gc->init_valid_mask =3D ltc4283_init_valid_mask; + gc->can_sleep =3D true; + + gc->base =3D -1; + gc->ngpio =3D LTC4283_GPIO_MAX; + gc->label =3D pdev->name; + gc->owner =3D THIS_MODULE; + + for_each_set_bit(gpio, mask, LTC4283_GPIO_MAX) { + if (gpio < LTC4283_PGIOX_START_NR) + continue; + + /* + * PGIO pins can have some other state other than input + * or output, so we need to make sure to set one of those. + * Default to input. + */ + ret =3D ltc4283_gpio_direction_set(st, gpio, true); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set direction for PGIO %u\n", gpio); + } + + return devm_gpiochip_add_data(dev, &st->gpio_chip, st); +} + +static const struct platform_device_id ltc4283_gpio_id_table[] =3D { + { "ltc4283-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(platform, ltc4283_gpio_id_table); + +static const struct of_device_id ltc4283_of_id_table[] =3D { + { "adi,ltc4283-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, ltc4283_of_id_table); + +static struct platform_driver ltc4283_gpio_driver =3D { + .driver =3D { + .name =3D "ltc4283-gpio", + .of_match_table =3D ltc4283_of_id_table, + }, + .probe =3D ltc4283_gpio_probe, + .id_table =3D ltc4283_gpio_id_table, +}; +module_platform_driver(ltc4283_gpio_driver); + +MODULE_AUTHOR("Nuno S=C3=A1 "); +MODULE_DESCRIPTION("GPIO LTC4283 Driver"); +MODULE_LICENSE("GPL"); --=20 2.50.1