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Thu, 14 Aug 2025 07:54:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH0iMYMoTllj+CL+S1xwyfEUHobNivxyO19y8utqoiQgSr1bo/ruM3i+IYF0w6YaJZEqu+2TQ== X-Received: by 2002:a05:6a20:3a90:b0:240:cd6:a91e with SMTP id adf61e73a8af0-240bd03852dmr4067924637.20.1755183281966; Thu, 14 Aug 2025 07:54:41 -0700 (PDT) Received: from [169.254.0.3] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76be718b2d6sm30715274b3a.56.2025.08.14.07.54.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Aug 2025 07:54:41 -0700 (PDT) From: Raviteja Laggyshetty Date: Thu, 14 Aug 2025 14:54:21 +0000 Subject: [PATCH v2 3/3] interconnect: qcom: add glymur interconnect provider driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-glymur-icc-v2-3-596cca6b6015@oss.qualcomm.com> References: <20250814-glymur-icc-v2-0-596cca6b6015@oss.qualcomm.com> In-Reply-To: <20250814-glymur-icc-v2-0-596cca6b6015@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Raviteja Laggyshetty Cc: Mike Tipton , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Odelu Kukatla X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=X4lSKHTe c=1 sm=1 tr=0 ts=689df8b5 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=7Y5ZrCSegFD1MsWmRDAA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAzMSBTYWx0ZWRfX8eU3KAcbNRwu zfAHoQ43QVNIhGQsgvuh+QoNzR2eepwhmBC3eKfSMdrsHyUPh2D20wsa+LxQVDS9YZmFPbIIwEZ hKeKV1mR58o1bWeISsX94A2i3pD5ZBI7PUCdI0JTXd3o2p4TytRHX9XvTwlsoT2WiyYeaIZRFWi JEXf1GPFi3OZd+P7+GMD28PiShYUMWZwNGfl7JbBPH5QEoj4fq5o+BOMT8vijO5QyvxtuY/OB9+ BTvF/K3n9+K703H0jrKKD8/MXM0UY37a6MB9tG1iScRy5/3s+L7imSFi5Xv5sFEpja8wPJRSrAa 44xJdgy8JERrDjnxx+H6hiW17XhPyY1H0qI7LFUPNmPVKZvPsnjHMBiLGwZr2qioahPlyMlPzhA 8kp1Pq9z X-Proofpoint-GUID: 6ns4R2LH83ys8-4rAOqIfuqkr54XmeMu X-Proofpoint-ORIG-GUID: 6ns4R2LH83ys8-4rAOqIfuqkr54XmeMu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-13_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 adultscore=0 spamscore=0 bulkscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090031 Add driver for the Qualcomm interconnect buses found in glymur based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Reviewed-by: Dmitry Baryshkov --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/glymur.c | 2543 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 2554 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 31dc4781abefb50a8b6ca1d8a6efed369c47e1a6..5b4bb9f1382b2fd3c14b6f1ea35= c43ac9fddd803 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -8,6 +8,15 @@ config INTERCONNECT_QCOM config INTERCONNECT_QCOM_BCM_VOTER tristate =20 +config INTERCONNECT_QCOM_GLYMUR + tristate "Qualcomm GLYMUR interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on glymur-based + platforms. + config INTERCONNECT_QCOM_MSM8909 tristate "Qualcomm MSM8909 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index f16ac242eba5509a8649bb4670dd0848320e5be9..cf8cba73ee3e61839180d0c0a7c= 127dce848bdf2 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) +=3D interconnect_qcom.o =20 interconnect_qcom-y :=3D icc-common.o icc-bcm-voter-objs :=3D bcm-voter.o +qnoc-glymur-objs :=3D glymur.o qnoc-milos-objs :=3D milos.o qnoc-msm8909-objs :=3D msm8909.o qnoc-msm8916-objs :=3D msm8916.o @@ -46,6 +47,7 @@ qnoc-x1e80100-objs :=3D x1e80100.o icc-smd-rpm-objs :=3D smd-rpm.o icc-rpm.o icc-rpm-clocks.o =20 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) +=3D icc-bcm-voter.o +obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) +=3D qnoc-glymur.o obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) +=3D qnoc-milos.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) +=3D qnoc-msm8916.o diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom= /glymur.c new file mode 100644 index 0000000000000000000000000000000000000000..cf20b5752dbbf4a5e7a79926910= 993445d7cbb4f --- /dev/null +++ b/drivers/interconnect/qcom/glymur.c @@ -0,0 +1,2543 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup2_core_slave =3D { + .name =3D "qup2_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 =3D { + .name =3D "qhs_ahb2phy2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy3 =3D { + .name =3D "qhs_ahb2phy3", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_av1_enc_cfg =3D { + .name =3D "qhs_av1_enc_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie2_cfg =3D { + .name =3D "qhs_pcie2_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie3a_cfg =3D { + .name =3D "qhs_pcie3a_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie3b_cfg =3D { + .name =3D "qhs_pcie3b_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie4_cfg =3D { + .name =3D "qhs_pcie4_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie5_cfg =3D { + .name =3D "qhs_pcie5_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie6_cfg =3D { + .name =3D "qhs_pcie6_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_rscc =3D { + .name =3D "qhs_pcie_rscc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_smmuv3_cfg =3D { + .name =3D "qhs_smmuv3_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb2_0_cfg =3D { + .name =3D "qhs_usb2_0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0_cfg =3D { + .name =3D "qhs_usb3_0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1_cfg =3D { + .name =3D "qhs_usb3_1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_2_cfg =3D { + .name =3D "qhs_usb3_2_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_mp_cfg =3D { + .name =3D "qhs_usb3_mp_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb4_0_cfg =3D { + .name =3D "qhs_usb4_0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb4_1_cfg =3D { + .name =3D "qhs_usb4_1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb4_2_cfg =3D { + .name =3D "qhs_usb4_2_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_lpass_qtb_cfg =3D { + .name =3D "qss_lpass_qtb_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_nsp_qtb_cfg =3D { + .name =3D "qss_nsp_qtb_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_soccp =3D { + .name =3D "qhs_soccp", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_apss =3D { + .name =3D "qns_apss", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_boot_imem =3D { + .name =3D "qxs_boot_imem", + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .channels =3D 12, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_nsinoc =3D { + .name =3D "srvc_nsinoc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_pcie_east_aggre_noc =3D { + .name =3D "srvc_pcie_east_aggre_noc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_hscnoc_pcie_east_ms_mpu_cfg =3D { + .name =3D "qhs_hscnoc_pcie_east_ms_mpu_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_pcie_east =3D { + .name =3D "srvc_pcie_east", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node xs_pcie_5 =3D { + .name =3D "xs_pcie_5", + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node srvc_pcie_west_aggre_noc =3D { + .name =3D "srvc_pcie_west_aggre_noc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_hscnoc_pcie_west_ms_mpu_cfg =3D { + .name =3D "qhs_hscnoc_pcie_west_ms_mpu_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_pcie_west =3D { + .name =3D "srvc_pcie_west", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie_2 =3D { + .name =3D "xs_pcie_2", + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node xs_pcie_3a =3D { + .name =3D "xs_pcie_3a", + .channels =3D 1, + .buswidth =3D 64, +}; + +static struct qcom_icc_node xs_pcie_3b =3D { + .name =3D "xs_pcie_3b", + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node xs_pcie_4 =3D { + .name =3D "xs_pcie_4", + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node xs_pcie_6 =3D { + .name =3D "xs_pcie_6", + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup2_core_master =3D { + .name =3D "qup2_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qup2_core_slave }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .channels =3D 12, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &ebi }, +}; + +static struct qcom_icc_node qsm_mnoc_cfg =3D { + .name =3D "qsm_mnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_mnoc }, +}; + +static struct qcom_icc_node qsm_pcie_east_anoc_cfg =3D { + .name =3D "qsm_pcie_east_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_pcie_east_aggre_noc }, +}; + +static struct qcom_icc_node qnm_hscnoc_pcie_east =3D { + .name =3D "qnm_hscnoc_pcie_east", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 3, + .link_nodes =3D (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_5 }, +}; + +static struct qcom_icc_node qsm_cnoc_pcie_east_slave_cfg =3D { + .name =3D "qsm_cnoc_pcie_east_slave_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_east_ms_mpu= _cfg, + &srvc_pcie_east }, +}; + +static struct qcom_icc_node qsm_pcie_west_anoc_cfg =3D { + .name =3D "qsm_pcie_west_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_pcie_west_aggre_noc }, +}; + +static struct qcom_icc_node qnm_hscnoc_pcie_west =3D { + .name =3D "qnm_hscnoc_pcie_west", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 5, + .link_nodes =3D (struct qcom_icc_node *[]) { &xs_pcie_2, &xs_pcie_3a, + &xs_pcie_3b, &xs_pcie_4, + &xs_pcie_6 }, +}; + +static struct qcom_icc_node qsm_cnoc_pcie_west_slave_cfg =3D { + .name =3D "qsm_cnoc_pcie_west_slave_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_west_ms_mpu= _cfg, + &srvc_pcie_west }, +}; + +static struct qcom_icc_node qss_cnoc_pcie_slave_east_cfg =3D { + .name =3D "qss_cnoc_pcie_slave_east_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_east_slave_cf= g }, +}; + +static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg =3D { + .name =3D "qss_cnoc_pcie_slave_west_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_west_slave_cf= g }, +}; + +static struct qcom_icc_node qss_mnoc_cfg =3D { + .name =3D "qss_mnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_pcie_east_anoc_cfg =3D { + .name =3D "qss_pcie_east_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_pcie_east_anoc_cfg }, +}; + +static struct qcom_icc_node qss_pcie_west_anoc_cfg =3D { + .name =3D "qss_pcie_west_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_pcie_west_anoc_cfg }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .channels =3D 12, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie_east =3D { + .name =3D "qns_pcie_east", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_east }, +}; + +static struct qcom_icc_node qns_pcie_west =3D { + .name =3D "qns_pcie_west", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_west }, +}; + +static struct qcom_icc_node qsm_cfg =3D { + .name =3D "qsm_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 51, + .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_av1_enc_cfg, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_crypto0_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie2_cfg, + &qhs_pcie3a_cfg, &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, &qhs_pcie5_cfg, + &qhs_pcie6_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_smmuv3_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, + &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, + &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, + &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, + &qhs_usb4_2_cfg, &qhs_venus_cfg, + &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg, + &qss_pcie_west_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x33000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc }, +}; + +static struct qcom_icc_node qss_cfg =3D { + .name =3D "qss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qsm_cfg }, +}; + +static struct qcom_icc_node qnm_hscnoc_cnoc =3D { + .name =3D "qnm_hscnoc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 8, + .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_ipc_router, + &qhs_soccp, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qxs_boot_imem, &qxs_imem }, +}; + +static struct qcom_icc_node qns_hscnoc_cnoc =3D { + .name =3D "qns_hscnoc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_hscnoc_cnoc }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x933000 }, + .prio =3D 1, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, +}; + +static struct qcom_icc_node alm_pcie_qtc =3D { + .name =3D "alm_pcie_qtc", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x51f000 }, + .prio =3D 3, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x51f080 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .channels =3D 6, + .buswidth =3D 32, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_aggre_noc_east =3D { + .name =3D "qnm_aggre_noc_east", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x934000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .channels =3D 4, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 4, + .port_offsets =3D { 0x935000, 0x936000, 0x937000, 0x938000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_lpass =3D { + .name =3D "qnm_lpass", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x939000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x721000, 0x721080 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x721100, 0x721180 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_nsp_noc =3D { + .name =3D "qnm_nsp_noc", + .channels =3D 4, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 4, + .port_offsets =3D { 0x816000, 0x816080, 0x816100, 0x816180 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_pcie_east =3D { + .name =3D "qnm_pcie_east", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x93a000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, +}; + +static struct qcom_icc_node qnm_pcie_west =3D { + .name =3D "qnm_pcie_west", + .channels =3D 1, + .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x721200 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc = }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .channels =3D 1, + .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x51f100 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qxm_wlan_q6 =3D { + .name =3D "qxm_wlan_q6", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 4, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qns_a4noc_hscnoc =3D { + .name =3D "qns_a4noc_hscnoc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre_noc_east }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { + .name =3D "qns_lpass_ag_noc_gemnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpass }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node qns_nsp_hscnoc =3D { + .name =3D "qns_nsp_hscnoc", + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_nsp_noc }, +}; + +static struct qcom_icc_node qns_pcie_east_mem_noc =3D { + .name =3D "qns_pcie_east_mem_noc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_pcie_east }, +}; + +static struct qcom_icc_node qns_pcie_west_mem_noc =3D { + .name =3D "qns_pcie_west_mem_noc", + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_pcie_west }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb4_0 =3D { + .name =3D "xm_usb4_0", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb4_1 =3D { + .name =3D "xm_usb4_1", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc =3D { + .name =3D "qnm_lpiaon_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc }, +}; + +static struct qcom_icc_node qnm_av1_enc =3D { + .name =3D "qnm_av1_enc", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x30000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x29000, 0x2a000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_camnoc_icp =3D { + .name =3D "qnm_camnoc_icp", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2b000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x2c000, 0x2d000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_eva =3D { + .name =3D "qnm_eva", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x34000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_mdp =3D { + .name =3D "qnm_mdp", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x2e000, 0x2f000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_vapss_hcp =3D { + .name =3D "qnm_vapss_hcp", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video =3D { + .name =3D "qnm_video", + .channels =3D 4, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 4, + .port_offsets =3D { 0x31000, 0x32000, 0x37000, 0x38000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu =3D { + .name =3D "qnm_video_cv_cpu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x33000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu =3D { + .name =3D "qnm_video_v_cpu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x35000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_nsp =3D { + .name =3D "qnm_nsp", + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_nsp_hscnoc }, +}; + +static struct qcom_icc_node xm_pcie_0 =3D { + .name =3D "xm_pcie_0", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_1 =3D { + .name =3D "xm_pcie_1", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_5 =3D { + .name =3D "xm_pcie_5", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_2 =3D { + .name =3D "xm_pcie_2", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_3a =3D { + .name =3D "xm_pcie_3a", + .channels =3D 1, + .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd200 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_3b =3D { + .name =3D "xm_pcie_3b", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd400 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_4 =3D { + .name =3D "xm_pcie_4", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd600 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_6 =3D { + .name =3D "xm_pcie_6", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd800 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre3_noc =3D { + .name =3D "qnm_aggre3_noc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_nsi_noc =3D { + .name =3D "qnm_nsi_noc", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1c000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_oobmss =3D { + .name =3D "qnm_oobmss", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1b000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qns_a3noc_snoc =3D { + .name =3D "qns_a3noc_snoc", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre3_noc }, +}; + +static struct qcom_icc_node qns_lpass_aggnoc =3D { + .name =3D "qns_lpass_aggnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpiaon_noc }, +}; + +static struct qcom_icc_node qns_system_noc =3D { + .name =3D "qns_system_noc", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_nsi_noc }, +}; + +static struct qcom_icc_node qns_oobmss_snoc =3D { + .name =3D "qns_oobmss_snoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_oobmss }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_soccp =3D { + .name =3D "qxm_soccp", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 =3D { + .name =3D "xm_qdss_etr_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 =3D { + .name =3D "xm_qdss_etr_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3_2 =3D { + .name =3D "xm_usb3_2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x8000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_usb4_2 =3D { + .name =3D "xm_usb4_2", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x10000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qxm_sp =3D { + .name =3D "qxm_sp", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node xm_usb2_0 =3D { + .name =3D "xm_usb2_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3_mp =3D { + .name =3D "xm_usb3_mp", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qnm_lpass_lpinoc =3D { + .name =3D "qnm_lpass_lpinoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_node xm_cpucp =3D { + .name =3D "xm_cpucp", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_system_noc, &srvc_nsino= c }, +}; + +static struct qcom_icc_node xm_mem_sp =3D { + .name =3D "xm_mem_sp", + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_oobmss_snoc }, +}; + +static struct qcom_icc_node qns_lpi_aon_noc =3D { + .name =3D "qns_lpi_aon_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpass_lpinoc }, +}; + +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m =3D { + .name =3D "qnm_lpinoc_dsp_qns4m", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D (struct qcom_icc_node *[]) { &qns_lpi_aon_noc }, +}; + +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .enable_mask =3D BIT(3), + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .enable_mask =3D BIT(0), + .num_nodes =3D 60, + .nodes =3D { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_ahb2phy2, + &qhs_ahb2phy3, &qhs_av1_enc_cfg, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie2_cfg, + &qhs_pcie3a_cfg, &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, &qhs_pcie5_cfg, + &qhs_pcie6_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_smmuv3_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, + &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, + &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, + &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, + &qhs_usb4_2_cfg, &qhs_venus_cfg, + &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg, + &qss_pcie_west_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg, &qnm_hscnoc_cnoc, + &qhs_aoss, &qhs_ipc_router, + &qhs_soccp, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qxs_boot_imem, &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .num_nodes =3D 1, + .nodes =3D { &qhs_display_cfg }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .enable_mask =3D BIT(0), + .num_nodes =3D 2, + .nodes =3D { &qnm_nsp, &qns_nsp_hscnoc }, +}; + +static struct qcom_icc_bcm bcm_lp0 =3D { + .name =3D "LP0", + .num_nodes =3D 2, + .nodes =3D { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .enable_mask =3D BIT(0), + .num_nodes =3D 11, + .nodes =3D { &qnm_av1_enc, &qnm_camnoc_hf, + &qnm_camnoc_icp, &qnm_camnoc_sf, + &qnm_eva, &qnm_mdp, + &qnm_vapss_hcp, &qnm_video, + &qnm_video_cv_cpu, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 =3D { + .name =3D "QUP1", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 =3D { + .name =3D "QUP2", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D BIT(0), + .num_nodes =3D 18, + .nodes =3D { &alm_gpu_tcu, &alm_pcie_qtc, + &alm_sys_tcu, &chm_apps, + &qnm_aggre_noc_east, &qnm_gpu, + &qnm_lpass, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_noc, + &qnm_pcie_east, &qnm_pcie_west, + &qnm_snoc_sf, &qxm_wlan_q6, + &xm_gic, &qns_hscnoc_cnoc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .enable_mask =3D BIT(0), + .num_nodes =3D 1, + .nodes =3D { &qnm_oobmss }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre3_noc }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .num_nodes =3D 1, + .nodes =3D { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_bcm bcm_sn6 =3D { + .name =3D "SN6", + .num_nodes =3D 4, + .nodes =3D { &qns_pcie_east_mem_noc, &qnm_hscnoc_pcie_east, + &qns_pcie_west_mem_noc, &qnm_hscnoc_pcie_west }, +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] =3D { + [MASTER_CRYPTO] =3D &qxm_crypto, + [MASTER_SOCCP_PROC] =3D &qxm_soccp, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr_1, + [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, +}; + +static const struct regmap_config glymur_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_aggre1_noc =3D { + .config =3D &glymur_aggre1_noc_regmap_config, + .nodes =3D aggre1_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), + .bcms =3D aggre1_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] =3D { + [MASTER_UFS_MEM] =3D &xm_ufs_mem, + [MASTER_USB3_2] =3D &xm_usb3_2, + [MASTER_USB4_2] =3D &xm_usb4_2, + [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, +}; + +static const struct regmap_config glymur_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_aggre2_noc =3D { + .config =3D &glymur_aggre2_noc_regmap_config, + .nodes =3D aggre2_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), + .alloc_dyn_id =3D true, + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_node * const aggre3_noc_nodes[] =3D { + [MASTER_QSPI_0] =3D &qhm_qspi, + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_QUP_1] =3D &qhm_qup1, + [MASTER_QUP_2] =3D &qhm_qup2, + [MASTER_SP] =3D &qxm_sp, + [MASTER_SDCC_2] =3D &xm_sdc2, + [MASTER_SDCC_4] =3D &xm_sdc4, + [MASTER_USB2] =3D &xm_usb2_0, + [MASTER_USB3_MP] =3D &xm_usb3_mp, + [SLAVE_A3NOC_SNOC] =3D &qns_a3noc_snoc, +}; + +static const struct regmap_config glymur_aggre3_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1d400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_aggre3_noc =3D { + .config =3D &glymur_aggre3_noc_regmap_config, + .nodes =3D aggre3_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre3_noc_nodes), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const aggre4_noc_bcms[] =3D { + &bcm_sn5, +}; + +static struct qcom_icc_node * const aggre4_noc_nodes[] =3D { + [MASTER_USB3_0] =3D &xm_usb3_0, + [MASTER_USB3_1] =3D &xm_usb3_1, + [MASTER_USB4_0] =3D &xm_usb4_0, + [MASTER_USB4_1] =3D &xm_usb4_1, + [SLAVE_A4NOC_HSCNOC] =3D &qns_a4noc_hscnoc, +}; + +static const struct regmap_config glymur_aggre4_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_aggre4_noc =3D { + .config =3D &glymur_aggre4_noc_regmap_config, + .nodes =3D aggre4_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre4_noc_nodes), + .bcms =3D aggre4_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre4_noc_bcms), + .alloc_dyn_id =3D true, + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [MASTER_QUP_CORE_1] =3D &qup1_core_master, + [MASTER_QUP_CORE_2] =3D &qup2_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, + [SLAVE_QUP_CORE_1] =3D &qup1_core_slave, + [SLAVE_QUP_CORE_2] =3D &qup2_core_slave, +}; + +static const struct qcom_icc_desc glymur_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] =3D { + [MASTER_CNOC_CFG] =3D &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] =3D &qhs_ahb2phy1, + [SLAVE_AHB2PHY_2] =3D &qhs_ahb2phy2, + [SLAVE_AHB2PHY_3] =3D &qhs_ahb2phy3, + [SLAVE_AV1_ENC_CFG] =3D &qhs_av1_enc_cfg, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_DISPLAY_CFG] =3D &qhs_display_cfg, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] =3D &qhs_pcie1_cfg, + [SLAVE_PCIE_2_CFG] =3D &qhs_pcie2_cfg, + [SLAVE_PCIE_3A_CFG] =3D &qhs_pcie3a_cfg, + [SLAVE_PCIE_3B_CFG] =3D &qhs_pcie3b_cfg, + [SLAVE_PCIE_4_CFG] =3D &qhs_pcie4_cfg, + [SLAVE_PCIE_5_CFG] =3D &qhs_pcie5_cfg, + [SLAVE_PCIE_6_CFG] =3D &qhs_pcie6_cfg, + [SLAVE_PCIE_RSCC] =3D &qhs_pcie_rscc, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QSPI_0] =3D &qhs_qspi, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_QUP_2] =3D &qhs_qup2, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_SDCC_4] =3D &qhs_sdc4, + [SLAVE_SMMUV3_CFG] =3D &qhs_smmuv3_cfg, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB2] =3D &qhs_usb2_0_cfg, + [SLAVE_USB3_0] =3D &qhs_usb3_0_cfg, + [SLAVE_USB3_1] =3D &qhs_usb3_1_cfg, + [SLAVE_USB3_2] =3D &qhs_usb3_2_cfg, + [SLAVE_USB3_MP] =3D &qhs_usb3_mp_cfg, + [SLAVE_USB4_0] =3D &qhs_usb4_0_cfg, + [SLAVE_USB4_1] =3D &qhs_usb4_1_cfg, + [SLAVE_USB4_2] =3D &qhs_usb4_2_cfg, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_CNOC_PCIE_SLAVE_EAST_CFG] =3D &qss_cnoc_pcie_slave_east_cfg, + [SLAVE_CNOC_PCIE_SLAVE_WEST_CFG] =3D &qss_cnoc_pcie_slave_west_cfg, + [SLAVE_LPASS_QTB_CFG] =3D &qss_lpass_qtb_cfg, + [SLAVE_CNOC_MNOC_CFG] =3D &qss_mnoc_cfg, + [SLAVE_NSP_QTB_CFG] =3D &qss_nsp_qtb_cfg, + [SLAVE_PCIE_EAST_ANOC_CFG] =3D &qss_pcie_east_anoc_cfg, + [SLAVE_PCIE_WEST_ANOC_CFG] =3D &qss_pcie_west_anoc_cfg, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct regmap_config glymur_cnoc_cfg_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x6600, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_cnoc_cfg =3D { + .config =3D &glymur_cnoc_cfg_regmap_config, + .nodes =3D cnoc_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), + .bcms =3D cnoc_cfg_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_HSCNOC_CNOC] =3D &qnm_hscnoc_cnoc, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_SOCCP] =3D &qhs_soccp, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_APPSS] =3D &qns_apss, + [SLAVE_CNOC_CFG] =3D &qss_cfg, + [SLAVE_BOOT_IMEM] =3D &qxs_boot_imem, + [SLAVE_IMEM] =3D &qxs_imem, +}; + +static const struct regmap_config glymur_cnoc_main_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_cnoc_main =3D { + .config =3D &glymur_cnoc_main_regmap_config, + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const hscnoc_bcms[] =3D { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const hscnoc_nodes[] =3D { + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_PCIE_TCU] =3D &alm_pcie_qtc, + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_AGGRE_NOC_EAST] =3D &qnm_aggre_noc_east, + [MASTER_GFX3D] =3D &qnm_gpu, + [MASTER_LPASS_GEM_NOC] =3D &qnm_lpass, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] =3D &qnm_nsp_noc, + [MASTER_PCIE_EAST] =3D &qnm_pcie_east, + [MASTER_PCIE_WEST] =3D &qnm_pcie_west, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_WLAN_Q6] =3D &qxm_wlan_q6, + [MASTER_GIC] =3D &xm_gic, + [SLAVE_HSCNOC_CNOC] =3D &qns_hscnoc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_PCIE_EAST] =3D &qns_pcie_east, + [SLAVE_PCIE_WEST] =3D &qns_pcie_west, +}; + +static const struct regmap_config glymur_hscnoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x93a080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_hscnoc =3D { + .config =3D &glymur_hscnoc_regmap_config, + .nodes =3D hscnoc_nodes, + .num_nodes =3D ARRAY_SIZE(hscnoc_nodes), + .bcms =3D hscnoc_bcms, + .num_bcms =3D ARRAY_SIZE(hscnoc_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { + [MASTER_LPIAON_NOC] =3D &qnm_lpiaon_noc, + [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, +}; + +static const struct regmap_config glymur_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xe080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_lpass_ag_noc =3D { + .config =3D &glymur_lpass_ag_noc_regmap_config, + .nodes =3D lpass_ag_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] =3D { + &bcm_lp0, +}; + +static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] =3D { + [MASTER_LPASS_LPINOC] =3D &qnm_lpass_lpinoc, + [SLAVE_LPIAON_NOC_LPASS_AG_NOC] =3D &qns_lpass_aggnoc, +}; + +static const struct regmap_config glymur_lpass_lpiaon_noc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x19080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_lpass_lpiaon_noc =3D { + .config =3D &glymur_lpass_lpiaon_noc_regmap_config, + .nodes =3D lpass_lpiaon_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), + .bcms =3D lpass_lpiaon_noc_bcms, + .num_bcms =3D ARRAY_SIZE(lpass_lpiaon_noc_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] =3D { + [MASTER_LPASS_PROC] =3D &qnm_lpinoc_dsp_qns4m, + [SLAVE_LPICX_NOC_LPIAON_NOC] =3D &qns_lpi_aon_noc, +}; + +static const struct regmap_config glymur_lpass_lpicx_noc_regmap_config =3D= { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x44080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_lpass_lpicx_noc =3D { + .config =3D &glymur_lpass_lpicx_noc_regmap_config, + .nodes =3D lpass_lpicx_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc glymur_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] =3D { + [MASTER_AV1_ENC] =3D &qnm_av1_enc, + [MASTER_CAMNOC_HF] =3D &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] =3D &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] =3D &qnm_camnoc_sf, + [MASTER_EVA] =3D &qnm_eva, + [MASTER_MDP] =3D &qnm_mdp, + [MASTER_CDSP_HCP] =3D &qnm_vapss_hcp, + [MASTER_VIDEO] =3D &qnm_video, + [MASTER_VIDEO_CV_PROC] =3D &qnm_video_cv_cpu, + [MASTER_VIDEO_V_PROC] =3D &qnm_video_v_cpu, + [MASTER_CNOC_MNOC_CFG] =3D &qsm_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] =3D &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] =3D &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] =3D &srvc_mnoc, +}; + +static const struct regmap_config glymur_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5b800, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_mmss_noc =3D { + .config =3D &glymur_mmss_noc_regmap_config, + .nodes =3D mmss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), + .bcms =3D mmss_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_node * const nsinoc_nodes[] =3D { + [MASTER_CPUCP] =3D &xm_cpucp, + [SLAVE_NSINOC_SYSTEM_NOC] =3D &qns_system_noc, + [SLAVE_SERVICE_NSINOC] =3D &srvc_nsinoc, +}; + +static const struct regmap_config glymur_nsinoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_nsinoc =3D { + .config =3D &glymur_nsinoc_regmap_config, + .nodes =3D nsinoc_nodes, + .num_nodes =3D ARRAY_SIZE(nsinoc_nodes), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] =3D { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] =3D { + [MASTER_CDSP_PROC] =3D &qnm_nsp, + [SLAVE_NSP0_HSC_NOC] =3D &qns_nsp_hscnoc, +}; + +static const struct regmap_config glymur_nsp_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x21280, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_nsp_noc =3D { + .config =3D &glymur_nsp_noc_regmap_config, + .nodes =3D nsp_noc_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), + .bcms =3D nsp_noc_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_noc_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_node * const oobm_ss_noc_nodes[] =3D { + [MASTER_OOBMSS_SP_PROC] =3D &xm_mem_sp, + [SLAVE_OOBMSS_SNOC] =3D &qns_oobmss_snoc, +}; + +static const struct regmap_config glymur_oobm_ss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1e080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_oobm_ss_noc =3D { + .config =3D &glymur_oobm_ss_noc_regmap_config, + .nodes =3D oobm_ss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(oobm_ss_noc_nodes), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] =3D { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_east_anoc_nodes[] =3D { + [MASTER_PCIE_EAST_ANOC_CFG] =3D &qsm_pcie_east_anoc_cfg, + [MASTER_PCIE_0] =3D &xm_pcie_0, + [MASTER_PCIE_1] =3D &xm_pcie_1, + [MASTER_PCIE_5] =3D &xm_pcie_5, + [SLAVE_PCIE_EAST_MEM_NOC] =3D &qns_pcie_east_mem_noc, + [SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC] =3D &srvc_pcie_east_aggre_noc, +}; + +static const struct regmap_config glymur_pcie_east_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf300, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_pcie_east_anoc =3D { + .config =3D &glymur_pcie_east_anoc_regmap_config, + .nodes =3D pcie_east_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_east_anoc_nodes), + .bcms =3D pcie_east_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_east_anoc_bcms), + .alloc_dyn_id =3D true, + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_bcm * const pcie_east_slv_noc_bcms[] =3D { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_east_slv_noc_nodes[] =3D { + [MASTER_HSCNOC_PCIE_EAST] =3D &qnm_hscnoc_pcie_east, + [MASTER_CNOC_PCIE_EAST_SLAVE_CFG] =3D &qsm_cnoc_pcie_east_slave_cfg, + [SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG] =3D &qhs_hscnoc_pcie_east_ms_mpu_cfg, + [SLAVE_SERVICE_PCIE_EAST] =3D &srvc_pcie_east, + [SLAVE_PCIE_0] =3D &xs_pcie_0, + [SLAVE_PCIE_1] =3D &xs_pcie_1, + [SLAVE_PCIE_5] =3D &xs_pcie_5, +}; + +static const struct regmap_config glymur_pcie_east_slv_noc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xe080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_pcie_east_slv_noc =3D { + .config =3D &glymur_pcie_east_slv_noc_regmap_config, + .nodes =3D pcie_east_slv_noc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_east_slv_noc_nodes), + .bcms =3D pcie_east_slv_noc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_east_slv_noc_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] =3D { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_west_anoc_nodes[] =3D { + [MASTER_PCIE_WEST_ANOC_CFG] =3D &qsm_pcie_west_anoc_cfg, + [MASTER_PCIE_2] =3D &xm_pcie_2, + [MASTER_PCIE_3A] =3D &xm_pcie_3a, + [MASTER_PCIE_3B] =3D &xm_pcie_3b, + [MASTER_PCIE_4] =3D &xm_pcie_4, + [MASTER_PCIE_6] =3D &xm_pcie_6, + [SLAVE_PCIE_WEST_MEM_NOC] =3D &qns_pcie_west_mem_noc, + [SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] =3D &srvc_pcie_west_aggre_noc, +}; + +static const struct regmap_config glymur_pcie_west_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf580, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_pcie_west_anoc =3D { + .config =3D &glymur_pcie_west_anoc_regmap_config, + .nodes =3D pcie_west_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_west_anoc_nodes), + .bcms =3D pcie_west_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_west_anoc_bcms), + .alloc_dyn_id =3D true, + .qos_requires_clocks =3D true, +}; + +static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] =3D { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] =3D { + [MASTER_HSCNOC_PCIE_WEST] =3D &qnm_hscnoc_pcie_west, + [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] =3D &qsm_cnoc_pcie_west_slave_cfg, + [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] =3D &qhs_hscnoc_pcie_west_ms_mpu_cfg, + [SLAVE_SERVICE_PCIE_WEST] =3D &srvc_pcie_west, + [SLAVE_PCIE_2] =3D &xs_pcie_2, + [SLAVE_PCIE_3A] =3D &xs_pcie_3a, + [SLAVE_PCIE_3B] =3D &xs_pcie_3b, + [SLAVE_PCIE_4] =3D &xs_pcie_4, + [SLAVE_PCIE_6] =3D &xs_pcie_6, +}; + +static const struct regmap_config glymur_pcie_west_slv_noc_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf180, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_pcie_west_slv_noc =3D { + .config =3D &glymur_pcie_west_slv_noc_regmap_config, + .nodes =3D pcie_west_slv_noc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_west_slv_noc_nodes), + .bcms =3D pcie_west_slv_noc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_west_slv_noc_bcms), + .alloc_dyn_id =3D true, +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, + &bcm_sn4, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_A1NOC_SNOC] =3D &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] =3D &qnm_aggre2_noc, + [MASTER_A3NOC_SNOC] =3D &qnm_aggre3_noc, + [MASTER_NSINOC_SNOC] =3D &qnm_nsi_noc, + [MASTER_OOBMSS] =3D &qnm_oobmss, + [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, +}; + +static const struct regmap_config glymur_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc glymur_system_noc =3D { + .config =3D &glymur_system_noc_regmap_config, + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), + .alloc_dyn_id =3D true, +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,glymur-aggre1-noc", .data =3D &glymur_aggre1_noc}, + { .compatible =3D "qcom,glymur-aggre2-noc", .data =3D &glymur_aggre2_noc}, + { .compatible =3D "qcom,glymur-aggre3-noc", .data =3D &glymur_aggre3_noc}, + { .compatible =3D "qcom,glymur-aggre4-noc", .data =3D &glymur_aggre4_noc}, + { .compatible =3D "qcom,glymur-clk-virt", .data =3D &glymur_clk_virt}, + { .compatible =3D "qcom,glymur-cnoc-cfg", .data =3D &glymur_cnoc_cfg}, + { .compatible =3D "qcom,glymur-cnoc-main", .data =3D &glymur_cnoc_main}, + { .compatible =3D "qcom,glymur-hscnoc", .data =3D &glymur_hscnoc}, + { .compatible =3D "qcom,glymur-lpass-ag-noc", .data =3D &glymur_lpass_ag_= noc}, + { .compatible =3D "qcom,glymur-lpass-lpiaon-noc", .data =3D &glymur_lpass= _lpiaon_noc}, + { .compatible =3D "qcom,glymur-lpass-lpicx-noc", .data =3D &glymur_lpass_= lpicx_noc}, + { .compatible =3D "qcom,glymur-mc-virt", .data =3D &glymur_mc_virt}, + { .compatible =3D "qcom,glymur-mmss-noc", .data =3D &glymur_mmss_noc}, + { .compatible =3D "qcom,glymur-nsinoc", .data =3D &glymur_nsinoc}, + { .compatible =3D "qcom,glymur-nsp-noc", .data =3D &glymur_nsp_noc}, + { .compatible =3D "qcom,glymur-oobm-ss-noc", .data =3D &glymur_oobm_ss_no= c}, + { .compatible =3D "qcom,glymur-pcie-east-anoc", .data =3D &glymur_pcie_ea= st_anoc}, + { .compatible =3D "qcom,glymur-pcie-east-slv-noc", .data =3D &glymur_pcie= _east_slv_noc}, + { .compatible =3D "qcom,glymur-pcie-west-anoc", .data =3D &glymur_pcie_we= st_anoc}, + { .compatible =3D "qcom,glymur-pcie-west-slv-noc", .data =3D &glymur_pcie= _west_slv_noc}, + { .compatible =3D "qcom,glymur-system-noc", .data =3D &glymur_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-glymur", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("GLYMUR NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0