From nobody Sat Oct 4 17:34:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04576239E67; Thu, 14 Aug 2025 06:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755153181; cv=none; b=ZDPAVgXAyxGjFBx8SQmY7ig2QtJvkVzybUrBwgBu+vAg/uaCK7XjvPy5FN1f+xOYI+JbAiVPIZvbwV6fzjGmcsaaJInA9UOKGh41yiISw84XcFQAYbpJK3gDeHsxNi5PYIkqfRYBjvdNWP9gXhHGpsandviq2fJ/THj2hGs12Mc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755153181; c=relaxed/simple; bh=OUSduZHpQytaAfXKSV2SoQ+CWi6AI0udx0LxSMgifvY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RX/4SFQbiyYZKNnoyqHNyn939I29bU12mtTC8doKzXV/j7SCg3xbN8j3pDsfmsr174nQe/dXjugcsXwuSFVjTQCNJfyGL4JvLyMymRlP3/R+4CroG2ZjCEIWjRYcKHi0jzj+64A2dqhHdbn8/pzA5NllvNG3TW73rz1lUaYoIZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qjiK4xVf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qjiK4xVf" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8F6D7C4CEF5; Thu, 14 Aug 2025 06:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755153180; bh=OUSduZHpQytaAfXKSV2SoQ+CWi6AI0udx0LxSMgifvY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qjiK4xVfT+BD6LcYE4yVxmg6/loKD3035deHerx5W5E/pjhi1g/hXkB84h+C03wU2 qeHBtgE4ZBcL+Kgxl1Eb2adCe+wx1RmJFEvcLDedDQ0oc6H2S685MwqKjUyWTC8nfP GEqhneZCjp8113tsY5mrRJWozxWhBWu9+TYaMTelBz22uCSXcoSzoS+PFXlczI7ZqI qZCdoVxxek2731vomCbughwGPsOPjgwlWAjoYHQ3Rb4tZwiBtxn+uDmIdZK+/R6hwe 46lvTZ8EPUdlTOa1R8K6z48O7jrzIoFeWA5weFzhJUWqdKb+Lkan2Zb29z2kdWWTnd qs1ci7l634vZg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ED02CA0EDC; Thu, 14 Aug 2025 06:33:00 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Thu, 14 Aug 2025 14:32:44 +0800 Subject: [PATCH v2 1/2] dt-bindings: clock: add video clock indices for Amlogic S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-add_video_clk-v2-1-bb2b5a5f2904@amlogic.com> References: <20250814-add_video_clk-v2-0-bb2b5a5f2904@amlogic.com> In-Reply-To: <20250814-add_video_clk-v2-0-bb2b5a5f2904@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755153176; l=1113; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=bgu6e/fPXdfrF8SBobYJP00S8M4VvuEqG6nMELJh9dQ=; b=dLOnByYR4ot9TJREpWOoEnTKvj/IOsLcAtxaBMxhrBz8/5bDjbyeYgRStS76ese8bvWi2onpv YDWOoJ4ipPQCOGmKZjZiol6b/nO4oG8z6xhEZ5rr1QjccNJRUsQjm6K X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add indices for video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,s4-peripherals-clkc.h index 861a331963ac..b0fc549f53e3 100644 --- a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h +++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h @@ -232,5 +232,16 @@ #define CLKID_HDCP22_SKPCLK_SEL 222 #define CLKID_HDCP22_SKPCLK_DIV 223 #define CLKID_HDCP22_SKPCLK 224 +#define CLKID_CTS_ENCL_SEL 225 +#define CLKID_CTS_ENCL 226 +#define CLKID_CDAC_SEL 227 +#define CLKID_CDAC_DIV 228 +#define CLKID_CDAC 229 +#define CLKID_DEMOD_CORE_SEL 230 +#define CLKID_DEMOD_CORE_DIV 231 +#define CLKID_DEMOD_CORE 232 +#define CLKID_ADC_EXTCLK_IN_SEL 233 +#define CLKID_ADC_EXTCLK_IN_DIV 234 +#define CLKID_ADC_EXTCLK_IN 235 =20 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */ --=20 2.42.0 From nobody Sat Oct 4 17:34:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0450F1F5827; Thu, 14 Aug 2025 06:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755153181; cv=none; b=jHqFKnxlMwjFNgc1y1Zp3wEUoiQsMCKaI0xS/j9xfZOai9lQrawdVA2dPpICsXa/5hvvnlje7Eq6Z1mGoEt9w0g2U4WYRAxPbNI/zFgMWj3g1q85md1OjuUOTo3jMeMtXbuP0rIBgSZC6lxO9N/hZUC1Ztmd1RmE1FIqmkSPjN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755153181; c=relaxed/simple; bh=VSgImVuCqCH2tx9gJklqhA/Q7iOTvOvF3jkJS6V32lM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cKsPBFkipmvDiNgV/IK5Bc4Tstzow1JjjZl+jmX5Z3YB/poW7E77VqS18QpCEdznSErhNiH0BiIQqlyiMtmO+SPtCalbXgAqTdWyATjRV6DlMMgBzujGikqIgTCNAmaBiVxFm1SdOclSnsWNuojTNkvuk4yGvv0mpsZb9qeJrL8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J8phELsS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J8phELsS" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9DA97C4CEF4; Thu, 14 Aug 2025 06:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755153180; bh=VSgImVuCqCH2tx9gJklqhA/Q7iOTvOvF3jkJS6V32lM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=J8phELsSSCuexZ9uWF/rqirT7VfAFWsXFXLGCnkORHNLHl85ZbrcMyEIw96f9UTw3 jAU7Gn4q6b4tV6LL7tedVn4jsqomSLQDjSF7GMk2abgr/VXvjlsfcFbxtPWR7Vvx6r 58zlM17F5MvfJb861LXauuXjNQvw8VvDFIQIg9FmkYO+BRHXmNPJXI4Eaw8H0EPcc4 aIq1xznzP+bfW5oQXHkFDytYR4Mdy5NuAH7zRctIPY3tnC/aahvSGePQF+ogP7nKjX DcbC6ureMAS3n0mRwU8zwDE4jeoTcoH1g2IQWLDtVmy2G2TZ8LRNnpuFr8NDIc8i5o 6Zk1W7cNaZ2iw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C49FCA0EE4; Thu, 14 Aug 2025 06:33:00 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Thu, 14 Aug 2025 14:32:45 +0800 Subject: [PATCH v2 2/2] clk: amlogic: add video-related clocks for S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250814-add_video_clk-v2-2-bb2b5a5f2904@amlogic.com> References: <20250814-add_video_clk-v2-0-bb2b5a5f2904@amlogic.com> In-Reply-To: <20250814-add_video_clk-v2-0-bb2b5a5f2904@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755153176; l=7096; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=sYvEeZ4oYnSosnGYzWTsQjmj6ZIK9npvOzvOGvDxsvM=; b=GskWItH4d/0b/sbn+Tk54ut4IfML7X3nSuWQxzqDIEhiXU8vGrZO/++k0PCCsuuaQy+dFr09u 9YPTK4QYziMCJCENfTq1TbI3y1RJBxsxmeq4qJJv6Tv47oDgRNrdrtu X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu --- drivers/clk/meson/s4-peripherals.c | 203 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 203 insertions(+) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index c9400cf54c84..77c550376fc8 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -44,6 +44,7 @@ #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 #define CLKCTRL_VAPBCLK_CTRL 0x0fc #define CLKCTRL_HDCP22_CTRL 0x100 +#define CLKCTRL_CDAC_CLK_CTRL 0x108 #define CLKCTRL_VDEC_CLK_CTRL 0x140 #define CLKCTRL_VDEC2_CLK_CTRL 0x144 #define CLKCTRL_VDEC3_CLK_CTRL 0x148 @@ -1117,6 +1118,22 @@ static struct clk_regmap s4_cts_encp_sel =3D { }, }; =20 +static struct clk_regmap s4_cts_encl_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 12, + .table =3D mux_table_cts_sel, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cts_encl_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D s4_cts_parent_hws, + .num_parents =3D ARRAY_SIZE(s4_cts_parent_hws), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VIID_CLK_DIV, @@ -1196,6 +1213,22 @@ static struct clk_regmap s4_cts_encp =3D { }, }; =20 +static struct clk_regmap s4_cts_encl =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_VID_CLK_CTRL2, + .bit_idx =3D 3, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cts_encl", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cts_encl_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VID_CLK_CTRL2, @@ -3174,6 +3207,165 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 +/* CVBS DAC */ +static struct clk_regmap s4_cdac_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fclk_div5" }, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap s4_cdac_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .shift =3D 0, + .width =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_cdac =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "fclk_div4" } + }, + .num_parents =3D 3, + }, +}; + +static struct clk_regmap s4_demod_core_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 8 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* CVBS ADC */ +static struct clk_regmap s4_adc_extclk_in_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div4" }, + { .fw_name =3D "fclk_div3" }, + { .fw_name =3D "fclk_div5" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "gp0_pll" }, + { .fw_name =3D "hifi_pll" } + }, + .num_parents =3D 8, + }, +}; + +static struct clk_regmap s4_adc_extclk_in_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_adc_extclk_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 24 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + #define MESON_GATE(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) =20 @@ -3453,6 +3645,17 @@ static struct clk_hw *s4_periphs_hw_clks[] =3D { [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_mux.hw, [CLKID_HDCP22_SKPCLK_DIV] =3D &s4_hdcp22_skpclk_div.hw, [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk_gate.hw, + [CLKID_CTS_ENCL_SEL] =3D &s4_cts_encl_sel.hw, + [CLKID_CTS_ENCL] =3D &s4_cts_encl.hw, + [CLKID_CDAC_SEL] =3D &s4_cdac_sel.hw, + [CLKID_CDAC_DIV] =3D &s4_cdac_div.hw, + [CLKID_CDAC] =3D &s4_cdac.hw, + [CLKID_DEMOD_CORE_SEL] =3D &s4_demod_core_sel.hw, + [CLKID_DEMOD_CORE_DIV] =3D &s4_demod_core_div.hw, + [CLKID_DEMOD_CORE] =3D &s4_demod_core.hw, + [CLKID_ADC_EXTCLK_IN_SEL] =3D &s4_adc_extclk_in_sel.hw, + [CLKID_ADC_EXTCLK_IN_DIV] =3D &s4_adc_extclk_in_div.hw, + [CLKID_ADC_EXTCLK_IN] =3D &s4_adc_extclk_in.hw, }; =20 static const struct regmap_config clkc_regmap_config =3D { --=20 2.42.0