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Wed, 13 Aug 2025 16:29:42 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Bjorn Helgaas , Marc Zyngier , Lorenzo Pieralisi , Shradha Gupta , Haiyang Zhang , Inochi Amaoto , Jonathan Cameron , Juergen Gross , Nicolin Chen , Jason Gunthorpe , Chen Wang Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Yixun Lan , Longbin Li , Han Gao Subject: [PATCH v2 3/4] irqchip/sg2042-msi: Fix broken affinity setting Date: Thu, 14 Aug 2025 07:28:33 +0800 Message-ID: <20250813232835.43458-4-inochiama@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250813232835.43458-1-inochiama@gmail.com> References: <20250813232835.43458-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When using NVME on SG2044, the NVME always complains "I/O tag XXX (XXX) QID XX timeout, completion polled", which is caused by the broken handler of the sg2042-msi driver. As PLIC driver can only set affinity when enabling, the sg2042-msi does not properly handled affinity setting previously and enables irq in an unexpected executing path. Since the PCI template domain supports irq_startup()/irq_shutdown(), set irq_chip_[startup/shutdown]_parent() for irq_startup() and irq_shutdown(). So the irq can be started properly. Fixes: e96b93a97c90 ("irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interru= pt controller") Reported-by: Han Gao Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto --- drivers/irqchip/irq-sg2042-msi.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index bcfddc51bc6a..2fd4d94f9bd7 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -85,6 +85,8 @@ static void sg2042_msi_irq_compose_msi_msg(struct irq_dat= a *d, struct msi_msg *m =20 static const struct irq_chip sg2042_msi_middle_irq_chip =3D { .name =3D "SG2042 MSI", + .irq_startup =3D irq_chip_startup_parent, + .irq_shutdown =3D irq_chip_shutdown_parent, .irq_ack =3D sg2042_msi_irq_ack, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, @@ -114,6 +116,8 @@ static void sg2044_msi_irq_compose_msi_msg(struct irq_d= ata *d, struct msi_msg *m =20 static struct irq_chip sg2044_msi_middle_irq_chip =3D { .name =3D "SG2044 MSI", + .irq_startup =3D irq_chip_startup_parent, + .irq_shutdown =3D irq_chip_shutdown_parent, .irq_ack =3D sg2044_msi_irq_ack, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, @@ -185,8 +189,10 @@ static const struct irq_domain_ops sg204x_msi_middle_d= omain_ops =3D { .select =3D msi_lib_irq_domain_select, }; =20 -#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ - MSI_FLAG_USE_DEF_CHIP_OPS) +#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ + MSI_FLAG_PCI_MSI_MASK_PARENT | \ + MSI_FLAG_PCI_MSI_STARTUP_PARENT) =20 #define SG2042_MSI_FLAGS_SUPPORTED MSI_GENERIC_FLAGS_MASK =20 @@ -200,10 +206,12 @@ static const struct msi_parent_ops sg2042_msi_parent_= ops =3D { .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 -#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ - MSI_FLAG_USE_DEF_CHIP_OPS) +#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ + MSI_FLAG_PCI_MSI_MASK_PARENT | \ + MSI_FLAG_PCI_MSI_STARTUP_PARENT) =20 -#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ +#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ MSI_FLAG_PCI_MSIX) =20 static const struct msi_parent_ops sg2044_msi_parent_ops =3D { --=20 2.50.1