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Wed, 13 Aug 2025 16:29:32 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Bjorn Helgaas , Marc Zyngier , Lorenzo Pieralisi , Shradha Gupta , Haiyang Zhang , Inochi Amaoto , Jonathan Cameron , Juergen Gross , Nicolin Chen , Jason Gunthorpe , Chen Wang Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH v2 1/4] genirq: Add irq_chip_(startup/shutdown)_parent() Date: Thu, 14 Aug 2025 07:28:31 +0800 Message-ID: <20250813232835.43458-2-inochiama@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250813232835.43458-1-inochiama@gmail.com> References: <20250813232835.43458-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the MSI controller on SG2044 uses PLIC as the underlying interrupt controller, it needs to call the irq_enable() and irq_disable() to startup/shutdown irqs. Otherwise, the MSI interrupt can not be startup correctly and will not respond any incoming interrupt. Introduce helper irq_chip_startup_parent() and irq_chip_shutdown_parent() to allow the interrupt controller to call the irq_startup() or irq_shutdown() of the parent interrupt chip. In case irq_startup() or irq_shutdown() is not implemented for the parent interrupt chip, which will fallback to irq_chip_enable_parent() or irq_chip_disable_parent(). Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto --- include/linux/irq.h | 2 ++ kernel/irq/chip.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index 1d6b606a81ef..890e1371f5d4 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -669,6 +669,8 @@ extern int irq_chip_set_parent_state(struct irq_data *d= ata, extern int irq_chip_get_parent_state(struct irq_data *data, enum irqchip_irq_state which, bool *state); +extern void irq_chip_shutdown_parent(struct irq_data *data); +extern unsigned int irq_chip_startup_parent(struct irq_data *data); extern void irq_chip_enable_parent(struct irq_data *data); extern void irq_chip_disable_parent(struct irq_data *data); extern void irq_chip_ack_parent(struct irq_data *data); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 0d0276378c70..3ffa0d80ddd1 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1259,6 +1259,43 @@ int irq_chip_get_parent_state(struct irq_data *data, } EXPORT_SYMBOL_GPL(irq_chip_get_parent_state); =20 +/** + * irq_chip_shutdown_parent - Shutdown the parent interrupt + * @data: Pointer to interrupt specific data + * + * Invokes the irq_shutdown() callback of the parent if available or falls + * back to irq_chip_disable_parent(). + */ +void irq_chip_shutdown_parent(struct irq_data *data) +{ + struct irq_data *parent =3D data->parent_data; + + if (parent->chip->irq_shutdown) + parent->chip->irq_shutdown(parent); + else + irq_chip_disable_parent(data); +} +EXPORT_SYMBOL_GPL(irq_chip_shutdown_parent); + +/** + * irq_chip_startup_parent - Startup the parent interrupt + * @data: Pointer to interrupt specific data + * + * Invokes the irq_startup() callback of the parent if available or falls + * back to irq_chip_enable_parent(). + */ +unsigned int irq_chip_startup_parent(struct irq_data *data) +{ + struct irq_data *parent =3D data->parent_data; + + if (parent->chip->irq_startup) + return parent->chip->irq_startup(parent); + + irq_chip_enable_parent(data); + return 0; +} +EXPORT_SYMBOL_GPL(irq_chip_startup_parent); + /** * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmas= k if * NULL) --=20 2.50.1 From nobody Fri Oct 3 21:53:30 2025 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 876303002AC; Wed, 13 Aug 2025 23:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755127782; cv=none; b=PDBZefmym5RW78I6Vo9K3EIrw5jEjfKcWh0M584UGz2EA1uv4tOGsXepuv20vqAKYzmkQ9pHE13WdGwgtL3pvCSoeuyNDtqfZWVXNVnB83I7h52iq0mvHq+x2MMr2Pu6mnmtygugFPC9aC8tFPTTe6Hr/FL8xxMNIQts12eQuF0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755127782; c=relaxed/simple; bh=QxOx1Yj7EIirHJxr469BHjrZhOL0k5PImCUybXK3Gf8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Wed, 13 Aug 2025 16:29:37 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Bjorn Helgaas , Marc Zyngier , Lorenzo Pieralisi , Shradha Gupta , Haiyang Zhang , Inochi Amaoto , Jonathan Cameron , Juergen Gross , Nicolin Chen , Jason Gunthorpe , Chen Wang Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH v2 2/4] PCI/MSI: Add startup/shutdown for per device domains Date: Thu, 14 Aug 2025 07:28:32 +0800 Message-ID: <20250813232835.43458-3-inochiama@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250813232835.43458-1-inochiama@gmail.com> References: <20250813232835.43458-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the RISC-V PLIC can not apply affinity setting without calling irq_enable(), it will make the interrupt unavailble when using as an underlying IRQ chip for MSI controller. Implement .irq_startup() and .irq_shutdown() for the PCI MSI and MSI-X templates. For chips that specify MSI_FLAG_PCI_MSI_STARTUP_PARENT, these startup and shutdown the parent as well, which allows the irq on the parent chip to be enabled if the irq is not enabled when allocating. This is necessary for the MSI controllers which use PLIC as underlying IRQ chip. Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto Acked-by: Bjorn Helgaas Reported-by: Linux Kernel Functional Testing Tested-by: Linux Kernel Functional Testing Tested-by: Nathan Chancellor --- drivers/pci/msi/irqdomain.c | 52 +++++++++++++++++++++++++++++++++++++ include/linux/msi.h | 2 ++ 2 files changed, 54 insertions(+) diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c index 0938ef7ebabf..e0a800f918e8 100644 --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -148,6 +148,23 @@ static void pci_device_domain_set_desc(msi_alloc_info_= t *arg, struct msi_desc *d arg->hwirq =3D desc->msi_index; } =20 +static void cond_shutdown_parent(struct irq_data *data) +{ + struct msi_domain_info *info =3D data->domain->host_data; + + if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) + irq_chip_shutdown_parent(data); +} + +static unsigned int cond_startup_parent(struct irq_data *data) +{ + struct msi_domain_info *info =3D data->domain->host_data; + + if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) + return irq_chip_startup_parent(data); + return 0; +} + static __always_inline void cond_mask_parent(struct irq_data *data) { struct msi_domain_info *info =3D data->domain->host_data; @@ -164,6 +181,23 @@ static __always_inline void cond_unmask_parent(struct = irq_data *data) irq_chip_unmask_parent(data); } =20 +static void pci_irq_shutdown_msi(struct irq_data *data) +{ + struct msi_desc *desc =3D irq_data_get_msi_desc(data); + + pci_msi_mask(desc, BIT(data->irq - desc->irq)); + cond_shutdown_parent(data); +} + +static unsigned int pci_irq_startup_msi(struct irq_data *data) +{ + struct msi_desc *desc =3D irq_data_get_msi_desc(data); + unsigned int ret =3D cond_startup_parent(data); + + pci_msi_unmask(desc, BIT(data->irq - desc->irq)); + return ret; +} + static void pci_irq_mask_msi(struct irq_data *data) { struct msi_desc *desc =3D irq_data_get_msi_desc(data); @@ -194,6 +228,8 @@ static void pci_irq_unmask_msi(struct irq_data *data) static const struct msi_domain_template pci_msi_template =3D { .chip =3D { .name =3D "PCI-MSI", + .irq_startup =3D pci_irq_startup_msi, + .irq_shutdown =3D pci_irq_shutdown_msi, .irq_mask =3D pci_irq_mask_msi, .irq_unmask =3D pci_irq_unmask_msi, .irq_write_msi_msg =3D pci_msi_domain_write_msg, @@ -210,6 +246,20 @@ static const struct msi_domain_template pci_msi_templa= te =3D { }, }; =20 +static void pci_irq_shutdown_msix(struct irq_data *data) +{ + pci_msix_mask(irq_data_get_msi_desc(data)); + cond_shutdown_parent(data); +} + +static unsigned int pci_irq_startup_msix(struct irq_data *data) +{ + unsigned int ret =3D cond_startup_parent(data); + + pci_msix_unmask(irq_data_get_msi_desc(data)); + return ret; +} + static void pci_irq_mask_msix(struct irq_data *data) { pci_msix_mask(irq_data_get_msi_desc(data)); @@ -234,6 +284,8 @@ EXPORT_SYMBOL_GPL(pci_msix_prepare_desc); static const struct msi_domain_template pci_msix_template =3D { .chip =3D { .name =3D "PCI-MSIX", + .irq_startup =3D pci_irq_startup_msix, + .irq_shutdown =3D pci_irq_shutdown_msix, .irq_mask =3D pci_irq_mask_msix, .irq_unmask =3D pci_irq_unmask_msix, .irq_write_msi_msg =3D pci_msi_domain_write_msg, diff --git a/include/linux/msi.h b/include/linux/msi.h index e5e86a8529fb..3111ba95fbde 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -568,6 +568,8 @@ enum { MSI_FLAG_PARENT_PM_DEV =3D (1 << 8), /* Support for parent mask/unmask */ MSI_FLAG_PCI_MSI_MASK_PARENT =3D (1 << 9), + /* Support for parent startup/shutdown */ + MSI_FLAG_PCI_MSI_STARTUP_PARENT =3D (1 << 10), =20 /* Mask for the generic functionality */ MSI_GENERIC_FLAGS_MASK =3D GENMASK(15, 0), --=20 2.50.1 From nobody Fri Oct 3 21:53:31 2025 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C852930E826; 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charset="utf-8" When using NVME on SG2044, the NVME always complains "I/O tag XXX (XXX) QID XX timeout, completion polled", which is caused by the broken handler of the sg2042-msi driver. As PLIC driver can only set affinity when enabling, the sg2042-msi does not properly handled affinity setting previously and enables irq in an unexpected executing path. Since the PCI template domain supports irq_startup()/irq_shutdown(), set irq_chip_[startup/shutdown]_parent() for irq_startup() and irq_shutdown(). So the irq can be started properly. Fixes: e96b93a97c90 ("irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interru= pt controller") Reported-by: Han Gao Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto --- drivers/irqchip/irq-sg2042-msi.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index bcfddc51bc6a..2fd4d94f9bd7 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -85,6 +85,8 @@ static void sg2042_msi_irq_compose_msi_msg(struct irq_dat= a *d, struct msi_msg *m =20 static const struct irq_chip sg2042_msi_middle_irq_chip =3D { .name =3D "SG2042 MSI", + .irq_startup =3D irq_chip_startup_parent, + .irq_shutdown =3D irq_chip_shutdown_parent, .irq_ack =3D sg2042_msi_irq_ack, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, @@ -114,6 +116,8 @@ static void sg2044_msi_irq_compose_msi_msg(struct irq_d= ata *d, struct msi_msg *m =20 static struct irq_chip sg2044_msi_middle_irq_chip =3D { .name =3D "SG2044 MSI", + .irq_startup =3D irq_chip_startup_parent, + .irq_shutdown =3D irq_chip_shutdown_parent, .irq_ack =3D sg2044_msi_irq_ack, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, @@ -185,8 +189,10 @@ static const struct irq_domain_ops sg204x_msi_middle_d= omain_ops =3D { .select =3D msi_lib_irq_domain_select, }; =20 -#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ - MSI_FLAG_USE_DEF_CHIP_OPS) +#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ + MSI_FLAG_PCI_MSI_MASK_PARENT | \ + MSI_FLAG_PCI_MSI_STARTUP_PARENT) =20 #define SG2042_MSI_FLAGS_SUPPORTED MSI_GENERIC_FLAGS_MASK =20 @@ -200,10 +206,12 @@ static const struct msi_parent_ops sg2042_msi_parent_= ops =3D { .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 -#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ - MSI_FLAG_USE_DEF_CHIP_OPS) +#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ + MSI_FLAG_PCI_MSI_MASK_PARENT | \ + MSI_FLAG_PCI_MSI_STARTUP_PARENT) =20 -#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ +#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ MSI_FLAG_PCI_MSIX) =20 static const struct msi_parent_ops sg2044_msi_parent_ops =3D { --=20 2.50.1 From nobody Fri Oct 3 21:53:31 2025 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A580C2FC880; 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Wed, 13 Aug 2025 16:29:50 -0700 (PDT) Received: from localhost ([2001:19f0:ac00:4eb8:5400:5ff:fe30:7df3]) by smtp.gmail.com with UTF8SMTPSA id 2adb3069b0e04-55b8898bf90sm5539497e87.26.2025.08.13.16.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Aug 2025 16:29:50 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Bjorn Helgaas , Marc Zyngier , Lorenzo Pieralisi , Shradha Gupta , Haiyang Zhang , Inochi Amaoto , Jonathan Cameron , Juergen Gross , Nicolin Chen , Jason Gunthorpe , Chen Wang Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH v2 4/4] irqchip/sg2042-msi: Set MSI_FLAG_MULTI_PCI_MSI flags for SG2044 Date: Thu, 14 Aug 2025 07:28:34 +0800 Message-ID: <20250813232835.43458-5-inochiama@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250813232835.43458-1-inochiama@gmail.com> References: <20250813232835.43458-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MSI controller on SG2044 has the ability to allocate multiple PCI MSI interrupts. So the PCIe controller driver can use this feature if it also supports multiple PCI MSI interrupts. Add MSI_FLAG_MULTI_PCI_MSI flag for the supported_flags of SG2044 msi_parent_ops so the PCIe controller driver can use this feature if it also supports this feature. Signed-off-by: Inochi Amaoto --- drivers/irqchip/irq-sg2042-msi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index 2fd4d94f9bd7..3b13dbbfdb51 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -212,6 +212,7 @@ static const struct msi_parent_ops sg2042_msi_parent_op= s =3D { MSI_FLAG_PCI_MSI_STARTUP_PARENT) =20 #define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_MULTI_PCI_MSI | \ MSI_FLAG_PCI_MSIX) =20 static const struct msi_parent_ops sg2044_msi_parent_ops =3D { --=20 2.50.1