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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50ae9bd89d7sm3933104173.59.2025.08.13.11.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Aug 2025 11:47:18 -0700 (PDT) From: Alex Elder To: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org Cc: dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, tglx@linutronix.de, johan+linaro@kernel.org, thippeswamy.havalige@amd.com, namcao@linutronix.de, mayank.rana@oss.qualcomm.com, shradha.t@samsung.com, inochiama@gmail.com, quic_schintav@quicinc.com, fan.ni@samsung.com, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] riscv: dts: spacemit: PCIe and PHY-related updates Date: Wed, 13 Aug 2025 13:47:00 -0500 Message-ID: <20250813184701.2444372-7-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250813184701.2444372-1-elder@riscstar.com> References: <20250813184701.2444372-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 board. The combo PHY is used for USB on this board, and that will be enabled when USB 3 support is accepted. Signed-off-by: Alex Elder --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 28 +++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 169 ++++++++++++++++++ 3 files changed, 230 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index fe22c747c5012..1c75e38b1fab9 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -40,6 +40,34 @@ &emmc { status =3D "okay"; }; =20 +&combo_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_3_cfg>; + status =3D "okay"; +}; + +&pcie1_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_3_cfg>; + status =3D "okay"; +}; + +&pcie2_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_4_cfg>; + status =3D "okay"; +}; + +&pcie1 { + phys =3D <&pcie1_phy>; + status =3D "okay"; +}; + +&pcie2 { + phys =3D <&pcie2_phy>; + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot= /dts/spacemit/k1-pinctrl.dtsi index 3810557374228..e7dbecd7389b7 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -21,6 +21,39 @@ uart0-2-pins { }; }; =20 + pcie0_3_cfg: pcie0-3-cfg { + pcie0-3-pins { + pinmux =3D , /* PERST# */ + , /* WAKE */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + + pcie1_3_cfg: pcie1-3-cfg { + pcie1-3-pins { + pinmux =3D , /* PERST# */ + , /* WAKE */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + + pcie2_4_cfg: pcie2-4-cfg { + pcie2-4-pins { + pinmux =3D , /* PERST# */ + , /* WAKE */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + pwm14_1_cfg: pwm14-1-cfg { pwm14-1-pins { pinmux =3D ; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index abde8bb07c95c..6343f6e95284d 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -4,6 +4,8 @@ */ =20 #include +#include +#include =20 /dts-v1/; / { @@ -358,6 +360,42 @@ syscon_rcpu2: system-controller@c0888000 { #reset-cells =3D <1>; }; =20 + combo_phy: phy@c0b10000 { + compatible =3D "spacemit,k1-combo-phy"; + reg =3D <0x0 0xc0b10000 0x0 0x1000>; + clocks =3D <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>, + <&syscon_apmu RESET_PCIE0_GLOBAL>; + reset-names =3D "dbi", + "mstr", + "slv", + "global"; + spacemit,syscon-pmu =3D <&syscon_apmu>; + #phy-cells =3D <1>; + status =3D "disabled"; + }; + + pcie1_phy: phy@c0c10000 { + compatible =3D "spacemit,k1-pcie-phy"; + reg =3D <0x0 0xc0c10000 0x0 0x1000>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + pcie2_phy: phy@c0d10000 { + compatible =3D "spacemit,k1-pcie-phy"; + reg =3D <0x0 0xc0d10000 0x0 0x1000>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + syscon_apbc: system-controller@d4015000 { compatible =3D "spacemit,k1-syscon-apbc"; reg =3D <0x0 0xd4015000 0x0 0x1000>; @@ -814,6 +852,137 @@ pcie-bus { #size-cells =3D <2>; dma-ranges =3D <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; + pcie0: pcie@ca000000 { + compatible =3D "spacemit,k1-pcie-rc"; + reg =3D <0x0 0xca000000 0x0 0x00001000>, + <0x0 0xca300000 0x0 0x0001ff24>, + <0x0 0x8f000000 0x0 0x00002000>, + <0x0 0xc0b20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + spacemit,syscon-pmu =3D <&syscon_apmu 0x03cc>; + + ranges =3D <0x01000000 0x0 0x8f002000 0 0x8f002000 0x0 0x100000>, + <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x0f000000>; + + clocks =3D <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + + resets =3D <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>, + <&syscon_apmu RESET_PCIE0_GLOBAL>; + reset-names =3D "dbi", + "mstr", + "slv", + "global"; + + interrupts-extended =3D <&plic 141>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + max-link-speed =3D <2>; + bus-range =3D <0x00 0xff>; + num-viewport =3D <8>; + + status =3D "disabled"; + }; + + pcie1: pcie@ca400000 { + compatible =3D "spacemit,k1-pcie-rc"; + reg =3D <0x0 0xca400000 0x0 0x00001000>, + <0x0 0xca700000 0x0 0x0001ff24>, + <0x0 0x9f000000 0x0 0x00002000>, + <0x0 0xc0c20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + spacemit,syscon-pmu =3D <&syscon_apmu 0x3d4>; + + ranges =3D <0x01000000 0x0 0x9f002000 0 0x9f002000 0x0 0x100000>, + <0x02000000 0x0 0x90000000 0 0x90000000 0x0 0x0f000000>; + clocks =3D <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + + resets =3D <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>, + <&syscon_apmu RESET_PCIE1_GLOBAL>; + reset-names =3D "dbi", + "mstr", + "slv", + "global"; + + interrupts-extended =3D <&plic 142>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + max-link-speed =3D <2>; + bus-range =3D <0x00 0xff>; + num-viewport =3D <8>; + + status =3D "disabled"; + }; + + pcie2: pcie@ca800000 { + compatible =3D "spacemit,k1-pcie-rc"; + reg =3D <0x0 0xca800000 0x0 0x00001000>, + <0x0 0xcab00000 0x0 0x0001ff24>, + <0x0 0xb7000000 0x0 0x00002000>, + <0x0 0xc0d20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + + spacemit,syscon-pmu =3D <&syscon_apmu 0x3dc>; + + ranges =3D <0x01000000 0x0 0xb7002000 0 0xb7002000 0x0 0x100000>, + <0x42000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000>, + <0x02000000 0x0 0xb0000000 0 0xb0000000 0x0 0x7000000>; + clocks =3D <&syscon_apmu CLK_PCIE2_DBI>, + <&syscon_apmu CLK_PCIE2_MASTER>, + <&syscon_apmu CLK_PCIE2_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + + resets =3D <&syscon_apmu RESET_PCIE2_DBI>, + <&syscon_apmu RESET_PCIE2_MASTER>, + <&syscon_apmu RESET_PCIE2_SLAVE>, + <&syscon_apmu RESET_PCIE2_GLOBAL>; + reset-names =3D "dbi", + "mstr", + "slv", + "global"; + + interrupts-extended =3D <&plic 143>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + max-link-speed =3D <2>; + bus-range =3D <0x00 0xff>; + num-viewport =3D <8>; + + status =3D "disabled"; + }; }; =20 storage-bus { --=20 2.48.1