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Bae" To: x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, colinmitchell@google.com, chao.gao@intel.com, abusse@amazon.de, chang.seok.bae@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/6] x86/microcode/intel: Establish staging control logic Date: Wed, 13 Aug 2025 10:26:45 -0700 Message-ID: <20250813172649.15474-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250813172649.15474-1-chang.seok.bae@intel.com> References: <20250409232713.4536-1-chang.seok.bae@intel.com> <20250813172649.15474-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When microcode staging is initiated, operations are carried out through an MMIO interface. Each package has a unique interface specified by the IA32_MCU_STAGING_MBOX_ADDR MSR, which maps to a set of 32-bit registers. Prepare staging with the following steps: 1. Ensure the microcode image is 32-bit aligned to match the MMIO register size. 2. Identify each MMIO interface based on its per-package scope. 3. Invoke the staging function for each identified interface, which will be implemented separately. Also, define cpu_primary_thread_mask for the CONFIG_SMP=3Dn case, allowing consistent use when narrowing down primary threads to locate the per-package interface. Suggested-by: Thomas Gleixner Signed-off-by: Chang S. Bae Tested-by: Anselm Busse Link: https://lore.kernel.org/all/871pznq229.ffs@tglx --- V2 -> V3: * Remove a global variable and adjust stage_microcode() (Dave). * Simplify for_each_cpu() loop control code * Handle rdmsrl_on_cpu() return code explicitly (Chao) V1 -> V2: * Adjust to reference the staging_state struct. * Add lockdep_assert_cpus_held() (Boris) --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/microcode/intel.c | 50 +++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index b65c3ba5fa14..0356155f9264 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -913,6 +913,8 @@ #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b =20 +#define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5 + /* Intel SGX Launch Enclave Public Key Hash MSRs */ #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index 6c79ee7c0957..91b5fc44ca62 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -235,6 +235,7 @@ static inline bool topology_is_primary_thread(unsigned = int cpu) static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return = 0; } static inline int topology_max_smt_threads(void) { return 1; } static inline unsigned int topology_amd_nodes_per_pkg(void) { return 1; } +#define cpu_primary_thread_mask cpu_none_mask #endif /* !CONFIG_SMP */ =20 static inline void arch_fix_phys_package_id(int num, u32 slot) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 371ca6eac00e..468c4d3d5d66 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -299,6 +299,55 @@ static __init struct microcode_intel *scan_microcode(v= oid *data, size_t size, return size ? NULL : patch; } =20 +/* + * Handle the staging process using the mailbox MMIO interface. + * Return the result state. + */ +static enum ucode_state do_stage(u64 mmio_pa) +{ + pr_debug_once("Staging implementation is pending.\n"); + return UCODE_ERROR; +} + +static void stage_microcode(void) +{ + unsigned int pkg_id =3D UINT_MAX; + enum ucode_state ret; + int cpu, err; + u64 mmio_pa; + + if (!IS_ALIGNED(get_totalsize(&ucode_patch_late->hdr), sizeof(u32))) + return; + + lockdep_assert_cpus_held(); + + /* + * The MMIO address is unique per package, and all the SMT + * primary threads are online here. Find each MMIO space by + * their package ids to avoid duplicate staging. + */ + for_each_cpu(cpu, cpu_primary_thread_mask) { + if (topology_logical_package_id(cpu) =3D=3D pkg_id) + continue; + pkg_id =3D topology_logical_package_id(cpu); + + err =3D rdmsrl_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &mmio_pa); + if (WARN_ON_ONCE(err)) + return; + + ret =3D do_stage(mmio_pa); + if (ret !=3D UCODE_OK) { + pr_err("Error: staging failed with %s for CPU%d at package %u.\n", + ret =3D=3D UCODE_TIMEOUT ? "timeout" : "error state", + cpu, pkg_id); + return; + } + } + + pr_info("Staging of patch revision 0x%x succeeded.\n", + ((struct microcode_header_intel *)ucode_patch_late)->rev); +} + static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, struct microcode_intel *mc, u32 *cur_rev) @@ -627,6 +676,7 @@ static struct microcode_ops microcode_intel_ops =3D { .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode_late, .finalize_late_load =3D finalize_late_load, + .stage_microcode =3D stage_microcode, .use_nmi =3D IS_ENABLED(CONFIG_X86_64), }; =20 --=20 2.48.1