From nobody Sat Oct 4 19:18:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 039F7287247 for ; Wed, 13 Aug 2025 17:27:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106028; cv=none; b=bQiXK626yCjbtkG+62xO1Kb3XV44b/a08I/hfSSzgQQ+ZhUywQgpDsjccFzhnWyNfqiuIr2JZgBqx96fkkje8W+VpDYlClqhNw0qmVeN8KTqTXB51qJU0LyLb8RT+3pLamsoX8OSR1FuKmv0JV1dX75+mGVtayOQ0LrNFj0xhPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106028; c=relaxed/simple; bh=YBtgJINRq9CWupVyEhQDXVWYVFuj92uvEpfEeIJvJww=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sdSPzI78DDsnEBEBQLKxiqUZLLyaHxoydzrUy1uaOaoNYmjD96RHEjRUCw5RR1Gvn7fjMf4v900xi5yd/y9MoXZ2LdRrLHeUUyWLMKPt6E58kHKkbTrfKlk90WppuopbmBDYvGvZ98xYCT6UgV6PmFWnjUgMmNmiAEHCGVBqGVk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JhzNoXLe; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JhzNoXLe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755106028; x=1786642028; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YBtgJINRq9CWupVyEhQDXVWYVFuj92uvEpfEeIJvJww=; b=JhzNoXLeyOm4mEpcN4Ozt8u3jHDGRCAf8lEV1NpHsOXXBRgG16h5os3Q 70vMzpHvfsSyFC+liv+lMLgBnoJLPnco9fLrHhz1HNgbnu7nOPe9pbr+5 I7C6DcP9we+fXB8e7cN8tKcojvKG2htY7OEuIUBTLIwpHMgrl48vlPvF0 LYNbhGU2XrMyahcyvG1fqypfxRyou0N/09ib0qbTqKzg+bJLrqDTMEQdG 2ZGaejDUOWeVsWJYbFHX/7OREfi1AfH0IuBOFh5RDLVQY6k5TastKAN4R LivJpIxW+LzQ+jVxbYZdMc6fRlb7SWM4b9HqPGFojIoiW2R8dQbxoX2BB w==; X-CSE-ConnectionGUID: OHXsCw4QQ+uS16sm0M18TQ== X-CSE-MsgGUID: y/soZd0rRz6fLyTOKhLnCQ== X-IronPort-AV: E=McAfee;i="6800,10657,11520"; a="61255205" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="61255205" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2025 10:27:07 -0700 X-CSE-ConnectionGUID: JqHXX5nXTUu6lUSrNdDDRg== X-CSE-MsgGUID: IMnTRMzIQOWqF5lPvpnIbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="167329701" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.193]) by fmviesa010.fm.intel.com with ESMTP; 13 Aug 2025 10:27:06 -0700 From: "Chang S. Bae" To: x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, colinmitchell@google.com, chao.gao@intel.com, abusse@amazon.de, chang.seok.bae@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/6] x86/microcode: Introduce staging step to reduce late-loading time Date: Wed, 13 Aug 2025 10:26:44 -0700 Message-ID: <20250813172649.15474-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250813172649.15474-1-chang.seok.bae@intel.com> References: <20250409232713.4536-1-chang.seok.bae@intel.com> <20250813172649.15474-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As microcode patch sizes continue to grow, late-loading latency spikes can lead to timeouts and disruptions in running workloads. This trend of increasing patch sizes is expected to continue, so a foundational solution is needed to address the issue. To mitigate the problem, a new staging feature is introduced. This option processes most of the microcode update (excluding activation) on a non-critical path, allowing CPUs to remain operational during the majority of the update. By offloading work from the critical path, staging can significantly reduces latency spikes. Integrate staging as a preparatory step in late-loading. Introduce a new callback for staging, which is invoked at the beginning of load_late_stop_cpus(), before CPUs enter the rendezvous phase. Staging follows an opportunistic model: * If successful, it reduces CPU rendezvous time * Even though it fails, the process falls back to the legacy path to finish the loading process but with potentially higher latency. Extend struct microcode_ops to incorporate staging properties, which will be implemented in the vendor code separately. Signed-off-by: Chang S. Bae Tested-by: Anselm Busse Reviewed-by: Chao Gao --- There were discussions about whether staging success should be enforced by a configurable option. That topic is identified as follow-up work, separate from this series. https://lore.kernel.org/lkml/54308373-7867-4b76-be34-63730953f83c@intel= .com/ V1 -> V2: * Move invocation inside of load_late_stop_cpus() (Boris) * Add more note about staging (Dave) --- arch/x86/kernel/cpu/microcode/core.c | 11 +++++++++++ arch/x86/kernel/cpu/microcode/internal.h | 4 +++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index b92e09a87c69..34e569ee1db2 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -552,6 +552,17 @@ static int load_late_stop_cpus(bool is_safe) pr_err("You should switch to early loading, if possible.\n"); } =20 + /* + * Pre-load the microcode image into a staging device. This + * process is preemptible and does not require stopping CPUs. + * Successful staging simplifies the subsequent late-loading + * process, reducing rendezvous time. + * + * Even if the transfer fails, the update will proceed as usual. + */ + if (microcode_ops->use_staging) + microcode_ops->stage_microcode(); + atomic_set(&late_cpus_in, num_online_cpus()); atomic_set(&offline_in_nmi, 0); loops_per_usec =3D loops_per_jiffy / (TICK_NSEC / 1000); diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 50a9702ae4e2..adf02ebbf7a3 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,10 +31,12 @@ struct microcode_ops { * See also the "Synchronization" section in microcode_core.c. */ enum ucode_state (*apply_microcode)(int cpu); + void (*stage_microcode)(void); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); void (*finalize_late_load)(int result); unsigned int nmi_safe : 1, - use_nmi : 1; + use_nmi : 1, + use_staging : 1; }; =20 struct early_load_data { --=20 2.48.1 From nobody Sat Oct 4 19:18:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A41828850C for ; Wed, 13 Aug 2025 17:27:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106032; cv=none; b=s5EPDVb7e6GuIqOnGQKbWN8ZlYKqfSfler9xnM7YVgvBDcGtLYKKNDocUMa+TZbxKdIAcsgJUVW8kD5ueOI13tGBgzziJDHQdEcHkx5FzXU3YuzPIo7fzG/ldzdfcVbF+acVIVdd5yfhKCZ7+6FTeUqN5SfMlqfrCh5NDm4+4QE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106032; c=relaxed/simple; bh=pddAVofjUvwztbLAKX/AQSVKNcKJ0FW0t5mvkuaRnyg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F0WTnZQqcJ0kXdzSMdQVbBh3CR+/0p2oJ6OZey/qcu+C/LRltg9TSCUGUbalB6g8BEIhOURutv9UUIM+++FsV/GtjT4FqMQ/uXbLv/rCiFj09GL50oDXGHr+4LbPKwdO2E9S6i1oLk6Z7jHjT1Em7OhGzhN7W/JXzsxLd4DSn7s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q6Nd2FLo; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q6Nd2FLo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755106031; x=1786642031; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pddAVofjUvwztbLAKX/AQSVKNcKJ0FW0t5mvkuaRnyg=; b=Q6Nd2FLoXNL2uf+qm7Tn6XYN7jNgggJ9HjGoKDWuYtImG1QQ++w5R2D8 l4/DOyj4uZpvG6npMSxgWKvf2jOf7pBoEShdWNTrTwuwksKVpE3cdRmF9 MkJDsGqiR7ayGIJZpKcgnahkqosYWSXnXCz8lQCmbYAu2bNC3xK4lF6GX LHY1i8ts6hjHNmIv0/pd+iki4EFnSkEyDpd4YE3DLmdWtT73xOl3b5CJm 7o8g5fScudVcmUACvRc6y8QhaeSiQk1/MtZ/vZew7ogOiFYslNI1ElH3Y qKy7E27UvRGAUhrxFYxoveWe2uXzKB2PVfWMiEHyRT5pJio6pWhH2VpYF Q==; X-CSE-ConnectionGUID: tYuP4tVxTPuLbqgCGG+zPA== X-CSE-MsgGUID: E7kDgq3dTCKab1YBund/OQ== X-IronPort-AV: E=McAfee;i="6800,10657,11520"; a="61255211" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="61255211" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2025 10:27:11 -0700 X-CSE-ConnectionGUID: Y8Roc2FKQ8SN64N+OVj9Fg== X-CSE-MsgGUID: yO+RCJ25SWuo87R3+6CZSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="167329705" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.193]) by fmviesa010.fm.intel.com with ESMTP; 13 Aug 2025 10:27:09 -0700 From: "Chang S. Bae" To: x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, colinmitchell@google.com, chao.gao@intel.com, abusse@amazon.de, chang.seok.bae@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/6] x86/microcode/intel: Establish staging control logic Date: Wed, 13 Aug 2025 10:26:45 -0700 Message-ID: <20250813172649.15474-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250813172649.15474-1-chang.seok.bae@intel.com> References: <20250409232713.4536-1-chang.seok.bae@intel.com> <20250813172649.15474-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When microcode staging is initiated, operations are carried out through an MMIO interface. Each package has a unique interface specified by the IA32_MCU_STAGING_MBOX_ADDR MSR, which maps to a set of 32-bit registers. Prepare staging with the following steps: 1. Ensure the microcode image is 32-bit aligned to match the MMIO register size. 2. Identify each MMIO interface based on its per-package scope. 3. Invoke the staging function for each identified interface, which will be implemented separately. Also, define cpu_primary_thread_mask for the CONFIG_SMP=3Dn case, allowing consistent use when narrowing down primary threads to locate the per-package interface. Suggested-by: Thomas Gleixner Signed-off-by: Chang S. Bae Tested-by: Anselm Busse Link: https://lore.kernel.org/all/871pznq229.ffs@tglx --- V2 -> V3: * Remove a global variable and adjust stage_microcode() (Dave). * Simplify for_each_cpu() loop control code * Handle rdmsrl_on_cpu() return code explicitly (Chao) V1 -> V2: * Adjust to reference the staging_state struct. * Add lockdep_assert_cpus_held() (Boris) --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/microcode/intel.c | 50 +++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index b65c3ba5fa14..0356155f9264 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -913,6 +913,8 @@ #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b =20 +#define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5 + /* Intel SGX Launch Enclave Public Key Hash MSRs */ #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index 6c79ee7c0957..91b5fc44ca62 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -235,6 +235,7 @@ static inline bool topology_is_primary_thread(unsigned = int cpu) static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return = 0; } static inline int topology_max_smt_threads(void) { return 1; } static inline unsigned int topology_amd_nodes_per_pkg(void) { return 1; } +#define cpu_primary_thread_mask cpu_none_mask #endif /* !CONFIG_SMP */ =20 static inline void arch_fix_phys_package_id(int num, u32 slot) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 371ca6eac00e..468c4d3d5d66 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -299,6 +299,55 @@ static __init struct microcode_intel *scan_microcode(v= oid *data, size_t size, return size ? NULL : patch; } =20 +/* + * Handle the staging process using the mailbox MMIO interface. + * Return the result state. + */ +static enum ucode_state do_stage(u64 mmio_pa) +{ + pr_debug_once("Staging implementation is pending.\n"); + return UCODE_ERROR; +} + +static void stage_microcode(void) +{ + unsigned int pkg_id =3D UINT_MAX; + enum ucode_state ret; + int cpu, err; + u64 mmio_pa; + + if (!IS_ALIGNED(get_totalsize(&ucode_patch_late->hdr), sizeof(u32))) + return; + + lockdep_assert_cpus_held(); + + /* + * The MMIO address is unique per package, and all the SMT + * primary threads are online here. Find each MMIO space by + * their package ids to avoid duplicate staging. + */ + for_each_cpu(cpu, cpu_primary_thread_mask) { + if (topology_logical_package_id(cpu) =3D=3D pkg_id) + continue; + pkg_id =3D topology_logical_package_id(cpu); + + err =3D rdmsrl_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &mmio_pa); + if (WARN_ON_ONCE(err)) + return; + + ret =3D do_stage(mmio_pa); + if (ret !=3D UCODE_OK) { + pr_err("Error: staging failed with %s for CPU%d at package %u.\n", + ret =3D=3D UCODE_TIMEOUT ? "timeout" : "error state", + cpu, pkg_id); + return; + } + } + + pr_info("Staging of patch revision 0x%x succeeded.\n", + ((struct microcode_header_intel *)ucode_patch_late)->rev); +} + static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, struct microcode_intel *mc, u32 *cur_rev) @@ -627,6 +676,7 @@ static struct microcode_ops microcode_intel_ops =3D { .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode_late, .finalize_late_load =3D finalize_late_load, + .stage_microcode =3D stage_microcode, .use_nmi =3D IS_ENABLED(CONFIG_X86_64), }; =20 --=20 2.48.1 From nobody Sat Oct 4 19:18:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5283288514 for ; Wed, 13 Aug 2025 17:27:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106034; cv=none; b=DI2sdPr+Pi1BN39ZuuOIlFfNXhKpIiyp+HJ1oNihujt3SCDdAfXdYGK0w6A2R0dVZN1xJJOe5ZnJEDutyUXsJ6m7aVs4ilDHNdVEzAKi5HGjvAWd42IviyMjHBMUrgahEo1HxoL1R4rb6ZgmhU6KrWp3PsBrQuyjpXSraza7k9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106034; c=relaxed/simple; bh=bfbBVGoL1hUlUhbhKKduZgkj0HMRd8m5y/Epw1ScV7s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mLEJW8Lgj3fpOVlhWLrT5VM0dkrQN4tbeS/EhXVX713iDHvsa+DIRiYFf9W3nKTa2dPnl9tlh/IaPssxkXpJWLsRXPJ5FarhTBE3HLWqPP9xBwtOLwUBM4gEfWGt5WMtprAeUyE1BDpIqmYhhBdjg7iW8cpSCQTwpYvtlbxUPQk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gyKH0Tko; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gyKH0Tko" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755106033; x=1786642033; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bfbBVGoL1hUlUhbhKKduZgkj0HMRd8m5y/Epw1ScV7s=; b=gyKH0TkoHhyDV3XK3DuVrkXnJDup4e4LVnSkrMtqnCjrdAfFSGxqPHsJ LtU3reFF2kzY//aFl8hs4T0xFuWj+T3o3gnLEoHym2pg3JWR0/wDTpyaD KgESjXSl1MMzeUqEl02hfAi2DsFfNU6gtzAGCx89Dzryqsm1ghtMpGq6V Kml6Td784uSxz+ztCVP1gby57It4piR9D4SLMILTqOUDiuTK1D8R2AZI6 FCjf+DeFpG86UT7NJmE4pPlqx2s8d8UOkf9wgvTtXZllbgXGXCZ1b1270 z8f9Hf5hrYUzUL+aCh9SAmFIZ9P7Lejbp3KvLb1i75xjSu/vzXyH/F2Yv A==; X-CSE-ConnectionGUID: j6Da0a80RB+r01GI9lta8A== X-CSE-MsgGUID: CpYt9RQoTGyqa70LHJiW1w== X-IronPort-AV: E=McAfee;i="6800,10657,11520"; a="61255227" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="61255227" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2025 10:27:13 -0700 X-CSE-ConnectionGUID: 5vgHypc3T6qobLCqFJI75A== X-CSE-MsgGUID: WRebu1ZQSmiQb6Y1qxYkJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="167329709" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.193]) by fmviesa010.fm.intel.com with ESMTP; 13 Aug 2025 10:27:12 -0700 From: "Chang S. Bae" To: x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, colinmitchell@google.com, chao.gao@intel.com, abusse@amazon.de, chang.seok.bae@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/6] x86/microcode/intel: Define staging state struct Date: Wed, 13 Aug 2025 10:26:46 -0700 Message-ID: <20250813172649.15474-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250813172649.15474-1-chang.seok.bae@intel.com> References: <20250409232713.4536-1-chang.seok.bae@intel.com> <20250813172649.15474-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To facilitate a structured staging handler, a set of functions will be introduced. Define staging_state struct to simplify function prototypes by consolidating relevant data, instead of passing multiple local variables. Signed-off-by: Chang S. Bae Tested-by: Anselm Busse --- V1 -> V2: New patch Prior to V2, local variables were used to track state values, with the intention of improving readability by explicitly passing them between functions. However, given feedbacks, introducing a dedicated data structure looks to provide a benefit by simplifying the main loop. --- arch/x86/kernel/cpu/microcode/intel.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 468c4d3d5d66..36b426a90844 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -54,6 +54,27 @@ struct extended_sigtable { struct extended_signature sigs[]; }; =20 +/** + * struct staging_state - Tracks the current staging process state + * + * @mmio_base: MMIO base address for staging + * @ucode_ptr: Pointer to the microcode image + * @ucode_len: Total size of the microcode image + * @chunk_size: Size of each data piece + * @bytes_sent: Total bytes transmitted so far + * @offset: Current offset in the microcode image + * @state: Current state of the staging process + */ +struct staging_state { + void __iomem *mmio_base; + void *ucode_ptr; + unsigned int ucode_len; + unsigned int chunk_size; + unsigned int bytes_sent; + unsigned int offset; + enum ucode_state state; +}; + #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) #define EXT_HEADER_SIZE (sizeof(struct extended_sigtable)) #define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature)) --=20 2.48.1 From nobody Sat Oct 4 19:18:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D19728C5D9 for ; Wed, 13 Aug 2025 17:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106036; cv=none; b=miMS3nY1qjntPg77uku2+53HgN6git3PwubTZBR0FZFS6wTt0vEUFgZc/0RTrmXeekimel3ecy9dbyN/xbkYegX6HN6R1qf2VzhSVuZgBY7AMk998fbhT81Lwq8Rb/S88pMZTWCF+FkGdCfJ8Fb3OsQKt9tAZcO/kGGFT8ffoUc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106036; c=relaxed/simple; bh=ZrZJtVEmXZ9Mr8fQMBIZygqxXvpJUmoC9YWZOeHW0Qs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oUmYKbcdIr73wGhcQWBZ5nwjRLTL3XMBNLFhAhGv4ITe88+Oq9y9+wrAso6MWzjH+SPuu43pMZbmFrnMJMOqaXbHyoLoBNHYsJw40PPsm1UrZVBiX89aYznc1WGJEXLcSUq7mLezbzx/LhT6fC7aJem8Fcm51K7NoUIf7pvqRLI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LJYi9qUK; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LJYi9qUK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755106035; x=1786642035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZrZJtVEmXZ9Mr8fQMBIZygqxXvpJUmoC9YWZOeHW0Qs=; b=LJYi9qUKqTXEU8yTUiuGJRKGIvK/AMHwfsxcYLfqszecdJtTkqN/ObbF QOLECX2aXNVjTpyJpjbxOJDYJKhnFPfo8gurwtFyPjozC08uJfGo56Uo7 UkR2MKFATrXqwxGDR0wElMnhH++uKzB7bq2XuvDZHv8Q4YeVXLbSlqsLn RzEv6LC3wogMgPYKG0Zl6jCPmsg4oT4XqXVgQIHAffCf0bdcdES1fKNRj so8BqjdwND6vSgTsfBXb8Ey6NPfEX31m3Nzh9mtRYScXcDR/Q1VYXW/by AXodwL+C8zNYOYsPCakTtDo9psC+ld68rLFx4pGC+O2OdiiwCWITJH4l5 Q==; X-CSE-ConnectionGUID: yoID1EYIQvm0Z3qZ02+J3Q== X-CSE-MsgGUID: vRqGdS8TRm2/uW7o9yYORQ== X-IronPort-AV: E=McAfee;i="6800,10657,11520"; a="61255238" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="61255238" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2025 10:27:15 -0700 X-CSE-ConnectionGUID: WmRKfmfPTBm4d17DnxJiYg== X-CSE-MsgGUID: 0ajkj4qvSZ+Mcl5CP3TZ1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="167329712" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.193]) by fmviesa010.fm.intel.com with ESMTP; 13 Aug 2025 10:27:14 -0700 From: "Chang S. Bae" To: x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, colinmitchell@google.com, chao.gao@intel.com, abusse@amazon.de, chang.seok.bae@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/6] x86/microcode/intel: Implement staging handler Date: Wed, 13 Aug 2025 10:26:47 -0700 Message-ID: <20250813172649.15474-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250813172649.15474-1-chang.seok.bae@intel.com> References: <20250409232713.4536-1-chang.seok.bae@intel.com> <20250813172649.15474-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previously, per-package staging invocations and their associated state data were established. The next step is to implement the actual staging handler according to the specified protocol. Below are key aspects to note: (a) Each staging process must begin by resetting the staging hardware. (b) The staging hardware processes up to a page-sized chunk of the microcode image per iteration, requiring software to submit data incrementally. (c) Once a data chunk is processed, the hardware responds with an offset in the image for the next chunk. (d) The offset may indicate completion or request retransmission of an already transferred chunk. As long as the total transferred data remains within the predefined limit (twice the image size), retransmissions should be acceptable. With that, incorporate these code sequences to the staging handler: 1. Initialization: Map the MMIO space via ioremap(). Reset the staging hardware and initialize software state, ensuring a fresh staging process aligned with (a). 2. Processing Loop: Introduce a loop iterating over data chunk, following (b), with proper termination conditions established from (d) -- stop staging when the hardware signals completion, or if the total transmitted data exceeds the predefined limit. 3. Loop Body: Finally, compose the loop body with two steps -- transmitting a data chunk and retrieving the next offset from the hardware response, aligning with (b) and (c). Since data transmission and mailbox format handling require additional details, they are implemented separately in next changes. Signed-off-by: Chang S. Bae Tested-by: Anselm Busse --- V2 -> V3: * Rework code to eliminate global variables (Dave) * Remove redundant variable resets (Chao) V1 -> V2: * Re-write the changelog for clarity (Dave). * Move staging handling code into intel.c (Boris). * Add extensive comments to clarify staging logic and hardware interactions, along with function renaming (Dave). --- arch/x86/kernel/cpu/microcode/intel.c | 120 +++++++++++++++++++++++++- 1 file changed, 116 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 36b426a90844..3eb3331c5012 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include =20 #include #include @@ -33,6 +35,29 @@ static const char ucode_path[] =3D "kernel/x86/microcode= /GenuineIntel.bin"; =20 #define UCODE_BSP_LOADED ((struct microcode_intel *)0x1UL) =20 +/* Defines for the microcode staging mailbox interface */ + +#define MBOX_REG_NUM 4 +#define MBOX_REG_SIZE sizeof(u32) + +#define MBOX_CONTROL_OFFSET 0x0 +#define MBOX_STATUS_OFFSET 0x4 + +#define MASK_MBOX_CTRL_ABORT BIT(0) + +/* + * Each microcode image is divided into chunks, each at most + * MBOX_XACTION_SIZE in size. A 10-chunk image would typically require + * 10 transactions. However, the hardware managing the mailbox has + * limited resources and may not cache the entire image, potentially + * requesting the same chunk multiple times. + * + * To accommodate this behavior, allow up to twice the expected number of + * transactions (i.e., a 10-chunk image can take up to 20 attempts). + */ +#define MBOX_XACTION_SIZE PAGE_SIZE +#define MBOX_XACTION_MAX(imgsz) ((imgsz) * 2) + /* Current microcode patch used in early patching on the APs. */ static struct microcode_intel *ucode_patch_va __read_mostly; static struct microcode_intel *ucode_patch_late __read_mostly; @@ -321,13 +346,100 @@ static __init struct microcode_intel *scan_microcode= (void *data, size_t size, } =20 /* - * Handle the staging process using the mailbox MMIO interface. - * Return the result state. + * Prepare for a new microcode transfer by resetting hardware and + * configuring microcode image info. + */ +static void init_stage(struct staging_state *ss) +{ + ss->ucode_ptr =3D ucode_patch_late; + ss->ucode_len =3D get_totalsize(&ucode_patch_late->hdr); + + /* + * Abort any ongoing process, effectively resetting the device. + * Unlike regular mailbox data processing requests, this + * operation does not require a status check. + */ + writel(MASK_MBOX_CTRL_ABORT, ss->mmio_base + MBOX_CONTROL_OFFSET); +} + +/* + * Check if the staging process has completed. The hardware signals + * completion by setting a unique end offset. + */ +static inline bool is_stage_complete(unsigned int offset) +{ + return offset =3D=3D UINT_MAX; +} + +/* + * Determine if the next data chunk can be sent. Each chunk is typically + * one page unless the remaining data is smaller. If the total + * transmitted data exceeds the defined limit, a timeout occurs. + */ +static bool can_send_next_chunk(struct staging_state *ss) +{ + WARN_ON_ONCE(ss->ucode_len < ss->offset); + ss->chunk_size =3D min(MBOX_XACTION_SIZE, ss->ucode_len - ss->offset); + + if (ss->bytes_sent + ss->chunk_size > MBOX_XACTION_MAX(ss->ucode_len)) { + ss->state =3D UCODE_TIMEOUT; + return false; + } + return true; +} + +/* + * Transmit a chunk of the microcode image to the hardware. + * Return true if the chunk is processed successfully. + */ +static bool send_data_chunk(struct staging_state *ss) +{ + pr_debug_once("Staging mailbox loading code needs to be implemented.\n"); + ss->state =3D UCODE_ERROR; + return false; +} + +/* + * Retrieve the next offset from the hardware response. + * Return true if the response is valid, false otherwise. + */ +static bool fetch_next_offset(struct staging_state *ss) +{ + pr_debug_once("Staging mailbox response handling code needs to be impleme= nted.\n\n"); + ss->state =3D UCODE_ERROR; + return false; +} + +/* + * Handle the staging process using the mailbox MMIO interface. The + * microcode image is transferred in chunks until completion. Return the + * result state. */ static enum ucode_state do_stage(u64 mmio_pa) { - pr_debug_once("Staging implementation is pending.\n"); - return UCODE_ERROR; + struct staging_state ss =3D {}; + + ss.mmio_base =3D ioremap(mmio_pa, MBOX_REG_NUM * MBOX_REG_SIZE); + if (WARN_ON_ONCE(!ss.mmio_base)) + return UCODE_ERROR; + + init_stage(&ss); + + /* Perform the staging process while within the retry limit */ + while (!is_stage_complete(ss.offset) && can_send_next_chunk(&ss)) { + /* Send a chunk of microcode each time: */ + if (!send_data_chunk(&ss)) + break; + /* + * Then, ask the hardware which piece of the image it + * needs next. The same piece may be sent more than once. + */ + if (!fetch_next_offset(&ss)) + break; + } + + iounmap(ss.mmio_base); + return ss.state; } =20 static void stage_microcode(void) --=20 2.48.1 From nobody Sat Oct 4 19:18:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11E9E28D8ED for ; Wed, 13 Aug 2025 17:27:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106037; cv=none; b=ArlaWiqCweTwMZ4VQHLxmyW1iIV2f05D5CqPSFCyBxGsVQN/uyiZVliH/KdcSjKXQknfrnSuHfdJbC/5Q42l+c1SSI7K0D28UfMZjwaJDR1ZgrYVuzwEI5xKvwob7doStlFGZZOLPjYGd+xKzXdlnnTEUQiSJAzNLw7ovqcihsg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755106037; c=relaxed/simple; bh=+2PlyR2Mfu2HfSnv645I17k79gyNKv3yi1r6lbBvNsk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QmEsWsrD5Q9cMudq5l7AR4NUhJ5fBbc8qiMA5y0QVnbBEmS53dulJTtdXPnaqlFD56JnjEA6b9T4nkExwvm6UBdHmXlHkVRyOp7UnySNTqehzs6VV/IOGxwQedlAWiKylcNRgBPeNpwGneX8pUQQIjUX4hte2s62dIWyuNbCLzY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XnklfIXu; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XnklfIXu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755106037; x=1786642037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+2PlyR2Mfu2HfSnv645I17k79gyNKv3yi1r6lbBvNsk=; b=XnklfIXuqYnIFzRvvZY4gRX4p6t/vQ2gC9QSNLR5LAnZEv5uwdaUSQgb yto2WvRP2H4ZDDXNdpbMarbhrQrQxRpeuf3kl8wMagw89Yuei2zZG1Vqk gXpWgkuPdQ7gNKToQiqBEXB1k8OQ7TcsEY11SXYtKwMAn0HyJMVVq3NJR 7j6Y92unod/bx63HWqTrTsQxZKVVWEJ7Z3D2Lo1NUrv+SGD8m4xefRUd+ /AM0ihPQ+z12/kHIyCo55CU5v/ayDNeljBZw4j3ntDWVXB5cHHp7+LNUf wNBsls89K6j7nwoqMYQMCmguSoh2INFZGEhsMWIn+6ZkD5PsIAXx1gVkd w==; X-CSE-ConnectionGUID: jYJ+4dyvQuaeNRcBi0JNjg== X-CSE-MsgGUID: yRorfvVNTe28Wr0wf6rQaw== X-IronPort-AV: E=McAfee;i="6800,10657,11520"; a="61255252" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="61255252" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2025 10:27:16 -0700 X-CSE-ConnectionGUID: DvozPFRZRlG1SmR3MFnCiQ== X-CSE-MsgGUID: bEi/Ndb0SPqqGCqtj4V0mg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="167329716" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.193]) by fmviesa010.fm.intel.com with ESMTP; 13 Aug 2025 10:27:15 -0700 From: "Chang S. Bae" To: x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, colinmitchell@google.com, chao.gao@intel.com, abusse@amazon.de, chang.seok.bae@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/6] x86/microcode/intel: Support mailbox transfer Date: Wed, 13 Aug 2025 10:26:48 -0700 Message-ID: <20250813172649.15474-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250813172649.15474-1-chang.seok.bae@intel.com> References: <20250409232713.4536-1-chang.seok.bae@intel.com> <20250813172649.15474-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previously, the functions for sending microcode data and retrieving the next offset were placeholders, as they required handling the specific mailbox format. Implement them as following: =3D=3D Mailbox Format =3D=3D The staging mailbox consists of two primary sections: 'header' and 'data'. While the microcode must be transferred following this format, the actual data transfer mechanism involves reading and writing to specific MMIO registers. =3D=3D Mailbox Data Registers =3D=3D Unlike conventional interfaces that allocate MMIO space for each data chunk, the staging interface features a "narrow" interface, using only two dword-sized registers for read and write operations. For example, if writing 2 dwords of data to a device. Typically, the device would expose 2 dwords of "wide" MMIO space. To send the data to the device: writel(buf[0], io_addr + 0); writel(buf[1], io_addr + 1); But, this interface is a bit different. Instead of having a "wide" interface where there is separate MMIO space for each word in a transaction, it has a "narrow" interface where several words are written to the same spot in MMIO space: writel(buf[0], io_addr); writel(buf[1], io_addr); The same goes for the read side. =3D=3D Implementation Summary =3D=3D Given that, introduce two layers of helper functions at first: * Low-level helpers for reading and writing to data registers directly. * Wrapper functions for handling mailbox header and data sections. Using them, implement send_data_chunk() and fetch_next_offset() functions. Add explicit error and timeout handling routine in wait_for_transaction(), finishing up the transfer. Note: The kernel has support for similar mailboxes. But none of them are compatible with this one. Trying to share code resulted in a bloated mess, so this code is standalone. Signed-off-by: Chang S. Bae Tested-by: Anselm Busse --- V2 -> V3: * Update code to reflect the removal of a global variable (Dave). V1 -> V2: * Add lots of code comments and edit the changelog (Dave). * Encapsulate register read/write operations for processing header and data sections. --- arch/x86/kernel/cpu/microcode/intel.c | 150 ++++++++++++++++++++++++-- 1 file changed, 144 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 3eb3331c5012..5402bcb96f47 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 #include #include @@ -42,8 +43,30 @@ static const char ucode_path[] =3D "kernel/x86/microcode= /GenuineIntel.bin"; =20 #define MBOX_CONTROL_OFFSET 0x0 #define MBOX_STATUS_OFFSET 0x4 +#define MBOX_WRDATA_OFFSET 0x8 +#define MBOX_RDDATA_OFFSET 0xc =20 #define MASK_MBOX_CTRL_ABORT BIT(0) +#define MASK_MBOX_CTRL_GO BIT(31) + +#define MASK_MBOX_STATUS_ERROR BIT(2) +#define MASK_MBOX_STATUS_READY BIT(31) + +#define MASK_MBOX_RESP_SUCCESS BIT(0) +#define MASK_MBOX_RESP_PROGRESS BIT(1) +#define MASK_MBOX_RESP_ERROR BIT(2) + +#define MBOX_CMD_LOAD 0x3 +#define MBOX_OBJ_STAGING 0xb +#define DWORD_ALIGN(size) ((size) / sizeof(u32)) +#define MBOX_HEADER(mbox_size) (PCI_VENDOR_ID_INTEL | \ + (MBOX_OBJ_STAGING << 16) | \ + ((u64)DWORD_ALIGN(mbox_size) << 32)) + +/* The size of each mailbox header */ +#define MBOX_HEADER_SIZE sizeof(u64) +/* The size of staging hardware response */ +#define MBOX_RESPONSE_SIZE sizeof(u64) =20 /* * Each microcode image is divided into chunks, each at most @@ -57,6 +80,7 @@ static const char ucode_path[] =3D "kernel/x86/microcode/= GenuineIntel.bin"; */ #define MBOX_XACTION_SIZE PAGE_SIZE #define MBOX_XACTION_MAX(imgsz) ((imgsz) * 2) +#define MBOX_XACTION_TIMEOUT_MS (10 * MSEC_PER_SEC) =20 /* Current microcode patch used in early patching on the APs. */ static struct microcode_intel *ucode_patch_va __read_mostly; @@ -345,6 +369,49 @@ static __init struct microcode_intel *scan_microcode(v= oid *data, size_t size, return size ? NULL : patch; } =20 +static inline u32 read_mbox_dword(void __iomem *mmio_base) +{ + u32 dword =3D readl(mmio_base + MBOX_RDDATA_OFFSET); + + /* Acknowledge read completion to the staging hardware */ + writel(0, mmio_base + MBOX_RDDATA_OFFSET); + return dword; +} + +static inline void write_mbox_dword(void __iomem *mmio_base, u32 dword) +{ + writel(dword, mmio_base + MBOX_WRDATA_OFFSET); +} + +static inline u64 read_mbox_header(void __iomem *mmio_base) +{ + u32 high, low; + + low =3D read_mbox_dword(mmio_base); + high =3D read_mbox_dword(mmio_base); + + return ((u64)high << 32) | low; +} + +static inline void write_mbox_header(void __iomem *mmio_base, u64 value) +{ + write_mbox_dword(mmio_base, value); + write_mbox_dword(mmio_base, value >> 32); +} + +static void write_mbox_data(void __iomem *mmio_base, u32 *chunk, unsigned = int chunk_size) +{ + int i; + + /* + * The MMIO space is mapped as Uncached (UC). Each write arrives + * at the device as an individual transaction in program order. + * The device can then resemble the sequence accordingly. + */ + for (i =3D 0; i < DWORD_ALIGN(chunk_size); i++) + write_mbox_dword(mmio_base, chunk[i]); +} + /* * Prepare for a new microcode transfer by resetting hardware and * configuring microcode image info. @@ -388,15 +455,71 @@ static bool can_send_next_chunk(struct staging_state = *ss) return true; } =20 +/* + * Wait for the hardware to complete a transaction. + * Return true on success, false on failure. + */ +static bool wait_for_transaction(struct staging_state *ss) +{ + u32 timeout, status; + + /* Allow time for hardware to complete the operation: */ + for (timeout =3D 0; timeout < MBOX_XACTION_TIMEOUT_MS; timeout++) { + msleep(1); + + status =3D readl(ss->mmio_base + MBOX_STATUS_OFFSET); + /* Break out early if the hardware is ready: */ + if (status & MASK_MBOX_STATUS_READY) + break; + } + + status =3D readl(ss->mmio_base + MBOX_STATUS_OFFSET); + + /* Check for explicit error response */ + if (status & MASK_MBOX_STATUS_ERROR) { + ss->state =3D UCODE_ERROR; + return false; + } + + /* + * Hardware is neither responded to the action nor + * signaled any error. Treat the case as timeout. + */ + if (!(status & MASK_MBOX_STATUS_READY)) { + ss->state =3D UCODE_TIMEOUT; + return false; + } + + ss->state =3D UCODE_OK; + return true; +} + /* * Transmit a chunk of the microcode image to the hardware. * Return true if the chunk is processed successfully. */ static bool send_data_chunk(struct staging_state *ss) { - pr_debug_once("Staging mailbox loading code needs to be implemented.\n"); - ss->state =3D UCODE_ERROR; - return false; + u16 mbox_size =3D MBOX_HEADER_SIZE * 2 + ss->chunk_size; + u32 *chunk =3D ss->ucode_ptr + ss->offset; + + /* + * Write 'request' mailbox object in the following order: + * - Mailbox header includes total size + * - Command header specifies the load operation + * - Data section contains a microcode chunk + */ + write_mbox_header(ss->mmio_base, MBOX_HEADER(mbox_size)); + write_mbox_header(ss->mmio_base, MBOX_CMD_LOAD); + write_mbox_data(ss->mmio_base, chunk, ss->chunk_size); + ss->bytes_sent +=3D ss->chunk_size; + + /* + * Notify the hardware that the mailbox is ready for processing. + * The staging hardware will process the request asynchronously. + */ + writel(MASK_MBOX_CTRL_GO, ss->mmio_base + MBOX_CONTROL_OFFSET); + return wait_for_transaction(ss); } =20 /* @@ -405,9 +528,24 @@ static bool send_data_chunk(struct staging_state *ss) */ static bool fetch_next_offset(struct staging_state *ss) { - pr_debug_once("Staging mailbox response handling code needs to be impleme= nted.\n\n"); - ss->state =3D UCODE_ERROR; - return false; + const u16 mbox_size =3D MBOX_HEADER_SIZE + MBOX_RESPONSE_SIZE; + + /* All responses begin with the same header value: */ + WARN_ON_ONCE(read_mbox_header(ss->mmio_base) !=3D MBOX_HEADER(mbox_size)); + + /* + * The 'response' mailbox contains two dword data: + * - First has next offset in microcode image + * - Second delivers status flag + */ + ss->offset =3D read_mbox_dword(ss->mmio_base); + if (read_mbox_dword(ss->mmio_base) & MASK_MBOX_RESP_ERROR) { + ss->state =3D UCODE_ERROR; + return false; + } + + ss->state =3D UCODE_OK; + return true; } =20 /* --=20 2.48.1 From nobody Sat Oct 4 19:18:42 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BC60291861 for ; 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a="61255261" X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="61255261" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2025 10:27:17 -0700 X-CSE-ConnectionGUID: FHour4/+Q66Jz3QbIqYJBA== X-CSE-MsgGUID: oe/4pfVxSryXDOtdndcCNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,287,1747724400"; d="scan'208";a="167329719" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.161.193]) by fmviesa010.fm.intel.com with ESMTP; 13 Aug 2025 10:27:16 -0700 From: "Chang S. Bae" To: x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, colinmitchell@google.com, chao.gao@intel.com, abusse@amazon.de, chang.seok.bae@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH v4 6/6] x86/microcode/intel: Enable staging when available Date: Wed, 13 Aug 2025 10:26:49 -0700 Message-ID: <20250813172649.15474-7-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250813172649.15474-1-chang.seok.bae@intel.com> References: <20250409232713.4536-1-chang.seok.bae@intel.com> <20250813172649.15474-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the staging code being ready, check for staging availability by reading these following MSRs: * IA32_ARCH_CAPABILITIES (bit 16) for the presence of IA32_MCU_ENUMERATION * IA32_MCU_ENUMERATION (bit 4) for the staging feature availability. When available, enable it by setting the feature bit. Signed-off-by: Chang S. Bae Tested-by: Anselm Busse Reviewed-by: Chao Gao --- V1 -> V2: Fold MSR definings (Boris). --- arch/x86/include/asm/msr-index.h | 7 +++++++ arch/x86/kernel/cpu/microcode/intel.c | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 0356155f9264..2b7b598c414f 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -166,6 +166,10 @@ * Processor MMIO stale data * vulnerabilities. */ +#define ARCH_CAP_MCU_ENUM BIT(16) /* + * Indicates the presence of microcode update + * feature enumeration and status information + */ #define ARCH_CAP_FB_CLEAR BIT(17) /* * VERW clears CPU fill buffer * even on MDS_NO CPUs. @@ -913,6 +917,9 @@ #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b =20 +#define MSR_IA32_MCU_ENUMERATION 0x0000007b +#define MCU_STAGING BIT(4) + #define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5 =20 /* Intel SGX Launch Enclave Public Key Hash MSRs */ diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 5402bcb96f47..4da5f3581a94 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -959,6 +959,18 @@ static __init void calc_llc_size_per_core(struct cpuin= fo_x86 *c) llc_size_per_core =3D (unsigned int)llc_size; } =20 +static __init bool staging_available(void) +{ + u64 val; + + val =3D x86_read_arch_cap_msr(); + if (!(val & ARCH_CAP_MCU_ENUM)) + return false; + + rdmsrl(MSR_IA32_MCU_ENUMERATION, val); + return !!(val & MCU_STAGING); +} + struct microcode_ops * __init init_intel_microcode(void) { struct cpuinfo_x86 *c =3D &boot_cpu_data; @@ -969,6 +981,11 @@ struct microcode_ops * __init init_intel_microcode(voi= d) return NULL; } =20 + if (staging_available()) { + microcode_intel_ops.use_staging =3D true; + pr_info("Enabled staging feature.\n"); + } + calc_llc_size_per_core(c); =20 return µcode_intel_ops; --=20 2.48.1