From nobody Sat Oct 4 21:03:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C7672FF16D; Wed, 13 Aug 2025 14:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; cv=none; b=niYfJK2EiOAYbF2s5vccN48lpEP28DfLWCEya+rLBsrcmy6SV7BIfEUAf/STJJDXnBUG6LAooKHshF35kTRq9twk3mNPvApr7fxQ2G2ppsMg1NjgLsK/c6UOvuDbY8fRXTNZmUX2gLXa0LHP8jR35faAonNR0M7buTfRYrM8ac8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; c=relaxed/simple; bh=RVal9HTE3KtH+mFNbn3brWgtrY/W+HjmgbacLzq8U5E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=V7VSiVug8Esy1N/Ds8H6ESgliakMjj+KoIITP7KfiBm/bKBDhjxwyp98lcph1DL5aDtsESGj8OItzXql3yUUKsCS/M0MPZpjwtUA6NPA2/bkGjkXu6BerEOkplCZksq1vvjRh2yoC9GhbsmguyZAbjUWmbhYa81CmyWSMBScupc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S33giej8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S33giej8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA19DC4CEFA; Wed, 13 Aug 2025 14:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096950; bh=RVal9HTE3KtH+mFNbn3brWgtrY/W+HjmgbacLzq8U5E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S33giej8gHnlgi+xgSwr0e1NDi6b4ipyxr/RH4dmTP6GI2PtXGbI3UUfcPozZdXpe AUdAlv7mLk4VzoqPs+eeM1oNQpV4K4+Z9aZyZaIFHvYv3ffQG0otokJQsBzr/GKPH+ pWibPmGhQEafDsimQfSldAMA7ojQee4ioiiUyvbq+C4TC6c//9wLyyaB9o+cIFgo4p S+2xtgW/cLcf8OpFVU/P02sVhDjW9bUEb2IgIYgH7Bf4qRTrJxvdH+T7nL9UinTQSW HwTHNKFKAZC4YU4JIWJvS99+gzCS780gxur6pNFTfhhkrXczynhxGISzpaWapUM1Li A+bHLu56J9Geg== Received: by wens.tw (Postfix, from userid 1000) id 4A4C85FF90; Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 07/10] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Wed, 13 Aug 2025 22:55:37 +0800 Message-Id: <20250813145540.2577789-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. An enable delay for the PHY supply regulator is added to make sure the PHY's internal regulators are fully powered and the PHY is operational. Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Add PHY regulator delay --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index d4cee2222104..e96a419faf21 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -76,7 +77,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -85,13 +86,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <300>; + rx-internal-delay-ps =3D <400>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -100,6 +112,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -240,6 +262,8 @@ reg_cldo4: cldo4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay =3D <150000>; }; =20 reg_cpusldo: cpusldo { --=20 2.39.5