From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35B2F2F2909; Wed, 13 Aug 2025 14:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096948; cv=none; b=QzQ2/n0Y2VwG3oZTdCQ/PnPCjcTnOmgevrUGA0OkAgIdNAGoPF+ZqE8KNwi8zDSemGTlaPnkIeKedKwFcguLz3alDiuA87Zc6AiB2f4Pw1PO8PxndSJW4iVqvmXtfM5EhpwLVoyfb8IXvTA4oCfudoQheWF3AFzrT239oHKDXBc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096948; c=relaxed/simple; bh=VH0N7W47+kOQX4MCst8bkGtFUp56xeT53SSsWcTl1lA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bmbYkJBA1tBPY5dOpL085jmFqhSd/TJAQmMw6Jrz5u+DCsYZ2p3dfE9YGFzRwlHhfQRuqCqOo7QPR5nnjqZ00I0KbW3FrQJM/G870EFdSnAAEyJu6grjO2k4Er997PfVq0khhTMYevnfNvwoLvHpkD//IfNnCJ0N5b5Mvbw9wgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=j54Zd/IR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="j54Zd/IR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A4AEAC4AF0B; Wed, 13 Aug 2025 14:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096947; bh=VH0N7W47+kOQX4MCst8bkGtFUp56xeT53SSsWcTl1lA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j54Zd/IRCdHbdteiJ/3WB5SmJxLTENox/6+0h8gnY3oDL7I+CnDTpEYMQO9ntpzLD Uw0ZjCwC78QtmvVGClqZA+XJ4q4aKlHQa7njPt7OQq6ZTPuqTB6hGRaj+my1wbwra1 WQ94vtqT4OBZX8Vx0/L6oxUfFswvc1Gho/kuS33P+qmC2I/vH8copLv5r9Ru9zgE1A cld74mX1dawuaMGvM7zIwzMhy1ubTBoWmJ2IJA1w75nVBoVL1s2en+JWfueSo8n5UW F6P+LHb4OJd1FUlPPln05QtnYCH1gpobIIloWGMeIq39Q6ah1dPqW1F9t7h+1aq0FW S6g4oj44JN5hg== Received: by wens.tw (Postfix, from userid 1000) id 1658D5FE8C; Wed, 13 Aug 2025 22:55:44 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 01/10] dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Date: Wed, 13 Aug 2025 22:55:31 +0800 Message-Id: <20250813145540.2577789-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../net/allwinner,sun8i-a83t-emac.yaml | 81 ++++++++++++++++++- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 2ac709a4c472..b4358e6456fa 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -26,6 +26,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a =20 reg: maxItems: 1 @@ -37,14 +40,19 @@ properties: const: macirq =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clock-names: - const: stmmaceth + minItems: 1 + maxItems: 2 =20 phy-supply: description: PHY regulator =20 + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -191,6 +199,45 @@ allOf: - mdio-parent-bus - mdio@1 =20 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: stmmaceth + - const: mbus + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 700 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 3100 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: stmmaceth + power-domains: false + + unevaluatedProperties: false =20 examples: @@ -323,4 +370,34 @@ examples: }; }; =20 + - | + ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu 117>, <&ccu 79>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu 43>; + reset-names =3D "stmmaceth"; + interrupts =3D <0 47 4>; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 4>; + syscon =3D <&syscon>; + phy-handle =3D <&ext_rgmii_phy_1>; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; ... --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35BFF2F2914; Wed, 13 Aug 2025 14:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096948; cv=none; b=Nh2HdjByI5dVcVcel10lNhEimA4btbm9trow2DRiDm8vdFfeJ5EtOAebJv93HnEcIlXkBHFUPObqBMLd+mu0fPHrxHRlFcGNA6wXq9dYNbszFf+LqsctGIbkO6xn3o7z93QPXi6NGAX5nL6qZxVJwSVV2ko8cORQk+xQxx56rvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096948; c=relaxed/simple; bh=Cl/W5ilLxJ3HhR6Nrk8R7mtwkT5wONqPpFC+0pWz4xE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Rtn35jiK20AAKEXXdiyOnT29nD1eJr8VQUhMW3L5JAxyM3cGx17iffj/J30lkVR+OhKg+Qi8+tWH+zJEXrlRF0rwHmQZNL/KVbdBhcJTnQGihbrYl8Z7H6+wP8AaH5HdUTMDxho8iCbtPHR34iX3vxKztnH25eDDjx64skpS1Nk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BnPpbMpQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BnPpbMpQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9F50FC4CEF1; Wed, 13 Aug 2025 14:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096947; bh=Cl/W5ilLxJ3HhR6Nrk8R7mtwkT5wONqPpFC+0pWz4xE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BnPpbMpQ1UwEF9aACFd1v8R6iEEt/jc1hX2IfaWVFm2ECQoklOqH4bOB+9noRqRiU jlDMvk41HnTzVzSiGLegM2ukCHb9CUbTGvSKcXsun/R4DcZYXUzsZNsxMWdYm4qD7T Dd4/8vE3/GthmPoCDbkXZ32eueHB9jo2/tljlj5tjC2pVvesgQUX3Qjc0NIbpyu2Qk up9JadJxd4ne6cPqMGvlIony6K/eZmJk+pncrM+esNlSzKBwK8KxrKCc+ArlkvoxEu ePXaWSxDrXUx+srAgyV9RkxP66YuE3DpRBAd1rJPJ2fgBzV4RiLoTAXQ0KZBZeKtn9 O64jEcNl+VTcA== Received: by wens.tw (Postfix, from userid 1000) id 09D315F843; Wed, 13 Aug 2025 22:55:44 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 02/10] net: stmmac: Add support for Allwinner A523 GMAC200 Date: Wed, 13 Aug 2025 22:55:32 +0800 Message-Id: <20250813145540.2577789-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a new driver for this hardware supporting the integration layer. Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Change dev_err() + return to dev_err_probe() - Check return value from syscon regmap write - Change driver name to match file name --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-sun55i.c | 161 ++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..38ce9a0cfb5b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -263,6 +263,18 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_SUN55I + tristate "Allwinner sun55i GMAC200 support" + default ARCH_SUNXI + depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX + help + Support for Allwinner A523/T527 GMAC200 ethernet controllers. + + This selects Allwinner SoC glue layer support for the + stmmac device driver. This driver is used for A523/T527 + GMAC200 ethernet controller. + config DWMAC_THEAD tristate "T-HEAD dwmac support" depends on OF && (ARCH_THEAD || COMPILE_TEST) diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index b591d93f8503..51e068e26ce4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_SUN55I) +=3D dwmac-sun55i.o obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c new file mode 100644 index 000000000000..7c67313872e1 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dwmac-sun55i.c - Allwinner sun55i GMAC200 specific glue layer + * + * Copyright (C) 2025 Chen-Yu Tsai + * + * syscon parts taken from dwmac-sun8i.c, which is + * + * Copyright (C) 2017 Corentin Labbe + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define SYSCON_REG 0x34 + +/* RMII specific bits */ +#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ +/* Generic system control EMAC_CLK bits */ +#define SYSCON_ETXDC_MASK GENMASK(12, 10) +#define SYSCON_ERXDC_MASK GENMASK(9, 5) +/* EMAC PHY Interface Type */ +#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SYSCON_ETCS_MASK GENMASK(1, 0) +#define SYSCON_ETCS_MII 0x0 +#define SYSCON_ETCS_EXT_GMII 0x1 +#define SYSCON_ETCS_INT_GMII 0x2 + +#define MASK_TO_VAL(mask) ((mask) >> (__builtin_ffsll(mask) - 1)) + +static int sun55i_gmac200_set_syscon(struct device *dev, + struct plat_stmmacenet_data *plat) +{ + struct device_node *node =3D dev->of_node; + struct regmap *regmap; + u32 val, reg =3D 0; + int ret; + + regmap =3D syscon_regmap_lookup_by_phandle(node, "syscon"); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n"); + + if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "tx-delay must be a multiple of 100\n"); + val /=3D 100; + dev_dbg(dev, "set tx-delay to %x\n", val); + if (val > MASK_TO_VAL(SYSCON_ETXDC_MASK)) + return dev_err_probe(dev, -EINVAL, + "Invalid TX clock delay: %d\n", + val); + + reg |=3D FIELD_PREP(SYSCON_ETXDC_MASK, val); + } + + if (!of_property_read_u32(node, "rx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "rx-delay must be a multiple of 100\n"); + val /=3D 100; + dev_dbg(dev, "set rx-delay to %x\n", val); + if (val > MASK_TO_VAL(SYSCON_ERXDC_MASK)) + return dev_err_probe(dev, -EINVAL, + "Invalid RX clock delay: %d\n", + val); + + reg |=3D FIELD_PREP(SYSCON_ERXDC_MASK, val); + } + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg |=3D SYSCON_EPIT | SYSCON_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |=3D SYSCON_RMII_EN; + break; + default: + return dev_err_probe(dev, -EINVAL, "Unsupported interface mode: %s", + phy_modes(plat->mac_interface)); + } + + ret =3D regmap_write(regmap, SYSCON_REG, reg); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to write to syscon\n"); + + return 0; +} + +static int sun55i_gmac200_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct device *dev =3D &pdev->dev; + struct clk *clk; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + /* BSP disables it */ + plat_dat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + plat_dat->host_dma_width =3D 32; + + ret =3D sun55i_gmac200_set_syscon(dev, plat_dat); + if (ret) + return ret; + + clk =3D devm_clk_get_enabled(dev, "mbus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get or enable MBUS clock\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "phy"); + if (ret) + return dev_err_probe(dev, ret, "Failed to get or enable PHY supply\n"); + + return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); +} + +static const struct of_device_id sun55i_gmac200_match[] =3D { + { .compatible =3D "allwinner,sun55i-a523-gmac200" }, + { } +}; +MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); + +static struct platform_driver sun55i_gmac200_driver =3D { + .probe =3D sun55i_gmac200_probe, + .driver =3D { + .name =3D "dwmac-sun55i", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D sun55i_gmac200_match, + }, +}; +module_platform_driver(sun55i_gmac200_driver); + +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_DESCRIPTION("Allwinner sun55i GMAC200 specific glue layer"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35CE32F291A; Wed, 13 Aug 2025 14:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096948; cv=none; b=LwqLdmIAD0+9C3Vs31UDaGuaw6B68khoBK4kqvfTs5j8djMdoqaopIHo3UZEp2LkHE7g229msQklE91LJmjB/x9IEC5WcDpp7ghjW6qWjKwfIwWTVt3MU6nW7JZ8jj5inXKM+6lNnQMA4MZkGR0ZYQkxmunxVsKNkT5zAmNU9Io= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096948; c=relaxed/simple; bh=0IUVHkNpNiVd4dKfHNtccXkcqQYA1UMken7l+DdOKgk=; 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Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 03/10] soc: sunxi: sram: add entry for a523 Date: Wed, 13 Aug 2025 22:55:33 +0800 Message-Id: <20250813145540.2577789-4-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 has two Ethernet controllers. So in the system controller address space, there are two registers for Ethernet clock delays, one for each controller. Add a new entry for the A523 system controller that allows access to the second register. Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- drivers/soc/sunxi/sunxi_sram.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 08e264ea0697..4f8d510b7e1e 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -320,6 +320,10 @@ static const struct sunxi_sramc_variant sun50i_h616_sr= amc_variant =3D { .has_ths_offset =3D true, }; =20 +static const struct sunxi_sramc_variant sun55i_a523_sramc_variant =3D { + .num_emac_clocks =3D 2, +}; + #define SUNXI_SRAM_THS_OFFSET_REG 0x0 #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 #define SUNXI_SYS_LDO_CTRL_REG 0x150 @@ -440,6 +444,10 @@ static const struct of_device_id sunxi_sram_dt_match[]= =3D { .compatible =3D "allwinner,sun50i-h616-system-control", .data =3D &sun50i_h616_sramc_variant, }, + { + .compatible =3D "allwinner,sun55i-a523-system-control", + .data =3D &sun55i_a523_sramc_variant, + }, { }, }; MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A8A22FFDCC; Wed, 13 Aug 2025 14:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; cv=none; b=FWrg7ez/Ea187q8MkHcQUFhe3la3GhoFV2p6Vw1ACfE30Ph9YqtbxQ9GWAfTEUTJoUF0JFqFuGkViwSqji7rRVPKAEstnbgLRPn7BRO/qDKchfXAfu0mFdvJQfh9YqjQn6uwnq+2sRZdVk+lazD/tafEY06Vi4J7nv7rwYd20zM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; c=relaxed/simple; bh=W5wn3NeKGRyaF5afVGlpCWkJIlaztzO4EVZV0lTaqQg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bS/z5mYbZ3bhR9h+3qj3dq3oNvkxy2Bjmpp2/mqF+3hT3SZ4V9j08kcR8DsSvJn+Y0/R7z7JXRh/zIQ0Crlz0w6ZPsZhxfp4lL72lAVe3wItJZLda6l5rtzFRKW2y7skMlvTUdmogNUXTJ1SinPQZoxPvmA/9K6BBCb674ozXeo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gKjmu7gD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gKjmu7gD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E3CE7C116B1; Wed, 13 Aug 2025 14:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096950; bh=W5wn3NeKGRyaF5afVGlpCWkJIlaztzO4EVZV0lTaqQg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gKjmu7gDM/sY1ung+b2oB69H9t9KqVNJfZZG37yj0ObpM930lYQpvllOBqy57EVBb BYqjyn77jC9dpRjHpPpBFufMN/jl3clDlr5WPou97L63ucspEq6u7JFy0XYc4X0PXX SdyDkwbhXhpagqemeI2U66L1rSFi++CLCfbjmXNcTaAahu1KUqq8Lzuj23I9fw3xgR wAIXot0CwvTBXFjN29c36eSgEoFcyIIWdS3fsX/uiK+jOb4kw+0zLbtfq/NYDklvhq YvH6l6B1Q3zb0qe7/veWRGMicVkemt+H1NaNIoOZ6Dmx4zNkTT3wXZGTU41C5zm9P+ YrWKodIMh+YSw== Received: by wens.tw (Postfix, from userid 1000) id 341B15FF5B; Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 04/10] soc: sunxi: sram: register regmap as syscon Date: Wed, 13 Aug 2025 22:55:34 +0800 Message-Id: <20250813145540.2577789-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai If the system controller had a ethernet controller glue layer control register, a limited access regmap would be registered and tied to the system controller struct device for the ethernet driver to use. Until now, for the ethernet driver to acquire this regmap, it had to do a of_parse_phandle() + find device + dev_get_regmap() sequence. Since the syscon framework allows a provider to register a custom regmap for its device node, and the ethernet driver already uses syscon for one platform, this provides a much more easier way to pass the regmap. Use of_syscon_register_regmap() to register our regmap with the syscon framework so that consumers can retrieve it that way. Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- Changes since v1: - Fix check on return value - Expand commit message --- drivers/soc/sunxi/sunxi_sram.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 4f8d510b7e1e..1837e1b5dce8 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -12,6 +12,7 @@ =20 #include #include +#include #include #include #include @@ -377,6 +378,7 @@ static int __init sunxi_sram_probe(struct platform_devi= ce *pdev) const struct sunxi_sramc_variant *variant; struct device *dev =3D &pdev->dev; struct regmap *regmap; + int ret; =20 sram_dev =3D &pdev->dev; =20 @@ -394,6 +396,10 @@ static int __init sunxi_sram_probe(struct platform_dev= ice *pdev) regmap =3D devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + + ret =3D of_syscon_register_regmap(dev->of_node, regmap); + if (ret) + return ret; } =20 of_platform_populate(dev->of_node, NULL, NULL, dev); --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 889902FFDDC; Wed, 13 Aug 2025 14:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; cv=none; b=UA9SZs0ukGEDIzQxHEm2Ysd4rKrg1c6UHF6feW2jmiT8vDW3bBj/UMaRlUiXzUG1j5dXuXexbuG4NbHOg3u1o4KibWtulJu9WAwp7yW3M1rxwiojnbrvFMxvkHzriYCUdvmjaClO3whvNCrqA4upAsw3KwvirvJWYBM+kYBNfUA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; c=relaxed/simple; bh=yKrAHC0riAXESr1YT7TRrWp4LLqyhsj+D6V4VUG4krM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PQp0IAIJUR64+7qtXe2I9eLHlvHC+ji3kbx4mhTSh9rMqPiOryF0yjI2YcAZEJQRW5zVySrXRj0H1R0VQrpvzq5cI0qQWcLOKcfW7dT30DpOI5iXp+/d7B7zdws6frHBP9gYUlCLfRX0xZD0aLp50GX9b7qmKQHRQuJkSXQX0RM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aRn5niKh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aRn5niKh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C95EC4CEEF; Wed, 13 Aug 2025 14:55:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096950; bh=yKrAHC0riAXESr1YT7TRrWp4LLqyhsj+D6V4VUG4krM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aRn5niKhjq2Lr784ZyGMYtj4dP5OyKaAccRzguObTv7W4Sc/RbtOv3LjL57ayXrU/ 78WOYTPUMq8EbhBQuRUTYNQKM+TYCstHvrw/FlUCsyyJ67Ja9OqbUeRPc/NzvwkQs2 g3mOu0LRsw60EqW1JPt3SMufrSys39+DP+o4T69EsKuN4NVyjuNiyfNZMBNdkgY2dE GQvZPTne4nMKSAJFO5LclIqSl+xdpLhOjDq6HfP3czTfYrnG0tHNU7BQiG5OhbglBo 4fZoQNi6q/h8Gk3qr8xf8sMS49PXUbF3AyIAMvZhT9QolKqNcH7LvXIV56LyXfLNX8 26bS6VUl2vJLQ== Received: by wens.tw (Postfix, from userid 1000) id 38A3E5FEEF; Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 05/10] arm64: dts: allwinner: a523: Add GMAC200 ethernet controller Date: Wed, 13 Aug 2025 22:55:35 +0800 Message-Id: <20250813145540.2577789-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has a second ethernet controller, called the GMAC200. It is not exposed on all the SoCs in the family. Add a device node for it. All the hardware specific settings are from the vendor BSP. Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- Changes since v1: - Fixed typo in tx-queues-config --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296bdff..449bcafbddcd 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -180,6 +180,16 @@ rgmii0_pins: rgmii0-pins { bias-disable; }; =20 + rgmii1_pins: rgmii1-pins { + pins =3D "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux =3D <5>; + function =3D "gmac1"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -601,6 +611,51 @@ mdio0: mdio { }; }; =20 + gmac1: ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu RST_BUS_EMAC1>; + reset-names =3D "stmmaceth"; + interrupts =3D ; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 PD_VO1>; + syscon =3D <&syscon>; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35AB82EFDA5; Wed, 13 Aug 2025 14:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096948; cv=none; b=I2BWTDyZt4DOClRfTEheRXELFOYmJYy80qSsF2oN6c84Q9ioIvPAjolBhx0SVIxoXMWq2m2u1V/AtxNm+BRNJi2VQv1M0clZ104fwe3prwO/+fsEavZ50sjFQ/DIrfsRWBFy4pT0uX5AoN9QSBZwJOFSd/Ghxd682Er6RY8ZGdA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096948; c=relaxed/simple; bh=tDfUpZExKmJMXStQh2fTARqlHOrlMBEVmIQj8qTNpp8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JORQtQRv7n6RAbqZblovdZzQ2bmPegp3dpyaIBlryM55gZFr+qD9t5TpldmRn29BuP3pTOfmJ/7zFoDbKaBTL5nuM8pLi/529NiG2ZZ7A8Ne+htT4KEkAjHWecaiVl7CZZEilQjUJmaVIkunUYzuyXWe9ngvoaUbXO8tjZ3phbA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U6YkdF24; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U6YkdF24" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A210BC4AF09; Wed, 13 Aug 2025 14:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096947; bh=tDfUpZExKmJMXStQh2fTARqlHOrlMBEVmIQj8qTNpp8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U6YkdF24uls3iDY1HAv8Weghhp2cN67nZBA70lqLv1r2uhk3tRVBWlfJ/B3gQ9i/p +YwcjV5ob/61OwEq9MLS2tjY1Q1VRbmBrWQ7pKE2NCusSJMxni3Q6SRI8fhy9QbIew 18J96Kf4ueIjFH4GHiaJM71wSeXxvezTPTnrVFElmQq0a5G4AsAltbN11F2+vaOffz oNUG3Lv3JeLFpkcC2NjBtJKBCOb35MHNIhARhHYG0daIFjCZNhCkF+4OsC1K4xup+A Bd9qI2lZozR+KsuX9TIeFqb65lzs/ZHIeAhxYL63irKbFbvJ8OWVtxTx83EE0rWvIV 5TctEyHhXm86Q== Received: by wens.tw (Postfix, from userid 1000) id 27E2B5FEBD; Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 06/10] arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting Date: Wed, 13 Aug 2025 22:55:36 +0800 Message-Id: <20250813145540.2577789-7-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: acca163f3f51 ("arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E b= oard") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 70d439bc845c..d4cee2222104 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -94,6 +94,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; }; }; =20 --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C7672FF16D; Wed, 13 Aug 2025 14:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; cv=none; b=niYfJK2EiOAYbF2s5vccN48lpEP28DfLWCEya+rLBsrcmy6SV7BIfEUAf/STJJDXnBUG6LAooKHshF35kTRq9twk3mNPvApr7fxQ2G2ppsMg1NjgLsK/c6UOvuDbY8fRXTNZmUX2gLXa0LHP8jR35faAonNR0M7buTfRYrM8ac8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; c=relaxed/simple; bh=RVal9HTE3KtH+mFNbn3brWgtrY/W+HjmgbacLzq8U5E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=V7VSiVug8Esy1N/Ds8H6ESgliakMjj+KoIITP7KfiBm/bKBDhjxwyp98lcph1DL5aDtsESGj8OItzXql3yUUKsCS/M0MPZpjwtUA6NPA2/bkGjkXu6BerEOkplCZksq1vvjRh2yoC9GhbsmguyZAbjUWmbhYa81CmyWSMBScupc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S33giej8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S33giej8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA19DC4CEFA; Wed, 13 Aug 2025 14:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096950; bh=RVal9HTE3KtH+mFNbn3brWgtrY/W+HjmgbacLzq8U5E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S33giej8gHnlgi+xgSwr0e1NDi6b4ipyxr/RH4dmTP6GI2PtXGbI3UUfcPozZdXpe AUdAlv7mLk4VzoqPs+eeM1oNQpV4K4+Z9aZyZaIFHvYv3ffQG0otokJQsBzr/GKPH+ pWibPmGhQEafDsimQfSldAMA7ojQee4ioiiUyvbq+C4TC6c//9wLyyaB9o+cIFgo4p S+2xtgW/cLcf8OpFVU/P02sVhDjW9bUEb2IgIYgH7Bf4qRTrJxvdH+T7nL9UinTQSW HwTHNKFKAZC4YU4JIWJvS99+gzCS780gxur6pNFTfhhkrXczynhxGISzpaWapUM1Li A+bHLu56J9Geg== Received: by wens.tw (Postfix, from userid 1000) id 4A4C85FF90; Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 07/10] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Wed, 13 Aug 2025 22:55:37 +0800 Message-Id: <20250813145540.2577789-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. An enable delay for the PHY supply regulator is added to make sure the PHY's internal regulators are fully powered and the PHY is operational. Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Add PHY regulator delay --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index d4cee2222104..e96a419faf21 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -76,7 +77,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -85,13 +86,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <300>; + rx-internal-delay-ps =3D <400>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -100,6 +112,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -240,6 +262,8 @@ reg_cldo4: cldo4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay =3D <150000>; }; =20 reg_cpusldo: cpusldo { --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B3702FFDCD; Wed, 13 Aug 2025 14:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; cv=none; b=I387pioNFmqovzBOhyKOoGi7C5qkt7aU6vhSGirNmRh6GFM2gyq5iC0SxE7dWZIB8rUbcf/gUS7oHwxJbSKfLAfztLDuaiglAOKR6T8vigUIRfj8T1ZYed81+IXDzyWTfUiC9evySV/MmeqdQiVopCfKy1iIkwmAKXPG5hMPJBE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; c=relaxed/simple; bh=/usWm/vrAulCsp4Fo0dvH/GWf7HQ6Sc8o/o3f/vf8hE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LD9AqTHnjoFbDi4LUjJhLAoJgvWX+xTLOLk5r+29+Z3aDilwOCNL4E0nt9NJ2M49hLl6X1lWq734ydkpJfjNnYxCNbwJaOUj73vf1LRCqOuWqawIyccfNqFSKPJi7vAEMiPl2XwXGIT1dYpbkfyBNUatDEcPN0zl4ZwdNZZg9PY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F78sv2/7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F78sv2/7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0BC3C4CEF1; Wed, 13 Aug 2025 14:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096950; bh=/usWm/vrAulCsp4Fo0dvH/GWf7HQ6Sc8o/o3f/vf8hE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F78sv2/7X2r8RCxweQ91Vm2r+O/C8tEOxDFBrupkW8VJNsfb9n9TDBF7i0rmY/fvb tH3pvYlakWjVDCdjH/1LMnpZcreHnm0smJuVA2tFwp8sycBBDKg91IPV8gM4TuSlmJ 1nmafLuTvPmvzDlfs71e2XeRHbe91fDeb9L9HXtNjcd7oyEuHctzCeZ4DyFlTBfPKs MOLJry39YvbVDDxNKoYt4VGNZu4n4+MBDAlbes5cXHmMEAoq1sXHOimGhjkhKLDTXg 5EzukLsGzN8tfgBXrMmJfPaqk2m5UVEyz+0PCOlFZTaouEn7oKHZ7KzVW0J9yoxC9d O0tFX1ePl/ixw== Received: by wens.tw (Postfix, from userid 1000) id 42B565FF03; Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 08/10] arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting Date: Wed, 13 Aug 2025 22:55:38 +0800 Message-Id: <20250813145540.2577789-9-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: c6800f15998b ("arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 b= oard") Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index b9eeb6753e9e..e7713678208d 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -85,6 +85,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; }; }; =20 --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A66B2FFDCB; Wed, 13 Aug 2025 14:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; cv=none; b=DxNoJ2/nClzT36pNQ8wKGVLTlr+ky+jJSCKaJcAgf6Y1u+FuVL0dNK3sR23Yq/etDWDXOfrrcpdwU7pSjsr4s04enaoh7uY10cQfaE3kPWcZzg9GGmg4QHgqiCXCymtKFLxxLobfogHscn61zt81/tz5qVFQtcjJ4jwKnYFGFlw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; c=relaxed/simple; bh=efhUDQe2jwo6mMDNsNwWZlvEPFGFYGTDZhRv4W8Y2gI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Mln58W9kXyLwKsuMoRQPHnXxivtxmkEAVTbCokEH4yGF8mRSwIPzE4oPWFMx8XIU9G4tjJFhS/OvAwt45LdF6dX3B4R53L8vYFzjjKliQK/ZweZAs7QQmDN4/a+5/nvKDJnthm2f8mXUhLXNVBHPh/XR3HK0CM5MsWeh/NPfDko= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dZ9gTHp8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dZ9gTHp8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E748AC4CEF8; Wed, 13 Aug 2025 14:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096950; bh=efhUDQe2jwo6mMDNsNwWZlvEPFGFYGTDZhRv4W8Y2gI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dZ9gTHp8VjxKV0gtmhGBRwHECZQqSCBqWMAw6/AUvhnNoZjT2Dg6zwNsjY80VZ4j3 Ys99ZxZJJXj3mRgxEXZuU7A1ChzYtOV96zIqt4enqaN4iS3Wv8dFziiqu1jafO59OG skRZNZTXsZnmPm01UO3NYJ4MhJqxlyN3DOlWxG3cQn22EfHXAUTXxvFbdGo5PMSuXa 8uO8Ct2Ap8oGfVw7EbuPn4KK/3A7gLBouRYeFXEIwVYRFqh5DxMvLivhmx1dyV8n8U OVlCQf8Xl+NM3hYe7jLpx9Z/kSZ6iUtKIjg4LqF9wTJot801a4aKcQVqNnFWKwLkHf 2HXvv9XHT7a3w== Received: by wens.tw (Postfix, from userid 1000) id 551005FF75; Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 09/10] arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port Date: Wed, 13 Aug 2025 22:55:39 +0800 Message-Id: <20250813145540.2577789-10-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Avaota A1 board, the second Ethernet controller, aka the GMAC200, is connected to a second external RTL8211F-CG PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index e7713678208d..f540965ffaa4 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -67,7 +68,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_dcdc4>; =20 allwinner,tx-delay-ps =3D <100>; @@ -76,13 +77,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_dcdc4>; + + tx-internal-delay-ps =3D <100>; + rx-internal-delay-ps =3D <100>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -91,6 +103,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5 From nobody Sat Oct 4 19:16:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B74E2FFDC3; Wed, 13 Aug 2025 14:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; cv=none; b=NJQKETe8LBYOpyvV3GlXN6Z8HiEC4LuslT+OKSgpO8Av89kQ4rU/PxrpQPbqjbDCEJQbmuwdEfGlYd+O0KRQBR0B2isDpjWWpNUiLNP+Y/ETEdugtIMwgkLqm9I5Uardp6NJaVgNSDQNBK1Ey1MJ9PbSE9BZ9qNUIIM0r1eCMKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096950; c=relaxed/simple; bh=5v1d2ZPdszghDIrJGhbTRJ0+vB3QSvZx9Rmgr+KUWTs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I/L5Iy+J1eEDbx5/27xaS4FRgCKyE5xnSBHJSCgOWqnAuZl7tC8FO8HLQmOum8dGhFIL8BjjjyPpbARaXAWm5AOgU/SryXQ7ATnOBk1xaj4j4BAq9MuPiY0Me64Z//LDjY+7H4CFRDpc+VTiUcJNMPcbFiDLYJokeey667iHvrc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i/tw9UyR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i/tw9UyR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F1FF8C4CEF7; Wed, 13 Aug 2025 14:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755096950; bh=5v1d2ZPdszghDIrJGhbTRJ0+vB3QSvZx9Rmgr+KUWTs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i/tw9UyRi9WYAJpGYKFhq/mzhwsoJ9WvfHDmvHoORmD9os65C3G8v7G8n24guF39l +Ul0dpo0nlD7HyHP3LtVb+SZWbE535S8lmnQ8CLUkVnlKvK9KpInLx0xFvEXmsj2L8 zQM85epB76RtyEyelkpmpDJ4rgfCAknVgEb5G2P/F2N6bylYEvM7fKunH1d57hMNTA nkkM/PInbP33R62/RmZcV+eQSuajZ/mNwvdA/7pCMAj1kZVEBFTtbw/El6Me9CiYh+ pej+180DDPjBxq0ukp/6CpuidncOY0o7R/fXd7Hu/v61+5cUqhWT9bTU5cDuOY/JJQ UqZD7RENdW0hQ== Received: by wens.tw (Postfix, from userid 1000) id 610145FF91; Wed, 13 Aug 2025 22:55:45 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v2 10/10] arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port Date: Wed, 13 Aug 2025 22:55:40 +0800 Message-Id: <20250813145540.2577789-11-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250813145540.2577789-1-wens@kernel.org> References: <20250813145540.2577789-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200, is connected to an external Motorcomm YT8531 PHY. The PHY uses an external 25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and the PI16 pin for its interrupt pin. Enable it. Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index d07bb9193b43..b604d961c4fd 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ / { compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; =20 aliases { + ethernet0 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -95,11 +96,33 @@ &ehci1 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <0>; + rx-internal-delay-ps =3D <300>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts-extended =3D <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios =3D <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5