From nobody Mon Feb 9 05:22:42 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D75A02ED159; Wed, 13 Aug 2025 14:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096371; cv=none; b=BObjIKrm0rg8B5J1hbSMCm121799tKOL0LqwE4DX04C5KXpXz9RpUDy4spVcBI/pY5iVZVJqvtU08FAHm9Yd9KfOsH+NrZt35G25X63L7YUmYab23ivE9kZrNcuVsJh8pC8p00RSNxlZv1lV754p+5N0YE3Xmmb5fVi+jVDC8OY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096371; c=relaxed/simple; bh=Bx5xy4rdha8UlSfBmLumG1DN9a5yTYhdvdocUGB6vMo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cTu2qAaoWQGyyoqte2/+BqSAMIhSzNWHKWV+PCnT04Jvq80jZQF6hHH2dnrtGhLkSbHo7mhCfrJ8t5RrhlTAoQwexXsg2Kpjtf56mppI5Ckh3Ma0EuYhz1ylme938IVt9aCltWuh1ndZWOrbRjrCDtx1niYJGEDWGC5cK0lUi78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=exswT6AS; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="exswT6AS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=1K 2a590HEkP5ndEewvEUaYjFyB72wbqA06B8THOwEGM=; b=exswT6AStcYfHwliEv kBeG4cqDfFpwqhN0jk26teMz3KsSE5+ShXcs3fFpJfIxStY3EADE/pKAV+Zk7oAA XGKPZPrPnXcPUZp7EdE6g19n1AgIDfzx1IXuyru7zxGyO4iL3r+e5M+NL5oAHGEN +6fhXT6VK/0+VNbyBB+0MBPrI= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDHYosMpZxo4mzXAw--.28032S3; Wed, 13 Aug 2025 22:45:34 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, schnelle@linux.ibm.com, gbayer@linux.ibm.com, lukas@wunner.de, arnd@kernel.org, geert@linux-m68k.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v15 1/6] PCI: Clean up __pci_find_next_cap_ttl() readability Date: Wed, 13 Aug 2025 22:45:24 +0800 Message-Id: <20250813144529.303548-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250813144529.303548-1-18255117159@163.com> References: <20250813144529.303548-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDHYosMpZxo4mzXAw--.28032S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7tFyUuF4UZw1fZr48tF1fZwb_yoW8ZrWkpF 98CFyxArW8JF47Cw4v93WUAF13Xa4qy3y8GrW2gwn8uFy2yw18XwsI9Fy3tF12qrZ29F13 X3sIvryFgas0vaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pR_Ma5UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQxaoo2icmQX5igAAsF Content-Type: text/plain; charset="utf-8" Refactor the __pci_find_next_cap_ttl() to improve code clarity: - Replace magic number 0x40 with PCI_STD_HEADER_SIZEOF. - Use ALIGN_DOWN() for position alignment instead of manual bitmask. - Extract PCI capability fields via FIELD_GET() with standardized masks. - Add necessary headers (linux/align.h). No functional changes intended. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Manivannan Sadhasivam Reviewed-by: Gerd Bayer Tested-by: Niklas Schnelle --- drivers/pci/pci.c | 9 +++++---- include/uapi/linux/pci_regs.h | 3 +++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b0f4d98036cd..40a5c87d9a6b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,6 +9,7 @@ */ =20 #include +#include #include #include #include @@ -432,17 +433,17 @@ static u8 __pci_find_next_cap_ttl(struct pci_bus *bus= , unsigned int devfn, pci_bus_read_config_byte(bus, devfn, pos, &pos); =20 while ((*ttl)--) { - if (pos < 0x40) + if (pos < PCI_STD_HEADER_SIZEOF) break; - pos &=3D ~3; + pos =3D ALIGN_DOWN(pos, 4); pci_bus_read_config_word(bus, devfn, pos, &ent); =20 - id =3D ent & 0xff; + id =3D FIELD_GET(PCI_CAP_ID_MASK, ent); if (id =3D=3D 0xff) break; if (id =3D=3D cap) return pos; - pos =3D (ent >> 8); + pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); } return 0; } diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f5b17745de60..1bba99b46227 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -207,6 +207,9 @@ =20 /* Capability lists */ =20 +#define PCI_CAP_ID_MASK 0x00ff /* Capability ID mask */ +#define PCI_CAP_LIST_NEXT_MASK 0xff00 /* Next Capability Pointer mask */ + #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_ID_PM 0x01 /* Power Management */ #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ --=20 2.25.1 From nobody Mon Feb 9 05:22:42 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A3BF435977; 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arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="hKPUoxre" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=NE 5agrO+wh8mVH7mx5ud+4mDgDxVx9AkxXFBHODwjOk=; b=hKPUoxre8Y5mlZY4Y6 oE8KqNZ+iW8iDADFNBQHElBorv5DIirQvTpyeTxTgN+JbU7qh6OU28zDKmsYWs/W D7l5nHUiHqJFWi589z/2wAbRgrTLeg7V/hSQUf6Sm/Slvi6X6I69zwPTocCEyKxy mOor5uLu3lU2krPcwxkOMMHR4= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDHYosMpZxo4mzXAw--.28032S4; Wed, 13 Aug 2025 22:45:34 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, schnelle@linux.ibm.com, gbayer@linux.ibm.com, lukas@wunner.de, arnd@kernel.org, geert@linux-m68k.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v15 2/6] PCI: Refactor capability search into PCI_FIND_NEXT_CAP() Date: Wed, 13 Aug 2025 22:45:25 +0800 Message-Id: <20250813144529.303548-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250813144529.303548-1-18255117159@163.com> References: <20250813144529.303548-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDHYosMpZxo4mzXAw--.28032S4 X-Coremail-Antispam: 1Uf129KBjvJXoW3XrW7ZF1fZrWUAw1rCr4fAFb_yoW7XFW3pF ZxA3WayrW8G3W2qanIva1jkFyaqa97A3y2krW7Gwn8XFy2ka4vqa4ayF1aqFy2qrZ7CF17 Xws0qF1kG3WYyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEfHU9UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQxOoo2icmQX5iwABsA Content-Type: text/plain; charset="utf-8" The PCI Capability search functionality is duplicated across the PCI core and several controller drivers. The core's current implementation requires fully initialized PCI device and bus structures, which prevents controller drivers from using it during early initialization phases before these structures are available. Move the Capability search logic into a PCI_FIND_NEXT_CAP() macro that accepts a config space accessor function as an argument. This enables controller drivers to perform Capability discovery using their early access mechanisms prior to full device initialization while sharing the Capability search code. Convert the existing PCI core Capability search implementation to use PCI_FIND_NEXT_CAP(). Controller drivers can later use this with their early access mechanisms while maintaining the existing protection against infinite loops through preserved TTL checks. Signed-off-by: Hans Zhang <18255117159@163.com> Tested-by: Niklas Schnelle --- drivers/pci/pci.c | 42 ++++++++---------------------------------- drivers/pci/pci.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 34 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 40a5c87d9a6b..ac2658d946ea 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,7 +9,6 @@ */ =20 #include -#include #include #include #include @@ -424,36 +423,10 @@ static int pci_dev_str_match(struct pci_dev *dev, con= st char *p, return 1; } =20 -static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, - u8 pos, int cap, int *ttl) -{ - u8 id; - u16 ent; - - pci_bus_read_config_byte(bus, devfn, pos, &pos); - - while ((*ttl)--) { - if (pos < PCI_STD_HEADER_SIZEOF) - break; - pos =3D ALIGN_DOWN(pos, 4); - pci_bus_read_config_word(bus, devfn, pos, &ent); - - id =3D FIELD_GET(PCI_CAP_ID_MASK, ent); - if (id =3D=3D 0xff) - break; - if (id =3D=3D cap) - return pos; - pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); - } - return 0; -} - static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) { - int ttl =3D PCI_FIND_CAP_TTL; - - return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); + return PCI_FIND_NEXT_CAP(pci_bus_read_config, pos, cap, bus, devfn); } =20 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) @@ -649,7 +622,7 @@ EXPORT_SYMBOL_GPL(pci_get_dsn); =20 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) { - int rc, ttl =3D PCI_FIND_CAP_TTL; + int rc; u8 cap, mask; =20 if (ht_cap =3D=3D HT_CAPTYPE_SLAVE || ht_cap =3D=3D HT_CAPTYPE_HOST) @@ -657,8 +630,8 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u= 8 pos, int ht_cap) else mask =3D HT_5BIT_CAP_MASK; =20 - pos =3D __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, - PCI_CAP_ID_HT, &ttl); + pos =3D PCI_FIND_NEXT_CAP(pci_bus_read_config, pos, + PCI_CAP_ID_HT, dev->bus, dev->devfn); while (pos) { rc =3D pci_read_config_byte(dev, pos + 3, &cap); if (rc !=3D PCIBIOS_SUCCESSFUL) @@ -667,9 +640,10 @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, = u8 pos, int ht_cap) if ((cap & mask) =3D=3D ht_cap) return pos; =20 - pos =3D __pci_find_next_cap_ttl(dev->bus, dev->devfn, - pos + PCI_CAP_LIST_NEXT, - PCI_CAP_ID_HT, &ttl); + pos =3D PCI_FIND_NEXT_CAP(pci_bus_read_config, + pos + PCI_CAP_LIST_NEXT, + PCI_CAP_ID_HT, dev->bus, + dev->devfn); } =20 return 0; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 34f65d69662e..81580987509f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -2,6 +2,8 @@ #ifndef DRIVERS_PCI_H #define DRIVERS_PCI_H =20 +#include +#include #include =20 struct pcie_tlp_log; @@ -88,6 +90,49 @@ bool pcie_cap_has_lnkctl(const struct pci_dev *dev); bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); bool pcie_cap_has_rtctl(const struct pci_dev *dev); =20 +/* Standard Capability finder */ +/** + * PCI_FIND_NEXT_CAP - Find a PCI standard capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search + * @cap: Capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Search the capability list in PCI config space to find @cap. + * Implements TTL (time-to-live) protection against infinite loops. + * + * Return: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_CAP(read_cfg, start, cap, args...) \ +({ \ + int __ttl =3D PCI_FIND_CAP_TTL; \ + u8 __id, __found_pos =3D 0; \ + u8 __pos =3D (start); \ + u16 __ent; \ + \ + read_cfg##_byte(args, __pos, &__pos); \ + \ + while (__ttl--) { \ + if (__pos < PCI_STD_HEADER_SIZEOF) \ + break; \ + \ + __pos =3D ALIGN_DOWN(__pos, 4); \ + read_cfg##_word(args, __pos, &__ent); \ + \ + __id =3D FIELD_GET(PCI_CAP_ID_MASK, __ent); \ + if (__id =3D=3D 0xff) \ + break; \ + \ + if (__id =3D=3D (cap)) { \ + __found_pos =3D __pos; \ + break; \ + } \ + \ + __pos =3D FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ + } \ + __found_pos; \ +}) + /* Functions internal to the PCI core code */ =20 #ifdef CONFIG_DMI --=20 2.25.1 From nobody Mon Feb 9 05:22:42 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 239FC2F0680; Wed, 13 Aug 2025 14:46:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096372; cv=none; b=LUVUXHbMPvQWCiF1GAYTxZBIQLNZKrBrRE0ivR8CDjmhaC2o/N8HrQmglWA460T4XT6r4xit/O7TgTDyXc/MwcJ4NyFVaxu7GOL7TcYRAlGjYD/buCofaqqER7x8q0ZiCukm850HqxSLDoJ411qP9ZwB7FHyhMa3j7etbN8uwUk= ARC-Message-Signature: i=1; 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d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=0+ nzkjktRLVanoz16moHD5Kd1AcToEBpo22VbFhl3Lc=; b=QseZD5gY9mhHdOMLyI 52lb6Y+Fb7ImBxgnMLYQNZk1phAmy27TrWgBLnIukOrGF0qbJkMnxqnkrOlmzJjk OqrBOk/jRisUfHpUbucT+VtxlMBlDV+Z8EDptZZPoGBR7xCJCj/JIy8ZvKeNWg1n Ush2PdsLC0h8EnU4SOI6uWfdQ= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDHYosMpZxo4mzXAw--.28032S5; Wed, 13 Aug 2025 22:45:35 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, schnelle@linux.ibm.com, gbayer@linux.ibm.com, lukas@wunner.de, arnd@kernel.org, geert@linux-m68k.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v15 3/6] PCI: Refactor extended capability search into PCI_FIND_NEXT_EXT_CAP() Date: Wed, 13 Aug 2025 22:45:26 +0800 Message-Id: <20250813144529.303548-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250813144529.303548-1-18255117159@163.com> References: <20250813144529.303548-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDHYosMpZxo4mzXAw--.28032S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxXFyrtry3Ar48Zr4kCryxGrg_yoW5tr15p3 y3A3WSyryrJa12qwsIva1jgF1Ygan7CFW7WFWxG34rXFyDCw13Gr1fKaySgFy7trZruF1f XFs5AF4rC3ZxAF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zikhLnUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOg6oo2icmifhSgABsc Content-Type: text/plain; charset="utf-8" Move the extended Capability search logic into a PCI_FIND_NEXT_EXT_CAP() macro that accepts a config space accessor function as an argument. This enables controller drivers to perform Capability discovery using their early access mechanisms prior to full device initialization while sharing the Capability search code. Convert the existing PCI core extended Capability search implementation to use PCI_FIND_NEXT_EXT_CAP(). Signed-off-by: Hans Zhang <18255117159@163.com> Tested-by: Niklas Schnelle --- drivers/pci/pci.c | 35 ++--------------------------------- drivers/pci/pci.h | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ac2658d946ea..e698278229f2 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -527,42 +527,11 @@ EXPORT_SYMBOL(pci_bus_find_capability); */ u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) { - u32 header; - int ttl; - u16 pos =3D PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - if (dev->cfg_size <=3D PCI_CFG_SPACE_SIZE) return 0; =20 - if (start) - pos =3D start; - - if (pci_read_config_dword(dev, pos, &header) !=3D PCIBIOS_SUCCESSFUL) - return 0; - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header =3D=3D 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) =3D=3D cap && pos !=3D start) - return pos; - - pos =3D PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (pci_read_config_dword(dev, pos, &header) !=3D PCIBIOS_SUCCESSFUL) - break; - } - - return 0; + return PCI_FIND_NEXT_EXT_CAP(pci_bus_read_config, start, cap, + dev->bus, dev->devfn); } EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 81580987509f..7fb44faf2c44 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -133,6 +133,46 @@ bool pcie_cap_has_rtctl(const struct pci_dev *dev); __found_pos; \ }) =20 +/* Extended Capability finder */ +/** + * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability + * @read_cfg: Function pointer for reading PCI config space + * @start: Starting position to begin search (0 for initial search) + * @cap: Extended capability ID to find + * @args: Arguments to pass to read_cfg function + * + * Search the extended capability list in PCI config space to find @cap. + * Implements TTL protection against infinite loops using a calculated + * maximum search count. + * + * Return: Position of the capability if found, 0 otherwise. + */ +#define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, args...) \ +({ \ + u16 __pos =3D (start) ?: PCI_CFG_SPACE_SIZE; \ + u16 __found_pos =3D 0; \ + int __ttl, __ret; \ + u32 __header; \ + \ + __ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ + while (__ttl-- > 0 && __pos >=3D PCI_CFG_SPACE_SIZE) { \ + __ret =3D read_cfg##_dword(args, __pos, &__header); \ + if (__ret !=3D PCIBIOS_SUCCESSFUL) \ + break; \ + \ + if (__header =3D=3D 0) \ + break; \ + \ + if (PCI_EXT_CAP_ID(__header) =3D=3D (cap) && __pos !=3D start) {\ + __found_pos =3D __pos; \ + break; \ + } \ + \ + __pos =3D PCI_EXT_CAP_NEXT(__header); \ + } \ + __found_pos; \ +}) + /* Functions internal to the PCI core code */ =20 #ifdef CONFIG_DMI --=20 2.25.1 From nobody Mon Feb 9 05:22:42 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D4169194C96; Wed, 13 Aug 2025 14:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096371; cv=none; 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dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="fvUVJlQS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ez w+x6CPBZoj0Ns1BR+CJgZEtXO9GLRlu49I9UBWAjo=; b=fvUVJlQSa0Xz/B41nu peYEg5upAy/RF/pG9jgReYRCiZQwxHHACqGqBlWvvwesBjt6RQ0mXhSBXscpMxML VpGxcs036P6n6u4rUwt6bq5kcYNYG66Hg8QrrKFmz/HUK7q2mhCINNYSSSuG7oG3 KLYdKJbUKY+S+0ThQeLig5GKM= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDHYosMpZxo4mzXAw--.28032S6; Wed, 13 Aug 2025 22:45:36 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, schnelle@linux.ibm.com, gbayer@linux.ibm.com, lukas@wunner.de, arnd@kernel.org, geert@linux-m68k.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v15 4/6] PCI: dwc: Use PCI core APIs to find capabilities Date: Wed, 13 Aug 2025 22:45:27 +0800 Message-Id: <20250813144529.303548-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250813144529.303548-1-18255117159@163.com> References: <20250813144529.303548-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDHYosMpZxo4mzXAw--.28032S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxXFyUtF4xur13ZF4fKF1rJFb_yoWrCFyfpa y5JFyFyFWrAr4Yq3ZFv3Z8ZF13AF9xZFy7Ca97G3ZavFy2krWjg340krW3tr1xKrW2gry3 Kr4xtFyrCFnxJFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pil4EiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOgmoo2icmifhagAAs6 Content-Type: text/plain; charset="utf-8" The PCI core now provides generic PCI_FIND_NEXT_CAP() and PCI_FIND_NEXT_EXT_CAP() macros to search for PCI capabilities, using a config accessor we supply; use them in the DWC driver. Signed-off-by: Hans Zhang <18255117159@163.com> Tested-by: Niklas Schnelle --- drivers/pci/controller/dwc/pcie-designware.c | 77 ++------------------ drivers/pci/controller/dwc/pcie-designware.h | 21 ++++++ 2 files changed, 26 insertions(+), 72 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 89aad5a08928..5fe0744d4235 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -213,83 +213,16 @@ void dw_pcie_version_detect(struct dw_pcie *pci) pci->type =3D ver; } =20 -/* - * These interfaces resemble the pci_find_*capability() interfaces, but th= ese - * are for configuring host controllers, which are bridges *to* PCI device= s but - * are not PCI devices themselves. - */ -static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) -{ - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; - - reg =3D dw_pcie_readw_dbi(pci, cap_ptr); - cap_id =3D (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; - - if (cap_id =3D=3D cap) - return cap_ptr; - - next_cap_ptr =3D (reg & 0xff00) >> 8; - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); -} - u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { - u8 next_cap_ptr; - u16 reg; - - reg =3D dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr =3D (reg & 0x00ff); - - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, + pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); =20 -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, - u8 cap) -{ - u32 header; - int ttl; - int pos =3D PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl =3D (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos =3D start; - - header =3D dw_pcie_readl_dbi(pci, pos); - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header =3D=3D 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) =3D=3D cap && pos !=3D start) - return pos; - - pos =3D PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - header =3D dw_pcie_readl_dbi(pci, pos); - } - - return 0; -} - u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return dw_pcie_find_next_ext_capability(pci, 0, cap); + return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, pci); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); =20 @@ -302,8 +235,8 @@ static u16 __dw_pcie_find_vsec_capability(struct dw_pci= e *pci, u16 vendor_id, if (vendor_id !=3D dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) return 0; =20 - while ((vsec =3D dw_pcie_find_next_ext_capability(pci, vsec, - PCI_EXT_CAP_ID_VNDR))) { + while ((vsec =3D PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, vsec, + PCI_EXT_CAP_ID_VNDR, pci))) { header =3D dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); if (PCI_VNDR_HEADER_ID(header) =3D=3D vsec_id) return vsec; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 00f52d472dcd..b5e7e18138a6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -609,6 +609,27 @@ static inline void dw_pcie_writel_dbi2(struct dw_pcie = *pci, u32 reg, u32 val) dw_pcie_write_dbi2(pci, reg, 0x4, val); } =20 +static inline int dw_pcie_read_cfg_byte(struct dw_pcie *pci, int where, + u8 *val) +{ + *val =3D dw_pcie_readb_dbi(pci, where); + return PCIBIOS_SUCCESSFUL; +} + +static inline int dw_pcie_read_cfg_word(struct dw_pcie *pci, int where, + u16 *val) +{ + *val =3D dw_pcie_readw_dbi(pci, where); + return PCIBIOS_SUCCESSFUL; +} + +static inline int dw_pcie_read_cfg_dword(struct dw_pcie *pci, int where, + u32 *val) +{ + *val =3D dw_pcie_readl_dbi(pci, where); + return PCIBIOS_SUCCESSFUL; +} + static inline unsigned int dw_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep, u8 func_no) { --=20 2.25.1 From nobody Mon Feb 9 05:22:42 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 79F9F194C96; Wed, 13 Aug 2025 14:46:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755096365; cv=none; b=JLUEIy9GFk7gsNv8uz6nslsDeiGSLJqbhdKbz6DMpl6dkeyPQbIqiIhGbEYL2nILtZimao4y9uVMdutlMbvgR6uZB3A/RUiSrxa43WiWfpKEhUn0ErbpS/3ViFdT1xXEDfO7S1ovahvoQP3H6FSAxLnje+Qp75SXyh+ZeBIJEM0= ARC-Message-Signature: i=1; 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d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Aa J7ZYraUwva+Y2MbvzC03H7C9O4Dlcvf44pgcVRoCs=; b=TYq2u/nKJAjDO20rLc yNZ6q7BxfpmGHgXFQkcp7uwk50oJ55wtoQhjZzos11D3NQh8TvlY2tuPFYRf/DPL NJEKky2vJY26kQYZ1BAFSft/h4O8v9xd3huMXK7Tb9ZYTsmCLUiU5qo6JGPvLBHC cMPoxROKoWUewotpgrovAMJ4A= Received: from localhost.localdomain (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDHYosMpZxo4mzXAw--.28032S7; Wed, 13 Aug 2025 22:45:37 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, schnelle@linux.ibm.com, gbayer@linux.ibm.com, lukas@wunner.de, arnd@kernel.org, geert@linux-m68k.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v15 5/6] PCI: cadence: Use PCI core APIs to find capabilities Date: Wed, 13 Aug 2025 22:45:28 +0800 Message-Id: <20250813144529.303548-6-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250813144529.303548-1-18255117159@163.com> References: <20250813144529.303548-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDHYosMpZxo4mzXAw--.28032S7 X-Coremail-Antispam: 1Uf129KBjvJXoWxAryrtFy3WF47Zr47Ww1fXrb_yoW5CryrpF WDGFyfG3WrJFW3uFn3Za45Xr13tFnaka47ta92k34xZF17Cr4UGF1agFy3KF9xKrs7Xr17 X3yDtFyDGr13tFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pil4EiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhOoo2icmifhggAAsI Content-Type: text/plain; charset="utf-8" The PCI core now provides generic PCI_FIND_NEXT_CAP() and PCI_FIND_NEXT_EXT_CAP() macros to search for PCI capabilities, using a config accessor we supply; use them in the CDNS driver. Signed-off-by: Hans Zhang <18255117159@163.com> Tested-by: Niklas Schnelle --- drivers/pci/controller/cadence/pcie-cadence.c | 14 ++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 34 +++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 70a19573440e..c45585ae1746 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -8,6 +8,20 @@ #include =20 #include "pcie-cadence.h" +#include "../../pci.h" + +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_CAP(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST, + cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_capability); + +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) +{ + return PCI_FIND_NEXT_EXT_CAP(cdns_pcie_read_cfg, 0, cap, pcie); +} +EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); =20 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 1d81c4bf6c6d..71e203de1087 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -367,6 +367,37 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pc= ie, u32 reg) return readl(pcie->reg_base + reg); } =20 +static inline u16 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg) +{ + return readw(pcie->reg_base + reg); +} + +static inline u8 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg) +{ + return readb(pcie->reg_base + reg); +} + +static inline int cdns_pcie_read_cfg_byte(struct cdns_pcie *pcie, int wher= e, + u8 *val) +{ + *val =3D cdns_pcie_readb(pcie, where); + return PCIBIOS_SUCCESSFUL; +} + +static inline int cdns_pcie_read_cfg_word(struct cdns_pcie *pcie, int wher= e, + u16 *val) +{ + *val =3D cdns_pcie_readw(pcie, where); + return PCIBIOS_SUCCESSFUL; +} + +static inline int cdns_pcie_read_cfg_dword(struct cdns_pcie *pcie, int whe= re, + u32 *val) +{ + *val =3D cdns_pcie_readl(pcie, where); + return PCIBIOS_SUCCESSFUL; +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr =3D PTR_ALIGN_DOWN(addr, 0x4); @@ -536,6 +567,9 @@ static inline void cdns_pcie_ep_disable(struct cdns_pci= e_ep *ep) } #endif =20 +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); 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Wed, 13 Aug 2025 22:45:38 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, jingoohan1@gmail.com, mani@kernel.org Cc: robh@kernel.org, ilpo.jarvinen@linux.intel.com, schnelle@linux.ibm.com, gbayer@linux.ibm.com, lukas@wunner.de, arnd@kernel.org, geert@linux-m68k.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v15 6/6] PCI: cadence: Use cdns_pcie_find_*capability() to avoid hardcoding offsets Date: Wed, 13 Aug 2025 22:45:29 +0800 Message-Id: <20250813144529.303548-7-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250813144529.303548-1-18255117159@163.com> References: <20250813144529.303548-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDHYosMpZxo4mzXAw--.28032S8 X-Coremail-Antispam: 1Uf129KBjvJXoW3JF1rCrWfWF15ArWUXF18Xwb_yoWxAF45pF W5ua4SkF40qrW7uFsrA3W5ZrnxtFnIv347Aa92kw15uF129ryUGFyIva43KF1akrs7uF17 XrWDtrsa9a13trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pidHUhUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwyoo2icmrDSKwAAs7 The PCI capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Hence, use the cdns_pcie_find_{ext}_capability() APIs for finding them. This avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> Acked-by: Manivannan Sadhasivam Reviewed-by: Ilpo J=C3=A4rvinen Tested-by: Niklas Schnelle --- .../pci/controller/cadence/pcie-cadence-ep.c | 38 +++++++++++-------- drivers/pci/controller/cadence/pcie-cadence.h | 5 --- 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index 77c5a19b2ab1..5529ed84649f 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -21,12 +21,13 @@ =20 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) { - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 first_vf_offset, stride; + u16 cap; =20 if (vfn =3D=3D 0) return fn; =20 + cap =3D cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); fn =3D fn + first_vf_offset + ((vfn - 1) * stride); @@ -38,10 +39,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *ep= c, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie =3D &ep->pcie; u32 reg; + u16 cap; =20 + cap =3D cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); if (vfn > 1) { dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); return -EINVAL; @@ -227,9 +229,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u= 8 fn, u8 vfn, u8 nr_irqs) struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; u8 mmc =3D order_base_2(nr_irqs); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* @@ -249,9 +252,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u= 8 fn, u8 vfn) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Validate that the MSI feature is actually enabled. */ @@ -272,9 +276,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, = u8 func_no, u8 vfunc_no) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); =20 reg =3D cap + PCI_MSIX_FLAGS; @@ -292,9 +297,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, = u8 fn, u8 vfn, { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 reg =3D cap + PCI_MSIX_FLAGS; @@ -380,11 +386,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie= _ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; - u8 msi_count; u64 pci_addr, pci_addr_mask =3D 0xff; + u8 msi_count, cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -432,14 +438,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *e= pc, u8 fn, u8 vfn, u32 *msi_addr_offset) { struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; struct cdns_pcie *pcie =3D &ep->pcie; u64 pci_addr, pci_addr_mask =3D 0xff; u16 flags, mme, data, data_mask; - u8 msi_count; + u8 msi_count, cap; int ret; int i; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); =20 /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -482,16 +488,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *e= pc, u8 fn, u8 vfn, static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 v= fn, u16 interrupt_num) { - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 tbl_offset, msg_data, reg; struct cdns_pcie *pcie =3D &ep->pcie; struct pci_epf_msix_tbl *msix_tbl; struct cdns_pcie_epf *epf; u64 pci_addr_mask =3D 0xff; u64 msg_addr; + u8 bir, cap; u16 flags; - u8 bir; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); epf =3D &ep->epf[fn]; if (vfn > 0) epf =3D &epf->epf[vfn - 1]; @@ -565,7 +571,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) int max_epfs =3D sizeof(epc->function_num_map) * 8; int ret, epf, last_fn; u32 reg, value; + u8 cap; =20 + cap =3D cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP); /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. @@ -589,12 +597,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; =20 value =3D cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + cap + PCI_EXP_DEVCAP); value &=3D ~PCI_EXP_DEVCAP_FLR; cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + cap + PCI_EXP_DEVCAP, value); } } =20 diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 71e203de1087..84686b1493f2 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) =20 -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */ --=20 2.25.1