From nobody Sat Oct 4 19:17:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 26B352F83D4; Wed, 13 Aug 2025 12:01:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755086489; cv=none; b=Sq6gJzoIXnL0VWbFM1mLF50uqfKcjhAb8PhxSmTOjPKlOSs9bUA/cch97AyTy0T2HhY2iWpqjd7WWgRGnivgeH/ONSjubp9bUPg1fQG5GI9xI/TyVuwkgeoq5xRubZ6P4s9W0Su+Y5tkyCc+Lor+n9qTB2hYDx7MyAmgbMi2EP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755086489; c=relaxed/simple; bh=9zV77nEha+AzTcKTwOahPqFnp3HlP+R5XSNSAHflQ6U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=X/13ajld9ZZ+zPp5dsj2OFqOEHfeNAS7ILqH6m9MizO7u5Ozs+Jlh0eFvnWQIKPDruEgyAT8RUk/hFZOezz3Ii/GIa8q5WTqs+Npel21P0w+R8UQ1OffiailGSDLXd9fIapwAT9NoNfxtRK25LxOhWZVdeLQ/raRT5U3OTomkUU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8F69B14BF; Wed, 13 Aug 2025 05:01:19 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2DA733F5A1; Wed, 13 Aug 2025 05:01:24 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun , Marc Zyngier Subject: [PATCH v3 1/5] arm64: make SCTLR2_EL1 accessible Date: Wed, 13 Aug 2025 13:01:14 +0100 Message-Id: <20250813120118.3953541-2-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250813120118.3953541-1-yeoreum.yun@arm.com> References: <20250813120118.3953541-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the kernel runs at EL1, and yet is booted at EL2, HCRX_EL2.SCTLR2En must be set to avoid trapping SCTLR2_EL1 accesses from EL1 to EL2. Ensure this bit is set at the point of initialising EL2. Signed-off-by: Yeoreum Yun Reviewed-by: Marc Zyngier --- arch/arm64/include/asm/el2_setup.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 46033027510c..d755b4d46d77 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -57,9 +57,15 @@ /* Enable GCS if supported */ mrs_s x1, SYS_ID_AA64PFR1_EL1 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 - cbz x1, .Lset_hcrx_\@ + cbz x1, .Lskip_hcrx_GCSEn_\@ orr x0, x0, #HCRX_EL2_GCSEn =20 +.Lskip_hcrx_GCSEn_\@: + mrs_s x1, SYS_ID_AA64MMFR3_EL1 + ubfx x1, x1, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz x1, .Lset_hcrx_\@ + orr x0, x0, HCRX_EL2_SCTLR2En + .Lset_hcrx_\@: msr_s SYS_HCRX_EL2, x0 .Lskip_hcrx_\@: --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 4 19:17:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 144EC2FD1DB; Wed, 13 Aug 2025 12:01:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755086493; cv=none; b=Mf7V2m1Yg8MUV2R5TZX7O8W/kSXirNqYuBmxAt5ZzJXjfvNzwzDtXB5UyKs8eXJ7VzSw1JBMQAgkmh/Kzc6/R63jbl7T2LMmpJ8lhSa6iiryp+0E5pwje6+Xbc6ZtX5gZBu0jWoueTgZmKxs4BOTTVdIzp1gvkpBRN5x1DuQT8o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755086493; c=relaxed/simple; bh=1BQr4KWEuX9aN2KoDuV5IAf/milSiw/pUIR/ssp2a7Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RmSua//Jor9N8XLsCKd2moKaBugGfGX/FfoSpHejDUEH1K/bb4JnEsdOwb8vvh2YRts137GsPTV0i88fyagyvF6XAjEkvTVVpjjp/FXyNefougJwYkpBvbZeXTGGIahPIQJTEYAg2TguBDUV4kXsfGmGmcafHLdfx2Wci2HsnOE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 433ED175A; Wed, 13 Aug 2025 05:01:23 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 08BFD3F5A1; Wed, 13 Aug 2025 05:01:27 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v3 2/5] arm64: initialise SCTLR2_ELx register at boot time Date: Wed, 13 Aug 2025 13:01:15 +0100 Message-Id: <20250813120118.3953541-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250813120118.3953541-1-yeoreum.yun@arm.com> References: <20250813120118.3953541-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SCTLR2_ELx register is optional starting from ARMv8.8/ARMv9.3, and becomes mandatory from ARMv8.9/ARMv9.4 and serveral architectural feature are controled by bits in these registers. These register's value is UNKNOWN when it was reset It wasn't need to be initialised if firmware initilises these registers properly. But for the case not initialised properly, initialise SCTLR2_ELx registers at bootin cpu/vcpu so that unexpected system behavior couldn't happen for improper SCTLR2_ELx value. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/assembler.h | 22 ++++++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 6 ++++++ arch/arm64/include/asm/sysreg.h | 5 +++++ arch/arm64/kernel/head.S | 5 +++++ arch/arm64/kernel/hyp-stub.S | 10 ++++++++++ arch/arm64/kvm/hyp/nvhe/psci-relay.c | 3 +++ 6 files changed, 51 insertions(+) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index 23be85d93348..eef169c105f0 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -738,6 +738,28 @@ alternative_endif set_sctlr sctlr_el2, \reg .endm + /* + * Set SCTLR2_ELx to the @reg value. + */ + .macro __set_sctlr2_elx, el, reg, tmp + mrs_s \tmp, SYS_ID_AA64MMFR3_EL1 + ubfx \tmp, \tmp, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz \tmp, .Lskip_sctlr2_\@ + .if \el =3D=3D 2 + msr_s SYS_SCTLR_EL2, \reg + .elseif \el =3D=3D 12 + msr_s SYS_SCTLR_EL12, \reg + .else + msr_s SYS_SCTLR_EL1, \reg + .endif +.Lskip_sctlr2_\@: + .endm + + .macro set_sctlr2_elx, el, reg, tmp + __set_sctlr2_elx \el, \reg, \tmp + isb + .endm + /* * Check whether asm code should yield as soon as it is able. This is * the case if we are currently running in task context, and the diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index d755b4d46d77..c03cabd45fcf 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -48,6 +48,11 @@ isb .endm +.macro __init_sctlr2_el2 + mov_q x0, INIT_SCTLR2_EL2 + set_sctlr2_elx 2, x0, x1 +.endm + .macro __init_el2_hcrx mrs x0, id_aa64mmfr1_el1 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 @@ -411,6 +416,7 @@ */ .macro init_el2_state __init_el2_sctlr + __init_sctlr2_el2 __init_el2_hcrx __init_el2_timers __init_el2_debug diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index d5b5f2ae1afa..0431b357b87b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -868,6 +868,8 @@ #define INIT_SCTLR_EL2_MMU_OFF \ (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) +#define INIT_SCTLR2_EL2 UL(0) + /* SCTLR_EL1 specific flags. */ #ifdef CONFIG_CPU_BIG_ENDIAN #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) @@ -888,6 +890,8 @@ SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) +#define INIT_SCTLR2_EL1 UL(0) + /* MAIR_ELx memory attributes (used by Linux) */ #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) @@ -1164,6 +1168,7 @@ msr hcr_el2, \reg #endif .endm + #else #include diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index ca04b338cb0d..c41015675eae 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -276,6 +276,8 @@ SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) mov_q x0, INIT_SCTLR_EL1_MMU_OFF pre_disable_mmu_workaround msr sctlr_el1, x0 + mov_q x0, INIT_SCTLR2_EL1 + __set_sctlr2_elx 1, x0, x1 isb mov_q x0, INIT_PSTATE_EL1 msr spsr_el1, x0 @@ -308,6 +310,7 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) isb mov_q x1, INIT_SCTLR_EL1_MMU_OFF + mov_q x2, INIT_SCTLR2_EL1 mrs x0, hcr_el2 and x0, x0, #HCR_E2H @@ -315,11 +318,13 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) /* Set a sane SCTLR_EL1, the VHE way */ msr_s SYS_SCTLR_EL12, x1 + __set_sctlr2_elx 12, x2, x0 mov x2, #BOOT_CPU_FLAG_E2H b 3f 2: msr sctlr_el1, x1 + __set_sctlr2_elx 1, x2, x0 mov x2, xzr 3: mov x0, #INIT_PSTATE_EL1 diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index 36e2d26b54f5..ac12f1b4f8e2 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -144,7 +144,17 @@ SYM_CODE_START_LOCAL(__finalise_el2) .Lskip_indirection: .Lskip_tcr2: + mrs_s x1, SYS_ID_AA64MMFR3_EL1 + ubfx x1, x1, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz x1, .Lskip_sctlr2 + mrs_s x1, SYS_SCTLR2_EL12 + msr_s SYS_SCTLR2_EL1, x1 + // clean SCTLR2_EL1 + mov_q x1, INIT_SCTLR2_EL1 + msr_s SYS_SCTLR2_EL12, x1 + +.Lskip_sctlr2: isb // Hack the exception return to stay at EL2 diff --git a/arch/arm64/kvm/hyp/nvhe/psci-relay.c b/arch/arm64/kvm/hyp/nvhe= /psci-relay.c index c3e196fb8b18..4ed4b7fa57c2 100644 --- a/arch/arm64/kvm/hyp/nvhe/psci-relay.c +++ b/arch/arm64/kvm/hyp/nvhe/psci-relay.c @@ -4,6 +4,7 @@ * Author: David Brazdil */ +#include #include #include #include @@ -219,6 +220,8 @@ asmlinkage void __noreturn __kvm_host_psci_cpu_entry(bo= ol is_cpu_on) release_boot_args(boot_args); write_sysreg_el1(INIT_SCTLR_EL1_MMU_OFF, SYS_SCTLR); + if (alternative_has_cap_unlikely(ARM64_HAS_SCTLR2)) + write_sysreg_el1(INIT_SCTLR2_EL1, SYS_SCTLR2); write_sysreg(INIT_PSTATE_EL1, SPSR_EL2); __host_enter(host_ctxt); -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 4 19:17:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A26522FD1DB; Wed, 13 Aug 2025 12:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755086497; cv=none; b=VWDqprd8z6daY89NgtYZ7qREdSJj9CSJGCB8jcrZgr2MZ0mP/HOKRjj2IQefdFYzaNlV5/aENJPEDzxg8LdB9+OWITT2Kxgu9u0lKSTJmv6kHebAAYsOfsTI31/Lo9rFDOpzOt75c6vdeFux+0eQTwgn0vEDH0VbHVaDOJU9DEg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755086497; c=relaxed/simple; bh=VxeLWNVEZRUcSCDmjWrjuOceVIFpt1l7BL6suc1u/B4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SGzqH9F/5niSZ++zK5X6RFvmaVa4E5B9Na1tOsi1SQncJ5BJgTburxLdgv/NTge31cVSmwbs7YWKnInfdeefF1ydcOOmN12WfHNnEF+D4d7RAFROQ1HuPk0IFNQ1sUQBmhKfM84AMKCaUsH6/HUSMik8AhUSny218XjF7afpacs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E731012FC; Wed, 13 Aug 2025 05:01:26 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B050D3F5A1; Wed, 13 Aug 2025 05:01:31 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v3 3/5] arm64: save/restore SCTLR2_EL1 when cpu_suspend()/resume() Date: Wed, 13 Aug 2025 13:01:16 +0100 Message-Id: <20250813120118.3953541-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250813120118.3953541-1-yeoreum.yun@arm.com> References: <20250813120118.3953541-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SCTLR2_EL1 register is optional starting from ARMv8.8/ARMv9.3, and becomes mandatory from ARMv8.9/ARMv9.4 and serveral architectural feature are controled by bits in these registers (i.e) FEAT_PAuth_LR or FEAT_CPA/CPA2 Save and restore SCTLR2_EL1 when cpu_suspend() and resume(). so that configured value can sustain consistency before suspend and after resume. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/suspend.h | 2 +- arch/arm64/mm/proc.S | 26 ++++++++++++++++++-------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/suspend.h b/arch/arm64/include/asm/susp= end.h index 0cde2f473971..eb60c9735553 100644 --- a/arch/arm64/include/asm/suspend.h +++ b/arch/arm64/include/asm/suspend.h @@ -2,7 +2,7 @@ #ifndef __ASM_SUSPEND_H #define __ASM_SUSPEND_H =20 -#define NR_CTX_REGS 13 +#define NR_CTX_REGS 14 #define NR_CALLEE_SAVED_REGS 12 =20 /* diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 8c75965afc9e..f297bea7103b 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -87,8 +87,14 @@ SYM_FUNC_START(cpu_do_suspend) mrs x9, mdscr_el1 mrs x10, oslsr_el1 mrs x11, sctlr_el1 - get_this_cpu_offset x12 - mrs x13, sp_el0 +alternative_if_not ARM64_HAS_SCTLR2 + mov x12, xzr +alternative_else + mrs_s x12, SYS_SCTLR2_EL1 +alternative_endif + get_this_cpu_offset x13 + mrs x14, sp_el0 + stp x2, x3, [x0] stp x4, x5, [x0, #16] stp x6, x7, [x0, #32] @@ -99,7 +105,7 @@ SYM_FUNC_START(cpu_do_suspend) * Save x18 as it may be used as a platform register, e.g. by shadow * call stack. */ - str x18, [x0, #96] + stp x14, x18, [x0, #96] ret SYM_FUNC_END(cpu_do_suspend) =20 @@ -120,8 +126,8 @@ SYM_FUNC_START(cpu_do_resume) * the buffer to minimize the risk of exposure when used for shadow * call stack. */ - ldr x18, [x0, #96] - str xzr, [x0, #96] + ldp x15, x18, [x0, #96] + str xzr, [x0, #104] msr tpidr_el0, x2 msr tpidrro_el0, x3 msr contextidr_el1, x4 @@ -136,8 +142,12 @@ SYM_FUNC_START(cpu_do_resume) msr mdscr_el1, x10 =20 msr sctlr_el1, x12 - set_this_cpu_offset x13 - msr sp_el0, x14 +alternative_if ARM64_HAS_SCTLR2 + msr_s SYS_SCTLR2_EL1, x13 +alternative_else_nop_endif + + set_this_cpu_offset x14 + msr sp_el0, x15 /* * Restore oslsr_el1 by writing oslar_el1 */ @@ -151,7 +161,7 @@ alternative_if ARM64_HAS_RAS_EXTN msr_s SYS_DISR_EL1, xzr alternative_else_nop_endif =20 - ptrauth_keys_install_kernel_nosync x14, x1, x2, x3 + ptrauth_keys_install_kernel_nosync x15, x1, x2, x3 isb ret SYM_FUNC_END(cpu_do_resume) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 4 19:17:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 674122FD1DB; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A8EF514BF; Wed, 13 Aug 2025 05:01:30 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 638FF3F5A1; Wed, 13 Aug 2025 05:01:35 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v3 4/5] arm64: initialise SCTLR2_EL1 at cpu_soft_restart() Date: Wed, 13 Aug 2025 13:01:17 +0100 Message-Id: <20250813120118.3953541-5-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250813120118.3953541-1-yeoreum.yun@arm.com> References: <20250813120118.3953541-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SCTLR2_EL1 register is optional starting from ARMv8.8/ARMv9.3, and becomes mandatory from ARMv8.9/ARMv9.4 and serveral architectural feature are controled by bits in these registers. Before, launching new kernel via kexec, initialise SCTLR2_EL1 explicitly. Signed-off-by: Yeoreum Yun --- arch/arm64/kernel/cpu-reset.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/cpu-reset.S b/arch/arm64/kernel/cpu-reset.S index c87445dde674..123564af345b 100644 --- a/arch/arm64/kernel/cpu-reset.S +++ b/arch/arm64/kernel/cpu-reset.S @@ -37,6 +37,12 @@ SYM_TYPED_FUNC_START(cpu_soft_restart) * regime if HCR_EL2.E2H =3D=3D 1 */ msr sctlr_el1, x12 + +alternative_if ARM64_HAS_SCTLR2 + mov_q x12, INIT_SCTLR2_EL1 + msr_s SYS_SCTLR2_EL1, x12 +alternative_else_nop_endif + isb =20 cbz x0, 1f // el2_switch? --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 4 19:17:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E05382FE59E; Wed, 13 Aug 2025 12:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755086504; cv=none; b=UaD0SHUTMdwkH1d8GbZE3EykxLVVkoitpoYblZm3YvDH6o2v4N8O9s6ED8w0hAdLXz1eAgT3RYIEOR1VVUVyCcK0SFKyufJexzzNy4PABvd8rYv9Yv+zqMRRU1i+DSPpB3Mlf1KMVadFoACI3mi1KfBzbgeswY8VVgghkJpbA70= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755086504; c=relaxed/simple; bh=jvrnSFo2RTnrxOsEOCw0HxS3H2GPEPcK5sDoiCpspPI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DCO+u0sKhm4O/deW+5m/gzPy28/vCnuuF7LUf+DbgodhdfVPy7HhgyQ/YXbfuUprni2sSuuRfGiaIXL2oPnRcO2PpML3UvhZoCmYjQuUY4fXYrJ116o4prPm5JlGwPbhv3tBzDO+j86dwErVLYkHG/Ves43nP7jfS6pdryNko0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5758312FC; Wed, 13 Aug 2025 05:01:34 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 204DA3F5A1; Wed, 13 Aug 2025 05:01:39 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v3 5/5] arm64: make the per-task SCTLR2_EL1 Date: Wed, 13 Aug 2025 13:01:18 +0100 Message-Id: <20250813120118.3953541-6-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250813120118.3953541-1-yeoreum.yun@arm.com> References: <20250813120118.3953541-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SCTLR2_EL1 register is optional starting from ARMv8.8/ARMv9.3, and becomes mandatory from ARMv8.9/ARMv9.4 and serveral architectural feature are controled by bits in these registers and some of bits could be configurable per task not globally -- i.e) FEAT_CPA2 related field and etc. For future usage of these fields, make the per-task SCTLR2_EL1. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/processor.h | 5 +++++ arch/arm64/kernel/process.c | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/pr= ocessor.h index 61d62bfd5a7b..2c962816de70 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -184,6 +184,7 @@ struct thread_struct { u64 mte_ctrl; #endif u64 sctlr_user; + u64 sctlr2_user; u64 svcr; u64 tpidr2_el0; u64 por_el0; @@ -258,6 +259,9 @@ static inline void task_set_sve_vl_onexec(struct task_s= truct *task, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \ SCTLR_EL1_TCF0_MASK) =20 +#define SCTLR2_USER_MASK \ + (SCTLR2_EL1_EnPACM0 | SCTLR2_EL1_CPTA0 | SCTLR2_EL1_CPTM0) + static inline void arch_thread_struct_whitelist(unsigned long *offset, unsigned long *size) { @@ -370,6 +374,7 @@ struct task_struct; unsigned long __get_wchan(struct task_struct *p); =20 void update_sctlr_el1(u64 sctlr); +void update_sctlr2_el1(u64 sctlr2); =20 /* Thread switching */ extern struct task_struct *cpu_switch_to(struct task_struct *prev, diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 96482a1412c6..9191180c4875 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -698,6 +698,11 @@ void update_sctlr_el1(u64 sctlr) isb(); } =20 +void update_sctlr2_el1(u64 sctlr2) +{ + sysreg_clear_set_s(SYS_SCTLR2_EL1, SCTLR2_USER_MASK, sctlr2); +} + /* * Thread switching. */ @@ -737,6 +742,10 @@ struct task_struct *__switch_to(struct task_struct *pr= ev, if (prev->thread.sctlr_user !=3D next->thread.sctlr_user) update_sctlr_el1(next->thread.sctlr_user); =20 + if (alternative_has_cap_unlikely(ARM64_HAS_SCTLR2) && + prev->thread.sctlr2_user !=3D next->thread.sctlr2_user) + update_sctlr2_el1(next->thread.sctlr2_user); + /* the actual thread switch */ last =3D cpu_switch_to(prev, next); =20 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}