From nobody Sat Oct 4 21:05:29 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96D662F658E for ; Wed, 13 Aug 2025 09:53:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755078795; cv=none; b=J3y6ZbDYe86aqiu4bQO6iCcMGcLUHSDr0CJGJSbbFp7gZPM9M4iwQglDRAxl8CevRh1XX+cXIgawGDoloiL3Ob5PmBbd7gPHipkBhQq9qRMsTitK2qS62UOPBNGxDQ0MzXX0ZAjl+9jYjxVVB42VkMqM7ZQ7UkI9zH9/tUnvOGU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755078795; c=relaxed/simple; bh=bCPnPk8DP+Q1cTCB7jiXs25Tbp5TiN+Lk0oHK7xXvMo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Hot90fy4rcL5ICqnm6fFv+kmWkv64RMWaXJ5t4AXtyyELoVaJmLShfVXCNwT6QsxaoKfI5U9/0xgt58LcPxtGefr58TBHkvh1acMEJOJbD9g3h5oBa+2niydqdCqH9TO/EOUnZY/Hz/9ZJdg1VkmHl9dkufH/5TagpnFO4F8uZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4c23TS2j4cz14MRQ; Wed, 13 Aug 2025 17:48:12 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id C220A18049D; Wed, 13 Aug 2025 17:53:11 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 13 Aug 2025 17:53:10 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 13 Aug 2025 17:53:09 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 drm-dp 10/11] drm/hisilicon/hibmc: Adding reset colorbar cfg in dp init. Date: Wed, 13 Aug 2025 17:42:37 +0800 Message-ID: <20250813094238.3722345-11-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250813094238.3722345-1-shiyongbang@huawei.com> References: <20250813094238.3722345-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Baihan Li Add colorbar disable operation before reset controller, to make sure colorbar status is clear in the DP init, so if rmmod the driver and the previous colorbar configuration will not affect the next time insmod the driver. Fixes: 3c7623fb5bb6 ("drm/hisilicon/hibmc: Enable this hot plug detect of i= rq feature") Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi Reviewed-by: Dmitry Baryshkov --- ChangeLog: v3 -> v4: - fix the commit subject, suggested by Dmitry Baryshkov. v2 -> v3: - fix the issue commit ID, suggested by Dmitry Baryshkov. - split into 2 commits, suggested by Dmitry Baryshkov. - add more comments in commit log, suggested by Dmitry Baryshkov. --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index 77aacf09b1f8..18beef71d85f 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -181,6 +181,8 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) /* int init */ writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); + /* clr colorbar */ + writel(0, dp_dev->base + HIBMC_DP_COLOR_BAR_CTRL); /* rst */ writel(0, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); usleep_range(30, 50); --=20 2.33.0