From nobody Sat Oct 4 21:05:30 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 986822F6590 for ; Wed, 13 Aug 2025 09:53:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755078795; cv=none; b=a5p5nEIW/RAbzsNNMkmi5zR9Db2tgTJyvpP4wEN1apR4royScUZPTYuHCmVWiAUXab7DJP5Ra+Y0QDezEdufME51rqf85Hc6h39OzJyhXWyfFLpQWGTx0T9fCn9/N/JsMeZHHkTvqqfw2LQfjUFcFAQWneqLGydQVUunLn+O81Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755078795; c=relaxed/simple; bh=IOKZvq85pg4gxo+aA6QwREFdp/g0Y/zFI734NA21xWQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qUlxKrQfF8oOn4TZnmxUV9j38QLklG8RnR6uq0rPdOm+e36vhRcxTJhNLLMlQBk2vOyt5juYYf3P3uyZ/hgr46/ta0BoQheXdVUXxYEDwpmsgj0u4TCxSYh0td7rXI5FuKR4MnJ0ER4v/7Lwq/g0TNmxbbhgL8QV1qAon6pve4o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4c23TS2S5lz14MQt; Wed, 13 Aug 2025 17:48:12 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id BAEB5180495; Wed, 13 Aug 2025 17:53:11 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 13 Aug 2025 17:53:10 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 13 Aug 2025 17:53:09 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 drm-dp 09/11] drm/hisilicon/hibmc: fix no showing problem with loading hibmc manually Date: Wed, 13 Aug 2025 17:42:36 +0800 Message-ID: <20250813094238.3722345-10-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250813094238.3722345-1-shiyongbang@huawei.com> References: <20250813094238.3722345-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200002.china.huawei.com (7.221.188.68) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Baihan Li When using command rmmod and insmod, there is no showing in second time insmoding. Because DP controller won't send HPD signals, if connection doesn't change or controller isn't reset. So add reset before unreset in hibmc_dp_hw_init(). Fixes: 3c7623fb5bb6 ("drm/hisilicon/hibmc: Enable this hot plug detect of i= rq feature") Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi Reviewed-by: Dmitry Baryshkov --- ChangeLog: v2 -> v3: - fix the issue commit ID, suggested by Dmitry Baryshkov. --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index f8e1b437c385..77aacf09b1f8 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -182,6 +182,8 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); /* rst */ + writel(0, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); + usleep_range(30, 50); writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); /* clock enable */ writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL); --=20 2.33.0