From nobody Tue Dec 16 06:04:51 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0BD62D46D1; Wed, 13 Aug 2025 06:33:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755066794; cv=none; b=F5UcJbDeVF8ENrqhYLoRz8SHh3+Jc6Vpo6Ls+rF79qqZgBcREmDyfBOfIUoy6WMoByTCvfve+lXhsAaOQeDiYqutifKTZoApP4THq5ioG03U6mDhpUvro2gwSVM6X6SqPfFwvX9cCH1pEjyzy2xciRuSJEkdLM009hTuUxRs3Jg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755066794; c=relaxed/simple; bh=j4YAxQn2KRUaeEamaRjZGZdiY1KOc3QEORdou34sN9E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L17lolrb7UBJxYKuflMBgnFdehoWtHVwYan4vXLZaVH2//Ezs/2WZPlBXrnszf1pc+46Kji13aOUVJ9szcDgo+1mdiin393WrIW9FTO1Wt9WrPtvOES0wj13/PIGGcOtivCyluAMK6oldiGHnygAmo+Mw4TE9q8T3f1zTPyLJ/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 13 Aug 2025 14:33:01 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 13 Aug 2025 14:33:01 +0800 From: Jacky Chou To: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery CC: Simon Horman , Heiner Kallweit , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Po-Yu Chuang , , , , , , , Subject: [net-next v2 3/4] ARM: dts: aspeed: ast2600evb: Add delay setting for MAC Date: Wed, 13 Aug 2025 14:33:00 +0800 Message-ID: <20250813063301.338851-4-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250813063301.338851-1-jacky_chou@aspeedtech.com> References: <20250813063301.338851-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We use the rx-internal-delay-ps and the tx-internal-delay-ps to configure the RGMII delay. And change the phy_mode of MAC0 and MAC1 to "rgmii-id" to enable the TX/RX internal delay on PHY side. MAC0 and MAC1 configure on the edge delay. Keep the phy_mode of MAC2 and MAC3 to "rgmii". The RGMII delay of MAC2 and MAC3 can generate the delay to meet clock center, so we just add the delay property to let driver to configure 2ns delay. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts b/arch/arm/boo= t/dts/aspeed/aspeed-ast2600-evb.dts index de83c0eb1d6e..dc4d437a39ed 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts @@ -123,22 +123,28 @@ ethphy3: ethernet-phy@0 { &mac0 { status =3D "okay"; =20 - phy-mode =3D "rgmii-rxid"; + phy-mode =3D "rgmii-id"; phy-handle =3D <ðphy0>; =20 pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_rgmii1_default>; + + rx-internal-delay-ps =3D <0>; + tx-internal-delay-ps =3D <0>; }; =20 =20 &mac1 { status =3D "okay"; =20 - phy-mode =3D "rgmii-rxid"; + phy-mode =3D "rgmii-id"; phy-handle =3D <ðphy1>; =20 pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_rgmii2_default>; + + rx-internal-delay-ps =3D <0>; + tx-internal-delay-ps =3D <0>; }; =20 &mac2 { @@ -149,6 +155,9 @@ &mac2 { =20 pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_rgmii3_default>; + + rx-internal-delay-ps =3D <2000>; + tx-internal-delay-ps =3D <2000>; }; =20 &mac3 { @@ -159,6 +168,9 @@ &mac3 { =20 pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_rgmii4_default>; + + rx-internal-delay-ps =3D <2000>; + tx-internal-delay-ps =3D <2000>; }; =20 &emmc_controller { --=20 2.43.0