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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id AD2244143A8D; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 06/13] PCI: cadence: Split the common functions for PCIe controller support Date: Wed, 13 Aug 2025 12:23:24 +0800 Message-ID: <20250813042331.1258272-7-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C7:EE_|KU2PPF1A2CB34C0:EE_ X-MS-Office365-Filtering-Correlation-Id: 152ac205-c07c-4c7e-5b41-08ddda21aa59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?E9KQKkj87Lw6q/IYIPwU6TGZy3+rX5JGiKhTnULH/60U/VCIoiVTYttRzt2Y?= =?us-ascii?Q?A3R2/W1Tp+oBDr/5nyLi+mX4lEPLcfI3J+chx/3sK0PmZnBBCaEu+FGfLVCt?= =?us-ascii?Q?66BvByx6bwTnUrkNRDQxt0votId3r2OlS2QvHCcTfn7wV0UNmxKuyMWUBUsC?= =?us-ascii?Q?ElY7nLb+zd7AJQudwrIzkd1vUMmaxz7V3ehd8lE4/7GFrB/L1M5i5hxHQYjd?= =?us-ascii?Q?1xW9e/J2PRPpFmPJZjfL+FWbaIAvQyKcdLxilhzqSlhTcrewtskHj1Lpw6wk?= =?us-ascii?Q?ZwuRmrlTl8uKJPG/oKjx7PtL1G+pZk6nd5o2K488/b2khlwPqpn2iyWGkP87?= =?us-ascii?Q?/T63eFcsf5BehJiKmWD0pjLyBm1NJdRbmpA8RGFhWgWhWbBr2vA2OfXgN535?= =?us-ascii?Q?8DKLnckuXwZHsB+YvHkp8iBruQa06NBLiJcXdXYtzsTGbER5LKDDwzgrxJKG?= =?us-ascii?Q?JdOi0z9rszq0vVZmvIn3VMh7SgmaKakMs2piMFnD/VEXIktdPyLcRMEQTBSb?= =?us-ascii?Q?evAKIPfI66eOWlNMG0svV+2YGlBexbLq4xsdDE/L5/Vf3BAz1aS1Avt0iwRr?= =?us-ascii?Q?0hniDRIhk+ULvJLkjaPJeBYfXNVMgmwWhotUGkFPbx4yUssUWmMTeG4kmurz?= =?us-ascii?Q?QMR8cHfErOaKYuXyIwH1kgaIkAolwXNBeecVXlJUB8jODa9jrST8ga/GcvsL?= =?us-ascii?Q?GYF1zhuWOxaHWi5MPE15hSJixYy0YsEbOyAIFampMsjVkaXBONNZA0W0GFrT?= =?us-ascii?Q?PTFV+0KB6DjFsIcHzwwf8Fl+OdiBiP+jNzKmSCf5GelqTDyB2XKQzDE4Fkbn?= =?us-ascii?Q?ZFm1mrYJf5LnFX60n/PFy5LQZLrRzHa3QIq77mxvg5tOQMaR0zPz3QC4S8HD?= =?us-ascii?Q?d1dzNtJXMVh48wvlUIs6sqOuJcevXZNZUeBP3+OREKnQMFCNR/usWt9umI0x?= =?us-ascii?Q?gbMQ8qiy0QS4uBpC9MbysxhJF5w61Oe/9LJ1RCWHsrwJqBa/MRAOj+8mHwed?= =?us-ascii?Q?70XUYUKfQWopV3RL9estEoNnw1KHeVbotOsExoLnw7gM6PFOGRUYnp6RuZU2?= =?us-ascii?Q?2JeOY/CGm6ta5umO0OQsJWses3xBo/dpGe61gSi1lH6vIrgJRecNSixySgYt?= =?us-ascii?Q?ZHKyI62kBQ2zhH63/x5BD99zpujXfqlEZB6Li8Kl/1Yx6pUWwNrPuDoLOxBk?= =?us-ascii?Q?iNDefe0ZZXu+AiAhxoOHU2prlh0fB1+lyQtDQPKu5t8GIHPMf07CA5cvf/vX?= =?us-ascii?Q?YFiG7vZ9ecpr22YmpvuJiP/CioqYDUZxvqWOFC+a78/IOAcMLRyMQhshzrlE?= =?us-ascii?Q?PpbjhzR2TFHzWAnL4AyYg50g16UY9Twm1sbrnbVgdwPqoDV/fzm6hX+cg3vX?= =?us-ascii?Q?kBBmYKiW07ErWqK7hoSE98JTBXgvWbT+YecpsnMQNzq+MgZI8mGZrmsyCOty?= =?us-ascii?Q?ZVTek7xu6gcemnfneT0iTlrcn2uIRl/eP3h8HHj8duaAshw4nxkVIb+1h0G0?= =?us-ascii?Q?zIFCmyrIVK3opSGTyM0uHUbwyKfHbnloDm28?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:08.1133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 152ac205-c07c-4c7e-5b41-08ddda21aa59 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C7.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KU2PPF1A2CB34C0 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Separate the functions for platform specific tasks and common library tasks into different files. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../controller/cadence/pcie-cadence-common.c | 142 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.c | 129 ---------------- 3 files changed, 143 insertions(+), 130 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-common.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index e45f72388bbb..b104562fb86a 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-common.o pcie-caden= ce-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-common.c b/drivers= /pci/controller/cadence/pcie-cadence-common.c new file mode 100644 index 000000000000..23c5ab6637fb --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-common.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#include +#include + +#include "pcie-cadence.h" + +void cdns_pcie_disable_phy(struct cdns_pcie *pcie) +{ + int i =3D pcie->phy_count; + + while (i--) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } +} +EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); + +int cdns_pcie_enable_phy(struct cdns_pcie *pcie) +{ + int ret; + int i; + + for (i =3D 0; i < pcie->phy_count; i++) { + ret =3D phy_init(pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret =3D phy_power_on(pcie->phy[i]); + if (ret < 0) { + phy_exit(pcie->phy[i]); + goto err_phy; + } + } + + return 0; + +err_phy: + while (--i >=3D 0) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); + +int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) +{ + struct device_node *np =3D dev->of_node; + int phy_count; + struct phy **phy; + struct device_link **link; + int i; + int ret; + const char *name; + + phy_count =3D of_property_count_strings(np, "phy-names"); + if (phy_count < 1) { + dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); + pcie->phy_count =3D 0; + return 0; + } + + phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); + if (!link) + return -ENOMEM; + + for (i =3D 0; i < phy_count; i++) { + of_property_read_string_index(np, "phy-names", i, &name); + phy[i] =3D devm_phy_get(dev, name); + if (IS_ERR(phy[i])) { + ret =3D PTR_ERR(phy[i]); + goto err_phy; + } + link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); + if (!link[i]) { + devm_phy_put(dev, phy[i]); + ret =3D -EINVAL; + goto err_phy; + } + } + + pcie->phy_count =3D phy_count; + pcie->phy =3D phy; + pcie->link =3D link; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) + goto err_phy; + + return 0; + +err_phy: + while (--i >=3D 0) { + device_link_del(link[i]); + devm_phy_put(dev, phy[i]); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); + +static int cdns_pcie_suspend_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + + cdns_pcie_disable_phy(pcie); + + return 0; +} + +static int cdns_pcie_resume_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + int ret; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable PHY\n"); + return ret; + } + + return 0; +} + +const struct dev_pm_ops cdns_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, + cdns_pcie_resume_noirq) +}; +EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 5603f214f4c7..51c9bc4eb174 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -152,135 +152,6 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie= *pcie, u32 r) } EXPORT_SYMBOL_GPL(cdns_pcie_reset_outbound_region); =20 -void cdns_pcie_disable_phy(struct cdns_pcie *pcie) -{ - int i =3D pcie->phy_count; - - while (i--) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } -} -EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); - -int cdns_pcie_enable_phy(struct cdns_pcie *pcie) -{ - int ret; - int i; - - for (i =3D 0; i < pcie->phy_count; i++) { - ret =3D phy_init(pcie->phy[i]); - if (ret < 0) - goto err_phy; - - ret =3D phy_power_on(pcie->phy[i]); - if (ret < 0) { - phy_exit(pcie->phy[i]); - goto err_phy; - } - } - - return 0; - -err_phy: - while (--i >=3D 0) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); - -int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) -{ - struct device_node *np =3D dev->of_node; - int phy_count; - struct phy **phy; - struct device_link **link; - int i; - int ret; - const char *name; - - phy_count =3D of_property_count_strings(np, "phy-names"); - if (phy_count < 1) { - dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); - pcie->phy_count =3D 0; - return 0; - } - - phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); - if (!link) - return -ENOMEM; - - for (i =3D 0; i < phy_count; i++) { - of_property_read_string_index(np, "phy-names", i, &name); - phy[i] =3D devm_phy_get(dev, name); - if (IS_ERR(phy[i])) { - ret =3D PTR_ERR(phy[i]); - goto err_phy; - } - link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); - if (!link[i]) { - devm_phy_put(dev, phy[i]); - ret =3D -EINVAL; - goto err_phy; - } - } - - pcie->phy_count =3D phy_count; - pcie->phy =3D phy; - pcie->link =3D link; - - ret =3D cdns_pcie_enable_phy(pcie); - if (ret) - goto err_phy; - - return 0; - -err_phy: - while (--i >=3D 0) { - device_link_del(link[i]); - devm_phy_put(dev, phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); - -static int cdns_pcie_suspend_noirq(struct device *dev) -{ - struct cdns_pcie *pcie =3D dev_get_drvdata(dev); - - cdns_pcie_disable_phy(pcie); - - return 0; -} - -static int cdns_pcie_resume_noirq(struct device *dev) -{ - struct cdns_pcie *pcie =3D dev_get_drvdata(dev); - int ret; - - ret =3D cdns_pcie_enable_phy(pcie); - if (ret) { - dev_err(dev, "failed to enable PHY\n"); - return ret; - } - - return 0; -} - -const struct dev_pm_ops cdns_pcie_pm_ops =3D { - NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, - cdns_pcie_resume_noirq) -}; -EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); - MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Cadence PCIe controller driver"); MODULE_AUTHOR("Cyrille Pitchen "); --=20 2.49.0