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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 9D9544126FFD; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 05/13] PCI: cadence: Split PCIe RP support into common and specific functions Date: Wed, 13 Aug 2025 12:23:23 +0800 Message-ID: <20250813042331.1258272-6-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66C9:EE_|TYUPR06MB5947:EE_ X-MS-Office365-Filtering-Correlation-Id: a72f2b69-7ab2-45e5-47b8-08ddda21aa13 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GK9ibnHa1Z8IoQ6QwDAdC2nEz3jRl7XV0EdxJ9FoW8wIyAfj6UU0MWUWpS9W?= =?us-ascii?Q?K2Q5L2ecZZsMfnHCIxdJEObVzMEGl1HZwteGJ498K12aUsP4K3lbhl9BuCtA?= =?us-ascii?Q?sc9YGjP+Ov5W9XKqoHIhcmKMETSaBQVdSrpztkaMdq808LYVXnXLHnv0znv7?= =?us-ascii?Q?wGnxU7wNOGd0XKOJo8qWRq/GrXczPRPDcOvwYqv/j59zKNtG6pLJv4Tm2Pfw?= =?us-ascii?Q?wvqJfN4Bj3/WBqefx0kNohGyOpD9lIuPRVvAxf2KA/9930JiLZX6S3Q7Mlks?= =?us-ascii?Q?cRQq0uCCDNdlOfzlvblgi8VXoCrojUVh8M6fgCdFqKgeog6vFc00auAG6RvE?= =?us-ascii?Q?LNB+G4mjyTkXfVnR2RJSmXC5p5+q6ER1IE07ickq00tZF3DabpruomP7yqgl?= =?us-ascii?Q?8ERG/8WmBIBuZYSdbz71/p+c09WoSzdoUPGZTPZDasBQTPdweFZo0WJn54lw?= =?us-ascii?Q?fQ+Dje/jpG2t0jQYXrXG6peTJWIW9qNgMiRKqX5prAhaq6TMNkLhiMr6+K5C?= =?us-ascii?Q?LcT7xBUq4z1ubdyCPMNCA4h5RhLPueZApr6eEQ8aYihrHWDEr9xB6Ivz6n4f?= =?us-ascii?Q?PBfwykkE5tylImhIevnyaoh6nVCpJSv5xJa6/A62Gwt8W7My870kHFNB4M/h?= =?us-ascii?Q?Nd1tTXDz9wPaNIrlKorRhFLDFjt2yNoWPRZMTslHOHo4Ff/K2O7u7Hxcwpv9?= =?us-ascii?Q?8mFpDHY7clb/uk8ZmB/7AjanpcnCYx2+6DuA2/tDHua00KrFzFRWJc+95hfx?= =?us-ascii?Q?vBWnh4PZis/cLxMDb5lQBWFlzylsGPnlZSZKufkHd3XTrSc/EjZ6BuSlxPYs?= =?us-ascii?Q?Q4fK4GzfDu2YNXjOrTiHEUji7ec1EevP3rUNboCdEJZV9JyKiOe2bM4zdfv2?= =?us-ascii?Q?qwu+v+s4ssauKGyQ2cIpxKVDlxq0dUE2OLw3kFgugUP/i6KOADDJSNKxMRiU?= =?us-ascii?Q?OdMYRmjyj97p3QQpbXbMtQfukM+Z3PgrvAmO0QRGOJmKAL7uwHtW1FL1wVOl?= =?us-ascii?Q?vQmi1XIkKWcbhUTZ8EzHxObdfqmqUUe/5QFoH5atDwqbNLE13FqZkub1dIcF?= =?us-ascii?Q?GxzEc2YkVwAYQLWpv+FxefmEUQrrfsWYKCHl6nwhLqtroC7q3teeRajiqpmK?= =?us-ascii?Q?anOin8X9KQthpQEv5YnPjeU5X0CpehDSniu6eXtg9G5qWPvvFk+uv+pUO7qH?= =?us-ascii?Q?0bPiu5AE+4FVUZS6lVdobt3m62mgcwZMuld6K2j0/P/ZZ1B2+9rOQp32Ctez?= =?us-ascii?Q?2Z+7APwKBIyU9vrMSAb1h1m9OIfC+ae7AF5/mHof/DW00qDJnWE9qy6VdNhs?= =?us-ascii?Q?1E/oQcEa7BJKYXPr+rhXVGcDujyizXayJVpcdW5vd4e5FhTdvNMpL9Rfa1UG?= =?us-ascii?Q?R49pB3cj70lW3P8YdMftKegTqJFup7/4FlQeKkdNt7BsNE74u73JLCJawOnE?= =?us-ascii?Q?lX8FzYMpx+xiYgyuV69yADQUdZdcrraOnwdObXGwk06SRT/E0DGSdSdrYm14?= =?us-ascii?Q?yLcYmw25Tv0Nk9bRnXwzAHmjtpK1jaqtG+hn?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:07.6765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a72f2b69-7ab2-45e5-47b8-08ddda21aa13 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66C9.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYUPR06MB5947 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe controller RP functionality into common functions and functions for legacy PCIe RP controller. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../cadence/pcie-cadence-ep-common.h | 8 +- .../cadence/pcie-cadence-host-common.c | 181 ++++++++++++++++++ .../cadence/pcie-cadence-host-common.h | 25 +++ .../controller/cadence/pcie-cadence-host.c | 156 +-------------- 5 files changed, 212 insertions(+), 160 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .h diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 80c1c4be7e80..e45f72388bbb 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o -obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o +obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-common.o pcie-caden= ce-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.h index a91084bdedd5..9cfd0cfa7459 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0 */ // Copyright (c) 2017 Cadence -// Cadence PCIe Endpoint controller driver. +// Cadence PCIe Endpoint controller driver // Author: Manikandan K Pillai =20 -#ifndef _PCIE_CADENCE_EP_COMMON_H_ -#define _PCIE_CADENCE_EP_COMMON_H_ +#ifndef _PCIE_CADENCE_EP_COMMON_H +#define _PCIE_CADENCE_EP_COMMON_H =20 #include #include @@ -33,4 +33,4 @@ const struct pci_epc_features *cdns_pcie_ep_get_features(= struct pci_epc *epc, u8 func_no, u8 vfunc_no); =20 -#endif /* _PCIE_CADENCE_EP_COMMON_H_ */ +#endif /* _PCIE_CADENCE_EP_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c new file mode 100644 index 000000000000..5625c64c7974 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define LINK_RETRAIN_TIMEOUT HZ + +u64 bar_max_size[] =3D { + [RP_BAR0] =3D _ULL(128 * SZ_2G), + [RP_BAR1] =3D SZ_2G, + [RP_NO_BAR] =3D _BITULL(63), +}; +EXPORT_SYMBOL_GPL(bar_max_size); + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) +{ + u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + unsigned long end_jiffies; + u16 lnk_stat; + + /* Wait for link training to complete. Exit after timeout. */ + end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; + do { + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + break; + usleep_range(0, 1000); + } while (time_before(jiffies, end_jiffies)); + + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + return 0; + + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_training_complete); + +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link); + +int cdns_pcie_retrain(struct cdns_pcie *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + int ret =3D 0; + + /* + * Set retrain bit if current speed is 2.5 GB/s, + * but the PCIe root port support is > 2.5 GB/s. + */ + + lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) + return ret; + + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl =3D cdns_pcie_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |=3D PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + ret =3D cdns_pcie_host_training_complete(pcie); + if (ret) + return ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + } + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_retrain); + +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + + /* + * Retrain link for Gen2 training defect + * if quirk flag is set. + */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size <=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] < bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_find_min_bar); + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size >=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] > bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_find_max_bar); + +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b) +{ + struct resource_entry *entry1, *entry2; + + entry1 =3D container_of(a, struct resource_entry, node); + entry2 =3D container_of(b, struct resource_entry, node); + + return resource_size(entry2->res) - resource_size(entry1->res); +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_dma_ranges_cmp); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.h new file mode 100644 index 000000000000..f8eae2e963d8 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_HOST_COMMON_H +#define _PCIE_CADENCE_HOST_COMMON_H + +#include +#include + +extern u64 bar_max_size[]; + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_retrain(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b); + +#endif /* _PCIE_CADENCE_HOST_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/p= ci/controller/cadence/pcie-cadence-host.c index 59a4631de79f..bfdd0f200cfb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -12,14 +12,7 @@ #include =20 #include "pcie-cadence.h" - -#define LINK_RETRAIN_TIMEOUT HZ - -static u64 bar_max_size[] =3D { - [RP_BAR0] =3D _ULL(128 * SZ_2G), - [RP_BAR1] =3D SZ_2G, - [RP_NO_BAR] =3D _BITULL(63), -}; +#include "pcie-cadence-host-common.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x1F, @@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops =3D { .write =3D pci_generic_config_write, }; =20 -static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) -{ - u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - unsigned long end_jiffies; - u16 lnk_stat; - - /* Wait for link training to complete. Exit after timeout. */ - end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; - do { - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - break; - usleep_range(0, 1000); - } while (time_before(jiffies, end_jiffies)); - - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - return 0; - - return -ETIMEDOUT; -} - -static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) -{ - struct device *dev =3D pcie->dev; - int retries; - - /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (cdns_pcie_link_up(pcie)) { - dev_info(dev, "Link up\n"); - return 0; - } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); - } - - return -ETIMEDOUT; -} - -static int cdns_pcie_retrain(struct cdns_pcie *pcie) -{ - u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - u16 lnk_stat, lnk_ctl; - int ret =3D 0; - - /* - * Set retrain bit if current speed is 2.5 GB/s, - * but the PCIe root port support is > 2.5 GB/s. - */ - - lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + - PCI_EXP_LNKCAP)); - if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) - return ret; - - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { - lnk_ctl =3D cdns_pcie_rp_readw(pcie, - pcie_cap_off + PCI_EXP_LNKCTL); - lnk_ctl |=3D PCI_EXP_LNKCTL_RL; - cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, - lnk_ctl); - - ret =3D cdns_pcie_host_training_complete(pcie); - if (ret) - return ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - } - return ret; -} - static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) { u32 val; @@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct c= dns_pcie *pcie) cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL= _PTMRSEN); } =20 -static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) -{ - struct cdns_pcie *pcie =3D &rc->pcie; - int ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - - /* - * Retrain link for Gen2 training defect - * if quirk flag is set. - */ - if (!ret && rc->quirk_retrain_flag) - ret =3D cdns_pcie_retrain(pcie); - - return ret; -} - static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; @@ -290,54 +195,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pc= ie_rc *rc, return 0; } =20 -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size <=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] < bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size >=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] > bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, struct resource_entry *entry) { @@ -410,17 +267,6 @@ static int cdns_pcie_host_bar_config(struct cdns_pcie_= rc *rc, return 0; } =20 -static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_hea= d *a, - const struct list_head *b) -{ - struct resource_entry *entry1, *entry2; - - entry1 =3D container_of(a, struct resource_entry, node); - entry2 =3D container_of(b, struct resource_entry, node); - - return resource_size(entry2->res) - resource_size(entry1->res); -} - static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; --=20 2.49.0