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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 7F40E400E6CC; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 01/13] PCI: cadence: Add support for modules for cadence controller builds Date: Wed, 13 Aug 2025 12:23:19 +0800 Message-ID: <20250813042331.1258272-2-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E6:EE_|SI2PR06MB5244:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d86fd7d-ed16-4795-9b7b-08ddda21a8b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|36860700013|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uz1A3hclSnvMIs/f0/cDXrhNf2+UtrNnr3eozH/D5VIRE5WHKCCkcC8JR1aR?= =?us-ascii?Q?x2a/eg/2rmuqVrN6ywalTIsqTrbDVRK1Lz98w6+TjkVdFUeDMv95pt9sLBa/?= =?us-ascii?Q?ESXu7s6R9Z70gBd4j0JTfG+TZ2gnKMxPtb/ztp14Uc5V84v+2maS9dxRqBPK?= =?us-ascii?Q?CfDsQeORw7LWX8SNBzmIogS3NwMy2nRroi/OsHPidJgpe4Ok2Ke4Hobs7IjU?= =?us-ascii?Q?5VPEDLhmFFk8NNA7cx+Bp6IKWdiWnD8yPb28pw4YoC9ihdstfXpnR7N89zX5?= =?us-ascii?Q?8hambk+8ZDNDRe6Dmd7eN0dX9RbqqzA8NImHmCFX6bO1K3psZUvBgjAsTo5a?= =?us-ascii?Q?5hbQ1wTvVAijhdZEw1SrfdAM04a/DGcWHZgeLDoy9cPYlD4hR2VDWXRi+UH4?= =?us-ascii?Q?gSFtW/pEOp+gsUFXhlvFtJC8/XyaH7vPyiluBpMPxIX8I1VHtIpHTcyPC8+W?= =?us-ascii?Q?3xaADDw9ckKHJVJNY1rHx8Tl47A+7Fcg3Db3jxxWmXEfnIUqJ6K9LrGKjfPu?= =?us-ascii?Q?I7G/9Y+Tp/D67UL2dDaB4fytWQviS9vpFsNxXPEYtaduZsJKxRN7Gq1QEHDV?= =?us-ascii?Q?CdGnPmr/QWW8nRIl2KC//2s8fkFmS6givSUsUzK58UrLG4nDBozqnPtXIF6W?= =?us-ascii?Q?PLtlIIc6Ig3CcZnS5fBYUgfW7Gaq3JLvBPbUEZXVU0iAiqVdtwCfZvbr0sLr?= =?us-ascii?Q?57XG3rqf6MkmGLw7NLecoT5bhKcnxxGw2MDaq9/NBt9kZwXAFQSNSYmecT0m?= =?us-ascii?Q?8mVEjTl5fjZN2bCJXBgys6G04BphNsUdeclKH7yNqnbENgbfLyaBk/X2MCoT?= =?us-ascii?Q?9moN+WzxCuhewYaG8bjwWI8M8RKwSDus/uAr0PhSt4pX9y+IHXG/mczzEIcI?= =?us-ascii?Q?K+LNl2TVTl/gkWmsUTp8yvyUpKa87M94u3qECca+GQbWtfJ2zqRYl4s0aRB4?= =?us-ascii?Q?L6GN8TkqWf+ZjbKjR8NPjH03mRN8qhJ2ZgMFzoyMkL7lO8Uyx0FXsmTrIiKt?= =?us-ascii?Q?jIF4kWzDOmEgiTE9omKgkQTGHt1Gp8zGkCxOcmEMOnCZGGwzGIwXTFtw2dsL?= =?us-ascii?Q?zSfxjbEz7vATh139um6pwgxc01+dzLI8x51qiw7fpN3H/JCNSZSPuOZ59W7z?= =?us-ascii?Q?tChRx1XcAr+0/+r4w2Nzs/4i4RdB6VoiZAHax+F1y8BhK4/5xV5UeRXjeaIl?= =?us-ascii?Q?5bwyvpRtLzrPcgZYV06a/wJFx/ZKfKFvi9avJR0avyU4QTAyoWgClV4DbBQc?= =?us-ascii?Q?yQLxZjYBMSxm2PEfvsQTPvzVdXVV4eBJokm3GweQntGuUFw/iYLjWPBWBr3L?= =?us-ascii?Q?Gi1CA79PK5TY39JKz5tXlB9vhr2+Eg1D+g5IkEedTp/TJKdDU46dwylooVPY?= =?us-ascii?Q?Vq5Ajq5tQIVGWiN3W7yr7yK/GXcDMn1uGRkgYqXM9j4g0Youlbur0P+GEv1c?= =?us-ascii?Q?7hPzoXNh3O/6YrBqefaUHZUouUpNPofdRXcrDsMBGWxiST+U82b+z4UPo1Xh?= =?us-ascii?Q?v7DHwmzADVoxTO9v8YoUokY3H+yaE28JPna+?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(376014)(36860700013)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:05.3837 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d86fd7d-ed16-4795-9b7b-08ddda21a8b3 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E6.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SI2PR06MB5244 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add support for building PCI cadence platforms as a module. Signed-off-by: Manikandan K Pillai Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 6 +++--- drivers/pci/controller/cadence/pcie-cadence-plat.c | 4 ++++ drivers/pci/controller/cadence/pcie-cadence.c | 1 + 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 666e16b6367f..117677a23d68 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -19,10 +19,10 @@ config PCIE_CADENCE_EP select PCIE_CADENCE =20 config PCIE_CADENCE_PLAT - bool + tristate =20 config PCIE_CADENCE_PLAT_HOST - bool "Cadence platform PCIe controller (host mode)" + tristate "Cadence platform PCIe controller (host mode)" depends on OF select PCIE_CADENCE_HOST select PCIE_CADENCE_PLAT @@ -32,7 +32,7 @@ config PCIE_CADENCE_PLAT_HOST vendors SoCs. =20 config PCIE_CADENCE_PLAT_EP - bool "Cadence platform PCIe controller (endpoint mode)" + tristate "Cadence platform PCIe controller (endpoint mode)" depends on OF depends on PCI_ENDPOINT select PCIE_CADENCE_EP diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index 0456845dabb9..c9330aa50a88 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -178,3 +178,7 @@ static struct platform_driver cdns_plat_pcie_driver =3D= { .shutdown =3D cdns_plat_pcie_shutdown, }; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 8246840A5BFA; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 02/13] PCI: cadence: Split PCIe controller header file Date: Wed, 13 Aug 2025 12:23:20 +0800 Message-ID: <20250813042331.1258272-3-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E8:EE_|KUXPR06MB8032:EE_ X-MS-Office365-Filtering-Correlation-Id: 56aadd3d-c260-4904-0922-08ddda21a94f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WUdOoU1V6GQyjaoAIwornl/zKowyaAD4VSmobzvmv8Tu7R60bGWab6BBXnbN?= =?us-ascii?Q?P7RCqmCYyhv0OwI6S2fHisYHcM9FY3S033D2qedrnlJtMtRGx4BlErIdIiMw?= =?us-ascii?Q?XyYJOKHsZ/LyxCTAd3iiBZhb9B51qO7CAjVTfQLeqx/CD7H3vW1+wNLcjTgK?= =?us-ascii?Q?3mravPZ/Fr21IJemarYQhX+VSrsR2fWcXLTEih///CQCeiwa1YDJRAm0TxYy?= =?us-ascii?Q?ZmwY4WPH5zyH0P0zMYwMQMpgXI8gld053pr5nMQi7oWzFsaTZvSIXzbBJTVS?= =?us-ascii?Q?CdXcgTWZm6PQEA+w3YrHSbIcxE/aqXNlA5o5o1bGWamZM1fZ6zwbvpzbf0ti?= =?us-ascii?Q?Vxb4Bq7RUHZQw4rZNUPtiGxAclDbDHnfun+/rxq2pFwyd3OhvAIRTawJOb/w?= =?us-ascii?Q?0xHRDTWzEWES15Kektx6GSkM3mc+mr4nrmVv8z9LFyVDnFkiwQ78yhDpOYss?= =?us-ascii?Q?uz1QFlMLlMpVy38RWv2cMGg/vkRactN990ezbDDTVKNBlaCv5sFfhYpUlxpY?= =?us-ascii?Q?J6P3WhVf/yBBruguSuvYfmbdU+FXQFvtOKQ4oFJPhRXybvCqRBGOeFawAK+o?= =?us-ascii?Q?c2AHi5fx5ImrxeVksOEoKwlw8k/VyIjhPENmGcaHTb/Q80pWgeNg7LayJnT0?= =?us-ascii?Q?TRpbNlWHz77xIN9mdtoUxgqDKmmfLxe8t7sXNF95T+pxKjhrT4asYk2rhdLn?= =?us-ascii?Q?/TlrrhvWfOrHvhhMwRxo+qeFDrYLCJT215SlwRytKb1E1soYwYdMI7hjKu9r?= =?us-ascii?Q?NBak41MR4L7/jesldu9SYgcEfDd8UuIltccHZwdRqmFA6Y9bKYgGj1J+7CIJ?= =?us-ascii?Q?yo/gcbkpgjqftOpbKaNf6LX2jJ1r1cFc4Rpq3u9QfVqMp3gbZdHggniREpks?= =?us-ascii?Q?5PqDVhwBjnFYUdezQu+dpjbgbA0lErjiN+NKSS6rYZwAEzqFDfyKXDQtsI2L?= =?us-ascii?Q?eZzSPTWP81OnUIAbKnBIxNKiI1ThAxVbOMrOZHOA/6zw+rKmb4iOWKE3AhW9?= =?us-ascii?Q?T8LkYsULEh/dDALGqz84EZxj71miBa8F+w8bNvEE44ApTMCSZKpfO4H65KN7?= =?us-ascii?Q?jho5Y9JB3CEYfrIOVOc7fDA0v94rroEJ3ELICsKT4i9YXv/UrLgwkI13Lqfk?= =?us-ascii?Q?l22uILV5TRsjxay5EHcgh6fH2sViZxj+6O19Qx5LRsa4UXH2wirWZhKzNwhG?= =?us-ascii?Q?RDAMM0v8dlfzwYwzZPZVXTEsL4qz5DLW+prnMnq20MG2cRC+ISOw1Co8l7BV?= =?us-ascii?Q?g0ZFEC+T8J4T5gVzBhNEskC6Vx007iLTx4P4Wsg+kBXqK/OIkVCez/NDPFqF?= =?us-ascii?Q?4Rfp3vWrjh0Vshh9ShzBn4mJUUBI0b8LjQnAdSB+W3DPchORpza0SpNVnXeJ?= =?us-ascii?Q?r8ttswu+HakaXb5OboMhjNenIz7FBB3ZdYFi93dAkbXmlC1D+/ps5LPn7jrJ?= =?us-ascii?Q?MMX5FPJNJWuDop50hkWcfasF4j125Jri5h2bqCOaY+EIcpOm9bhIbyKU2/Z4?= =?us-ascii?Q?5DwlaSXJ1T6UUx+DQ6TS/HqFxbb2BmwZ0R7u?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:06.3987 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56aadd3d-c260-4904-0922-08ddda21a94f X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUXPR06MB8032 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe header file by moving the Legacy(LGA) controller register definitions to a separate header file for support of next generation PCIe controller architecture. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../cadence/pcie-cadence-lga-regs.h | 228 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 226 +---------------- 2 files changed, 229 insertions(+), 225 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-lga-regs.h diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-lga-regs.h new file mode 100644 index 000000000000..0e88beb77292 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_LGA_REGS_H +#define _PCIE_CADENCE_LGA_REGS_H + +#include + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + +/* Local Management Registers */ +#define CDNS_PCIE_LM_BASE 0x00100000 + +/* Vendor ID Register */ +#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) +#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 +#define CDNS_PCIE_LM_ID_VENDOR(vid) \ + (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) +#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) +#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 +#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ + (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) + +/* Root Port Requester ID Register */ +#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) +#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_RP_RID_SHIFT 0 +#define CDNS_PCIE_LM_RP_RID_(rid) \ + (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) + +/* Endpoint Bus and Device Number Register */ +#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C) +#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) +#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 +#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) +#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 + +/* Endpoint Function f BAR b Configuration Registers */ +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FU= NC_BAR_CFG1(fn)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_V= FUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ + (GENMASK(4, 0) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ + (GENMASK(7, 5) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) + +/* Endpoint Function Configuration Register */ +#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0) + +/* Root Complex BAR Configuration Register */ +#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) +#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) + +/* BAR control values applicable to both Endpoint Function and Root Comple= x */ +#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 + +#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 2) << ((bar) * 8)) + +/* PTM Control Register */ +#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8) +#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) + +/* + * Endpoint Function Registers (PCI configuration space for endpoint funct= ions) + */ +#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) + +#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 +#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0 +#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0 +#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 + +/* Endpoint PF Registers */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + +/* Root Port Registers (PCI configuration space for the root port function= ) */ +#define CDNS_PCIE_RP_BASE 0x00200000 +#define CDNS_PCIE_RP_CAP_OFFSET 0xC0 + +/* Address Translation Registers */ +#define CDNS_PCIE_AT_BASE 0x00400000 + +/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) + +/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020) + +/* Region r Outbound PCIe Descriptor Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ + (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD +/* Bit 23 MUST be set in RC mode. */ +#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ + (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) + +/* Region r Outbound PCIe Descriptor Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ + (CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ + ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) + +/* Region r AXI Region Base Address Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) + +/* Region r AXI Region Base Address Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020) + +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ + (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ + (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) + +/* AXI link down register */ +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) + +/* LTSSM Capabilities register */ +#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ + (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ + CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) + +#define CDNS_PCIE_RP_MAX_IB 0x3 +#define CDNS_PCIE_MAX_OB 32 + +/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) + +/* Normal/Vendor specific message access: offset inside some outbound regi= on */ +#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) +#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ + (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) +#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) +#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ + (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) +#define CDNS_PCIE_MSG_NO_DATA BIT(16) + +#endif /* _PCIE_CADENCE_LGA_REGS_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 1d81c4bf6c6d..79df86117fde 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,213 +10,7 @@ #include #include #include - -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - -/* - * Local Management Registers - */ -#define CDNS_PCIE_LM_BASE 0x00100000 - -/* Vendor ID Register */ -#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) -#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) -#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 -#define CDNS_PCIE_LM_ID_VENDOR(vid) \ - (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) -#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) -#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 -#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ - (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) - -/* Root Port Requester ID Register */ -#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) -#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) -#define CDNS_PCIE_LM_RP_RID_SHIFT 0 -#define CDNS_PCIE_LM_RP_RID_(rid) \ - (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) - -/* Endpoint Bus and Device Number Register */ -#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) -#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) -#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 -#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) -#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 - -/* Endpoint Function f BAR b Configuration Registers */ -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ - (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FU= NC_BAR_CFG1(fn)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ - (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ - (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ - (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_V= FUNC_BAR_CFG1(fn)) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ - (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ - (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ - (GENMASK(4, 0) << ((b) * 8)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ - (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ - (GENMASK(7, 5) << ((b) * 8)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ - (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) - -/* Endpoint Function Configuration Register */ -#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) - -/* Root Complex BAR Configuration Register */ -#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ - (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ - (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ - (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ - (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) -#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) - -/* BAR control values applicable to both Endpoint Function and Root Comple= x */ -#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 - -#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ - (((aperture) - 2) << ((bar) * 8)) - -/* PTM Control Register */ -#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) -#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) - -/* - * Endpoint Function Registers (PCI configuration space for endpoint funct= ions) - */ -#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) - -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - -/* - * Endpoint PF Registers - */ -#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) -#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) - -/* - * Root Port Registers (PCI configuration space for the root port function) - */ -#define CDNS_PCIE_RP_BASE 0x00200000 -#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 - -/* - * Address Translation Registers - */ -#define CDNS_PCIE_AT_BASE 0x00400000 - -/* Region r Outbound AXI to PCIe Address Translation Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ - (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ - (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ - (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) - -/* Region r Outbound AXI to PCIe Address Translation Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ - (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) - -/* Region r Outbound PCIe Descriptor Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ - (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd -/* Bit 23 MUST be set in RC mode. */ -#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) -#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) -#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ - (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) - -/* Region r Outbound PCIe Descriptor Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ - (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) -#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ - ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) - -/* Region r AXI Region Base Address Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ - (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) - -/* Region r AXI Region Base Address Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ - (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) - -/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ - (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ - (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) - -/* AXI link down register */ -#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) - -/* LTSSM Capabilities register */ -#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x005= 4) -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ - (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ - CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) +#include "pcie-cadence-lga-regs.h" =20 enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED =3D -1, @@ -225,29 +19,11 @@ enum cdns_pcie_rp_bar { RP_NO_BAR }; =20 -#define CDNS_PCIE_RP_MAX_IB 0x3 -#define CDNS_PCIE_MAX_OB 32 - struct cdns_pcie_rp_ib_bar { u64 size; bool free; }; =20 -/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ -#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ - 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 88FD94115DE1; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 03/13] PCI: cadence: Add register definitions for HPA(High Perf Architecture) Date: Wed, 13 Aug 2025 12:23:21 +0800 Message-ID: <20250813042331.1258272-4-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E4:EE_|TYZPR06MB7094:EE_ X-MS-Office365-Filtering-Correlation-Id: abd05fe8-d697-47dd-4fc3-08ddda21a96e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?CizLuYRFsvmF6mdsDOCAu9fy02nyWEDbyghdzTPHtwsgBz3Xu32bsckDbtMH?= =?us-ascii?Q?HBPDBXtKlkzlTS+tUlbu9Y8fx1XKl+bevYZmFzP4pzOjLkA9nIu7yz/5Lo4n?= =?us-ascii?Q?EeDIIamRO9WJ0FXUkOs71E8hai/0u64WRFIwv06QIqym7SdrN5goJVwVVU5q?= =?us-ascii?Q?0MxiCx5hcqqBmB2KeoEP5AmdbqVoetD+AvhhRAKvZoFNiQHzMhOjcaNk85Xk?= =?us-ascii?Q?q9sQ1MM8qiGzejxT6ssjfs7GQUgFZVt0KBp+1Cpjb/nZ12QIKLVPTqhGzdEd?= =?us-ascii?Q?iqj2lTX+xbcSAosBPy2WQHJAhL+1YqNm9kiid3kgjcMC572hEZKxy7KndlVW?= =?us-ascii?Q?VhihYjLRil2+InE+N6mLC7MmzNe3rvg2yZebYnXa1dMXNqHXHVEmNECN3wNt?= =?us-ascii?Q?1WpC5/MaDqV4JDFSCW5XA6KDL/dbj8U0y3cyJL+LLHDgJcyzElcvK2s+DBsV?= =?us-ascii?Q?2sBPd003wtwCe97PEUj3Cu1nXY6WpEILisrbn0es9nfhwlUGim7G1cRBM1OS?= =?us-ascii?Q?SmQGAsApB8JDOvKmd3J6GjbkmVti0GILsOFu16gpfldPoF4fLdsm9lwYmTLW?= =?us-ascii?Q?v6wvTZx5lFTzpNBne5ciKTiTTyYkWtJkzpj5g+h67KAmVvnGHvVabf5pECNz?= =?us-ascii?Q?YHTcR0N4gbHlWVN//LnO/rzm7cU9CH8LrOwCCRitAEWC23MdYKipJ6zZOTHx?= =?us-ascii?Q?FYoze/24hROViN+cVI74Yb+o6VI7EtMjR7AcsW4H7gAmvCAzHrNRBAnQwRZt?= =?us-ascii?Q?IgUosaLOmVbf83XimRcwyLvmd+X2jA4PxcBCLibC/hN6pklxbs+xrl5JFzqk?= =?us-ascii?Q?6dTafTVPsvWcgh06nVMfdJA52KfcX9kSeUnqlw8/cw7qbDQ9h8x7eXXM5KC7?= =?us-ascii?Q?RNcaueJXNCJ+RUvH/lQJ8bvzlaAmcT/bH5hdOCn3Qt/oWxVUSACBwnLIM4o8?= =?us-ascii?Q?AJcAf36VtjCIb59LMkStY/b3bUvl0uAdC8mXGIsqAukuch49gve3iLRKugxr?= =?us-ascii?Q?b72HC64N+QuCUVAg17SgxJ0F1YHn7HNsfb/1ZeBhyuIa4/GwTo9n9hO3lWbi?= =?us-ascii?Q?DGWS22HTtSYbWWwZzkxSkVhd7K1DyVZ14TTPsJT/Tlw7koZ1hTXcu8f50gXJ?= =?us-ascii?Q?sEDCDW0CCJ4nh7PCYm9goptWbR2ECYnMdW9FvCZVwrAB+xgKekSr5mA33FkK?= =?us-ascii?Q?jmiOr8kuPMTI4TZ1mJqzJMVT8OAPK8aA4ipjGgJFVUAPzHFju1cLxB+A2Ud0?= =?us-ascii?Q?Ba5oMAULCzJrGQgcQC99DKyMb/uJ1sqDoq/J+GT++n8IUM4v2mPSWoS6aYji?= =?us-ascii?Q?oze/7jAFmYwX8b3Us/RATxld3HYVmSparztWutnd/xLeB47878BYjSFR3cLt?= =?us-ascii?Q?gpT3RozVLpckO6MMuBKb0youfpjeD9WyEGjOzEXQXO/KWepoh5V+6aVKUM0z?= =?us-ascii?Q?HcKD1tiGE4iezHeGtZhVqi8K5oHIaoZwPPoXamsaiu9LgRanm+MNyu9JP91J?= =?us-ascii?Q?mQq13leZ/cYqvYC7NAIasPRkCoj6Phn1rVlV?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:06.5982 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abd05fe8-d697-47dd-4fc3-08ddda21a96e X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E4.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB7094 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add the register offsets and register definitions for HPA(High Performance architecture) PCIe controllers from Cadence. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../cadence/pcie-cadence-hpa-regs.h | 212 ++++++++++++++++++ .../controller/cadence/pcie-cadence-plat.c | 4 - drivers/pci/controller/cadence/pcie-cadence.h | 121 ++++++++-- 3 files changed, 320 insertions(+), 17 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-hpa-regs.h new file mode 100644 index 000000000000..016144e2df81 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_HPA_REGS_H +#define _PCIE_CADENCE_HPA_REGS_H + +#include +#include +#include +#include +#include + +/* + * HPA (High Performance Architecture) PCIe controller register + */ +#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000 +#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00 +#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x01020000 +/* + * Address Translation Registers(HPA) + */ +#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000 +#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000 +/* + * Root port register base address + */ +#define CDNS_PCIE_HPA_RP_BASE 0x0 + +#define CDNS_PCIE_HPA_LM_ID 0x1420 + +/* + * Endpoint Function BARs(HPA) Configuration Registers + */ +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \ + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \ + CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \ + (GENMASK(9, 4) << ((f) * 10)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTU= RE_MASK(b))) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \ + (GENMASK(3, 0) << ((f) * 10)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)= )) + +/* + * Endpoint Function Configuration Register + */ +#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0 + +/* + * Root Complex BAR Configuration Register + */ +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14 +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c) + +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23) + +/* BAR control values applicable to both Endpoint Function and Root Comple= x */ +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD + +#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 7) << ((bar) * 10)) + +#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520 +#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN BIT(17) + +/* + * Root Port Registers PCI config space(HPA) for root port function + */ +#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0 + +/* + * Region r Outbound AXI to PCIe Address Translation Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) = & 0x1F) * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK, ((nbits) - 1)) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus) + +/* + * Region r Outbound AXI to PCIe Address Translation Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) = & 0x1F) * 0x0080) + +/* + * Region r Outbound PCIe Descriptor Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) = & 0x1F) * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10) + +/* + * Region r Outbound PCIe Descriptor Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) = * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn) + +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F)= * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26) +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25) + +/* + * Region r AXI Region Base Address Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F)= * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK, ((nbits) - 1)) + +/* + * Region r AXI Region Base Address Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F)= * 0x0080) + +/* + * Root Port BAR Inbound PCIe to AXI Address Translation Register + */ +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x000= 8)) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK, ((nbits) - 1)) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) = * 0x0008)) + +/* + * AXI link down register + */ +#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04 + +/* + * Physical Layer Configuration Register 0 + * This register contains the parameters required for functional setup + * of Physical Layer. + */ +#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400 +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24) +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \ + FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay) +#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27) + +#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420 + +#define CDNS_PCIE_HPA_RP_MAX_IB 0x3 +#define CDNS_PCIE_HPA_MAX_OB 15 + +/* + * Endpoint Function BAR Inbound PCIe to AXI Address Translation Register(= HPA) + */ +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0040) + = ((bar) * 0x0008)) +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x00= 40) + ((bar) * 0x0008)) + +#endif /* _PCIE_CADENCE_HPA_REGS_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index c9330aa50a88..ced030cc0fda 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -22,10 +22,6 @@ struct cdns_plat_pcie { struct cdns_pcie *pcie; }; =20 -struct cdns_plat_pcie_of_data { - bool is_rc; -}; - static const struct of_device_id cdns_plat_pcie_of_match[]; =20 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 79df86117fde..8048bef215d0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,7 +10,9 @@ #include #include #include +#include #include "pcie-cadence-lga-regs.h" +#include "pcie-cadence-hpa-regs.h" =20 enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED =3D -1, @@ -25,6 +27,20 @@ struct cdns_pcie_rp_ib_bar { }; =20 struct cdns_pcie; +struct cdns_pcie_rc; + +enum cdns_pcie_reg_bank { + REG_BANK_RP, + REG_BANK_IP_REG, + REG_BANK_IP_CFG_CTRL_REG, + REG_BANK_AXI_MASTER_COMMON, + REG_BANK_AXI_MASTER, + REG_BANK_AXI_SLAVE, + REG_BANK_AXI_HLS, + REG_BANK_AXI_RAS, + REG_BANK_AXI_DTI, + REG_BANKS_MAX, +}; =20 struct cdns_pcie_ops { int (*start_link)(struct cdns_pcie *pcie); @@ -33,6 +49,30 @@ struct cdns_pcie_ops { u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 +/** + * struct cdns_plat_pcie_of_data - Register bank offset for a platform + * @is_rc: controller is a RC + * @ip_reg_bank_offset: ip register bank start offset + * @ip_cfg_ctrl_reg_offset: ip config control register start offset + * @axi_mstr_common_offset: AXI master common register start offset + * @axi_slave_offset: AXI slave start offset + * @axi_master_offset: AXI master start offset + * @axi_hls_offset: AXI HLS offset start + * @axi_ras_offset: AXI RAS offset + * @axi_dti_offset: AXI DTI offset + */ +struct cdns_plat_pcie_of_data { + u32 is_rc:1; + u32 ip_reg_bank_offset; + u32 ip_cfg_ctrl_reg_offset; + u32 axi_mstr_common_offset; + u32 axi_slave_offset; + u32 axi_master_offset; + u32 axi_hls_offset; + u32 axi_ras_offset; + u32 axi_dti_offset; +}; + /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base @@ -44,16 +84,18 @@ struct cdns_pcie_ops { * @link: list of pointers to corresponding device link representations * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper + * @cdns_pcie_reg_offsets: Register bank offsets for different SoC */ struct cdns_pcie { - void __iomem *reg_base; - struct resource *mem_res; - struct device *dev; - bool is_rc; - int phy_count; - struct phy **phy; - struct device_link **link; - const struct cdns_pcie_ops *ops; + void __iomem *reg_base; + struct resource *mem_res; + struct device *dev; + bool is_rc; + int phy_count; + struct phy **phy; + struct device_link **link; + const struct cdns_pcie_ops *ops; + const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; }; =20 /** @@ -131,6 +173,40 @@ struct cdns_pcie_ep { unsigned int quirk_disable_flr:1; }; =20 +static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_p= cie_reg_bank bank) +{ + u32 offset =3D 0x0; + + switch (bank) { + case REG_BANK_IP_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; + break; + case REG_BANK_IP_CFG_CTRL_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; + break; + case REG_BANK_AXI_MASTER_COMMON: + offset =3D pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; + break; + case REG_BANK_AXI_MASTER: + offset =3D pcie->cdns_pcie_reg_offsets->axi_master_offset; + break; + case REG_BANK_AXI_SLAVE: + offset =3D pcie->cdns_pcie_reg_offsets->axi_slave_offset; + break; + case REG_BANK_AXI_HLS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_hls_offset; + break; + case REG_BANK_AXI_RAS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_ras_offset; + break; + case REG_BANK_AXI_DTI: + offset =3D pcie->cdns_pcie_reg_offsets->axi_dti_offset; + break; + default: + break; + }; + return offset; +} =20 /* Register access */ static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 v= alue) @@ -143,6 +219,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pc= ie, u32 reg) return readl(pcie->reg_base + reg); } =20 +static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg, + u32 value) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + writel(value, pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + return readl(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr =3D PTR_ALIGN_DOWN(addr, 0x4); @@ -313,19 +410,17 @@ static inline void cdns_pcie_ep_disable(struct cdns_p= cie_ep *ep) #endif =20 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); - 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 983DB4115DE4; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 04/13] PCI: cadence: Split PCIe EP support into common and specific functions Date: Wed, 13 Aug 2025 12:23:22 +0800 Message-ID: <20250813042331.1258272-5-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CE:EE_|SE2PPF3C2682CAB:EE_ X-MS-Office365-Filtering-Correlation-Id: b2855d4f-f596-4ec0-0eb4-08ddda21a8bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?k7VjKr8uXiZuzVZY4Ivw3QpQz4XNyY3qMjTcdb961BZUkY2dk+v4Zdl0kgEg?= =?us-ascii?Q?z5sexk4WeCF3VG82NhpYWrdA98fbz3F9QILD1n8kTk0ot+pQc4xH/yU9xidB?= =?us-ascii?Q?SKXRZCMAtz1zV3ZwTw2N/PhktleDb/ayGmFsTD+IkWbkKdcUvyGlv5gfRRyT?= =?us-ascii?Q?wM4Eto6Iz9/rpRYzthSfe/10QtxHCv/8BCdvLkc9jiLLvUTsbaTILKhg284u?= =?us-ascii?Q?+bgChHJXiRKxifLGUURt1aC4Bk5izRSYElEqlgIA8SN0OwZCo8xdW1cZVnmR?= =?us-ascii?Q?kXrATZww7ZGjzgWrGMng7gVF4omgkPHFFpNvooxzwbZyUlXhXXUYG7kJMdjU?= =?us-ascii?Q?vec4AUfXf2Q4J7UBysapkIjtBLclnS8SSD2p8AC1CuoKTqxHGDAjd8JLoo/U?= =?us-ascii?Q?2lX9+JcddkNVqBcC4VUf+vVZD+ieX6oYD0HjpaTWpmBSEJmq0sdp2iffCazx?= =?us-ascii?Q?n3Q/xKVRjibD2thAMsNRwglgzA4iTfPJMpB0lZL3x3LdAbwenNriSGnPSJkt?= =?us-ascii?Q?juL/Nri0rBbzjvGZOLVX0L/NkOtgi5/eeQ8KtALFvSXOoIMEDYzTZXz+ieL2?= =?us-ascii?Q?wu0wdD4cIHjmsIgnRdEXMw9sb6n3HQxrcqBqryA+uI97UMTr/bcjxTZwCm5a?= =?us-ascii?Q?9cTDPGhDiEgghIClKkHrsD7bgOIsgEey+txkwimhPvzhi9UiMT3EnE+2M33A?= =?us-ascii?Q?63PV0Cu/ZzTRpEBkiDnIiRdRu12gz18wbHdTaMK4A0LJ5NfclDyGPVtYnCUU?= =?us-ascii?Q?DCUbflvq/vnhNSF2r76mxb4FmcecLlJJVfw2M19Q5TrjH/DCSDWNgIJWKuuI?= =?us-ascii?Q?NgrKb6tT3giuuWnNlF4X9vB0kolfxdCZEB1McOYQ8jLYBsHBqwzSQYKAczHN?= =?us-ascii?Q?FVaJTLwp3sAFrK+xdOIlnhcfIHXDJ/z5vvo/TmIOmc7AXDTxAPwLfvVJyO5J?= =?us-ascii?Q?U4UlOXb+NfFXUYvokR1Ai6VXszm8n7BJq3qIz4KSt0cHjj/wXCQtqmOiRaYD?= =?us-ascii?Q?JXnoCp4rfvK5whJ1tt7MOgrBIi3gSgRCKVvZ4TBYv9UHLZN87gqzoA11/w6b?= =?us-ascii?Q?4lJA5/p+TpJ0eizQOHH8PLIBffIt06qCWGaxj8ugl1f25VHNhXKuYNMtydV9?= =?us-ascii?Q?Y4dcF6dwUPS7eu7a5hwhyfGkrZ7rWvxigDLa/rCGuDykaOKhkH85S1WxP0qY?= =?us-ascii?Q?LFbZdes3q2imOVK7WPPnQVawXfysTCHen+EeMrQQ2jBRmdPSg5nfHX9f7lYp?= =?us-ascii?Q?BsDGxQGCovHeILu2H+hRpISE2wXHmVVcnR1b8EISQZH9O3NBQa35OZCcuyW9?= =?us-ascii?Q?6plyhJgYgYO7ZJGCyKqtJvNtN4F9x0pbnJ4K2r1NQKKpJGf6RXqP6HGm4YB/?= =?us-ascii?Q?EYQ8tAjyeBNIEkYOEYPGsxPxBt094Raa7rg8jLwLu67aA5HlWb+TY1Z568KF?= =?us-ascii?Q?pXups3VcpaIkQGdbwe0gJyq6D1ypB5RGXAOkprUQZUmUsSVW4vSAeOZxACSy?= =?us-ascii?Q?8ZO5o4op07XIaG6eLBJn9Nn1xVwfHjPD4SIT?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:05.4278 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2855d4f-f596-4ec0-0eb4-08ddda21a8bb X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CE.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE2PPF3C2682CAB Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe controller EP functionality into common ibrary functions and functions for legacy PCIe EP controller. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../cadence/pcie-cadence-ep-common.c | 252 ++++++++++++++++++ .../cadence/pcie-cadence-ep-common.h | 36 +++ .../pci/controller/cadence/pcie-cadence-ep.c | 243 +---------------- 4 files changed, 295 insertions(+), 238 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-common.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-common.h diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 9bac5fb2f13d..80c1c4be7e80 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o -obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o +obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.c b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.c new file mode 100644 index 000000000000..46a1631e54e5 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe endpoint controller driver common +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-ep-common.h" + +u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) +{ + u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + u32 first_vf_offset, stride; + + if (vfn =3D=3D 0) + return fn; + + first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); + stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); + fn =3D fn + first_vf_offset + ((vfn - 1) * stride); + + return fn; +} +EXPORT_SYMBOL_GPL(cdns_pcie_get_fn_from_vfn); + +int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_header *hdr) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + struct cdns_pcie *pcie =3D &ep->pcie; + u32 reg; + + if (vfn > 1) { + dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); + return -EINVAL; + } else if (vfn =3D=3D 1) { + reg =3D cap + PCI_SRIOV_VF_DID; + cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); + return 0; + } + + cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, + hdr->subclass_code | hdr->baseclass_code << 8); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, + hdr->cache_line_size); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); + + /* + * Vendor ID can only be modified from function 0, all other functions + * use the same vendor ID as function 0. + */ + if (fn =3D=3D 0) { + /* Update the vendor IDs. */ + u32 id =3D CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | + CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); + + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_write_header); + +int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* + * Set the Multiple Message Capable bitfield into the Message Control + * register. + */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + flags =3D (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); + flags |=3D PCI_MSI_FLAGS_64BIT; + flags &=3D ~PCI_MSI_FLAGS_MASKBIT; + cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_set_msi); + +int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags, mme; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Validate that the MSI feature is actually enabled. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* + * Get the Multiple Message Enable bitfield from the Message Control + * register. + */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + + return mme; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_get_msi); + +int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); + + reg =3D cap + PCI_MSIX_FLAGS; + val =3D cdns_pcie_ep_fn_readw(pcie, func_no, reg); + if (!(val & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + val &=3D PCI_MSIX_FLAGS_QSIZE; + + return val; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_get_msix); + +int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, + u16 interrupts, enum pci_barno bir, + u32 offset) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + reg =3D cap + PCI_MSIX_FLAGS; + val =3D cdns_pcie_ep_fn_readw(pcie, fn, reg); + val &=3D ~PCI_MSIX_FLAGS_QSIZE; + val |=3D interrupts; + cdns_pcie_ep_fn_writew(pcie, fn, reg, val); + + /* Set MSI-X BAR and offset */ + reg =3D cap + PCI_MSIX_TABLE; + val =3D offset | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + /* Set PBA BAR and offset. BAR must match MSI-X BAR */ + reg =3D cap + PCI_MSIX_PBA; + val =3D (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_set_msix); + +int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + struct cdns_pcie *pcie =3D &ep->pcie; + u64 pci_addr, pci_addr_mask =3D 0xff; + u16 flags, mme, data, data_mask; + u8 msi_count; + int ret; + int i; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + msi_count =3D 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask =3D msi_count - 1; + data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data =3D data & ~data_mask; + + /* Get the PCI address where to write the data into. */ + pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<=3D 32; + pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &=3D GENMASK_ULL(63, 2); + + for (i =3D 0; i < interrupt_num; i++) { + ret =3D epc->ops->map_addr(epc, fn, vfn, addr, + pci_addr & ~pci_addr_mask, + entry_size); + if (ret) + return ret; + addr =3D addr + entry_size; + } + + *msi_data =3D data; + *msi_addr_offset =3D pci_addr & pci_addr_mask; + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_map_msi_irq); + +static const struct pci_epc_features cdns_pcie_epc_vf_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D true, + .align =3D 65536, +}; + +static const struct pci_epc_features cdns_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D true, + .align =3D 256, +}; + +const struct pci_epc_features* +cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + if (!vfunc_no) + return &cdns_pcie_epc_features; + + return &cdns_pcie_epc_vf_features; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_get_features); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.h new file mode 100644 index 000000000000..a91084bdedd5 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_EP_COMMON_H_ +#define _PCIE_CADENCE_EP_COMMON_H_ + +#include +#include +#include +#include +#include "../../pci.h" + +#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ +#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 +#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 + +u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn); +int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_header *hdr); +int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc); +int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn); +int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no); +int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, + u16 interrupts, enum pci_barno bir, + u32 offset); +int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset); +const struct pci_epc_features *cdns_pcie_ep_get_features(struct pci_epc *e= pc, + u8 func_no, + u8 vfunc_no); + +#endif /* _PCIE_CADENCE_EP_COMMON_H_ */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index 77c5a19b2ab1..83204efaea3f 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -13,68 +13,7 @@ #include =20 #include "pcie-cadence.h" -#include "../../pci.h" - -#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ -#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 -#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 - -static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) -{ - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; - u32 first_vf_offset, stride; - - if (vfn =3D=3D 0) - return fn; - - first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); - stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); - fn =3D fn + first_vf_offset + ((vfn - 1) * stride); - - return fn; -} - -static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, - struct pci_epf_header *hdr) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; - struct cdns_pcie *pcie =3D &ep->pcie; - u32 reg; - - if (vfn > 1) { - dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); - return -EINVAL; - } else if (vfn =3D=3D 1) { - reg =3D cap + PCI_SRIOV_VF_DID; - cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); - return 0; - } - - cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); - cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, - hdr->subclass_code | hdr->baseclass_code << 8); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, - hdr->cache_line_size); - cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); - - /* - * Vendor ID can only be modified from function 0, all other functions - * use the same vendor ID as function 0. - */ - if (fn =3D=3D 0) { - /* Update the vendor IDs. */ - u32 id =3D CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | - CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); - - cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); - } - - return 0; -} +#include "pcie-cadence-ep-common.h" =20 static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_bar *epf_bar) @@ -222,100 +161,6 @@ static void cdns_pcie_ep_unmap_addr(struct pci_epc *e= pc, u8 fn, u8 vfn, clear_bit(r, &ep->ob_region_map); } =20 -static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 nr_= irqs) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u8 mmc =3D order_base_2(nr_irqs); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - u16 flags; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* - * Set the Multiple Message Capable bitfield into the Message Control - * register. - */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - flags =3D (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); - flags |=3D PCI_MSI_FLAGS_64BIT; - flags &=3D ~PCI_MSI_FLAGS_MASKBIT; - cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); - - return 0; -} - -static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - u16 flags, mme; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* Validate that the MSI feature is actually enabled. */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - if (!(flags & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - - /* - * Get the Multiple Message Enable bitfield from the Message Control - * register. - */ - mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); - - return 1 << mme; -} - -static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc= _no) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; - u32 val, reg; - - func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); - - reg =3D cap + PCI_MSIX_FLAGS; - val =3D cdns_pcie_ep_fn_readw(pcie, func_no, reg); - if (!(val & PCI_MSIX_FLAGS_ENABLE)) - return -EINVAL; - - val &=3D PCI_MSIX_FLAGS_QSIZE; - - return val + 1; -} - -static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, - u16 nr_irqs, enum pci_barno bir, u32 offset) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; - u32 val, reg; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - reg =3D cap + PCI_MSIX_FLAGS; - val =3D cdns_pcie_ep_fn_readw(pcie, fn, reg); - val &=3D ~PCI_MSIX_FLAGS_QSIZE; - val |=3D nr_irqs - 1; /* encoded as N-1 */ - cdns_pcie_ep_fn_writew(pcie, fn, reg, val); - - /* Set MSI-X BAR and offset */ - reg =3D cap + PCI_MSIX_TABLE; - val =3D offset | bir; - cdns_pcie_ep_fn_writel(pcie, fn, reg, val); - - /* Set PBA BAR and offset. BAR must match MSI-X BAR */ - reg =3D cap + PCI_MSIX_PBA; - val =3D (offset + (nr_irqs * PCI_MSIX_ENTRY_SIZE)) | bir; - cdns_pcie_ep_fn_writel(pcie, fn, reg, val); - - return 0; -} - static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 in= tx, bool is_asserted) { @@ -426,59 +271,6 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_= ep *ep, u8 fn, u8 vfn, return 0; } =20 -static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, - phys_addr_t addr, u8 interrupt_num, - u32 entry_size, u32 *msi_data, - u32 *msi_addr_offset) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - struct cdns_pcie *pcie =3D &ep->pcie; - u64 pci_addr, pci_addr_mask =3D 0xff; - u16 flags, mme, data, data_mask; - u8 msi_count; - int ret; - int i; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* Check whether the MSI feature has been enabled by the PCI host. */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - if (!(flags & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - - /* Get the number of enabled MSIs */ - mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); - msi_count =3D 1 << mme; - if (!interrupt_num || interrupt_num > msi_count) - return -EINVAL; - - /* Compute the data value to be written. */ - data_mask =3D msi_count - 1; - data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); - data =3D data & ~data_mask; - - /* Get the PCI address where to write the data into. */ - pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); - pci_addr <<=3D 32; - pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); - pci_addr &=3D GENMASK_ULL(63, 2); - - for (i =3D 0; i < interrupt_num; i++) { - ret =3D cdns_pcie_ep_map_addr(epc, fn, vfn, addr, - pci_addr & ~pci_addr_mask, - entry_size); - if (ret) - return ret; - addr =3D addr + entry_size; - } - - *msi_data =3D data; - *msi_addr_offset =3D pci_addr & pci_addr_mask; - - return 0; -} - static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 v= fn, u16 interrupt_num) { @@ -589,12 +381,12 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; =20 value =3D cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP); value &=3D ~PCI_EXP_DEVCAP_FLR; cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP, value); } } =20 @@ -607,29 +399,6 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) return 0; } =20 -static const struct pci_epc_features cdns_pcie_epc_vf_features =3D { - .linkup_notifier =3D false, - .msi_capable =3D true, - .msix_capable =3D true, - .align =3D 65536, -}; - -static const struct pci_epc_features cdns_pcie_epc_features =3D { - .linkup_notifier =3D false, - .msi_capable =3D true, - .msix_capable =3D true, - .align =3D 256, -}; - -static const struct pci_epc_features* -cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) -{ - if (!vfunc_no) - return &cdns_pcie_epc_features; - - return &cdns_pcie_epc_vf_features; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 9D9544126FFD; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 05/13] PCI: cadence: Split PCIe RP support into common and specific functions Date: Wed, 13 Aug 2025 12:23:23 +0800 Message-ID: <20250813042331.1258272-6-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66C9:EE_|TYUPR06MB5947:EE_ X-MS-Office365-Filtering-Correlation-Id: a72f2b69-7ab2-45e5-47b8-08ddda21aa13 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GK9ibnHa1Z8IoQ6QwDAdC2nEz3jRl7XV0EdxJ9FoW8wIyAfj6UU0MWUWpS9W?= =?us-ascii?Q?K2Q5L2ecZZsMfnHCIxdJEObVzMEGl1HZwteGJ498K12aUsP4K3lbhl9BuCtA?= =?us-ascii?Q?sc9YGjP+Ov5W9XKqoHIhcmKMETSaBQVdSrpztkaMdq808LYVXnXLHnv0znv7?= =?us-ascii?Q?wGnxU7wNOGd0XKOJo8qWRq/GrXczPRPDcOvwYqv/j59zKNtG6pLJv4Tm2Pfw?= =?us-ascii?Q?wvqJfN4Bj3/WBqefx0kNohGyOpD9lIuPRVvAxf2KA/9930JiLZX6S3Q7Mlks?= =?us-ascii?Q?cRQq0uCCDNdlOfzlvblgi8VXoCrojUVh8M6fgCdFqKgeog6vFc00auAG6RvE?= =?us-ascii?Q?LNB+G4mjyTkXfVnR2RJSmXC5p5+q6ER1IE07ickq00tZF3DabpruomP7yqgl?= =?us-ascii?Q?8ERG/8WmBIBuZYSdbz71/p+c09WoSzdoUPGZTPZDasBQTPdweFZo0WJn54lw?= =?us-ascii?Q?fQ+Dje/jpG2t0jQYXrXG6peTJWIW9qNgMiRKqX5prAhaq6TMNkLhiMr6+K5C?= =?us-ascii?Q?LcT7xBUq4z1ubdyCPMNCA4h5RhLPueZApr6eEQ8aYihrHWDEr9xB6Ivz6n4f?= =?us-ascii?Q?PBfwykkE5tylImhIevnyaoh6nVCpJSv5xJa6/A62Gwt8W7My870kHFNB4M/h?= =?us-ascii?Q?Nd1tTXDz9wPaNIrlKorRhFLDFjt2yNoWPRZMTslHOHo4Ff/K2O7u7Hxcwpv9?= =?us-ascii?Q?8mFpDHY7clb/uk8ZmB/7AjanpcnCYx2+6DuA2/tDHua00KrFzFRWJc+95hfx?= =?us-ascii?Q?vBWnh4PZis/cLxMDb5lQBWFlzylsGPnlZSZKufkHd3XTrSc/EjZ6BuSlxPYs?= =?us-ascii?Q?Q4fK4GzfDu2YNXjOrTiHEUji7ec1EevP3rUNboCdEJZV9JyKiOe2bM4zdfv2?= =?us-ascii?Q?qwu+v+s4ssauKGyQ2cIpxKVDlxq0dUE2OLw3kFgugUP/i6KOADDJSNKxMRiU?= =?us-ascii?Q?OdMYRmjyj97p3QQpbXbMtQfukM+Z3PgrvAmO0QRGOJmKAL7uwHtW1FL1wVOl?= =?us-ascii?Q?vQmi1XIkKWcbhUTZ8EzHxObdfqmqUUe/5QFoH5atDwqbNLE13FqZkub1dIcF?= =?us-ascii?Q?GxzEc2YkVwAYQLWpv+FxefmEUQrrfsWYKCHl6nwhLqtroC7q3teeRajiqpmK?= =?us-ascii?Q?anOin8X9KQthpQEv5YnPjeU5X0CpehDSniu6eXtg9G5qWPvvFk+uv+pUO7qH?= =?us-ascii?Q?0bPiu5AE+4FVUZS6lVdobt3m62mgcwZMuld6K2j0/P/ZZ1B2+9rOQp32Ctez?= =?us-ascii?Q?2Z+7APwKBIyU9vrMSAb1h1m9OIfC+ae7AF5/mHof/DW00qDJnWE9qy6VdNhs?= =?us-ascii?Q?1E/oQcEa7BJKYXPr+rhXVGcDujyizXayJVpcdW5vd4e5FhTdvNMpL9Rfa1UG?= =?us-ascii?Q?R49pB3cj70lW3P8YdMftKegTqJFup7/4FlQeKkdNt7BsNE74u73JLCJawOnE?= =?us-ascii?Q?lX8FzYMpx+xiYgyuV69yADQUdZdcrraOnwdObXGwk06SRT/E0DGSdSdrYm14?= =?us-ascii?Q?yLcYmw25Tv0Nk9bRnXwzAHmjtpK1jaqtG+hn?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:07.6765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a72f2b69-7ab2-45e5-47b8-08ddda21aa13 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66C9.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYUPR06MB5947 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe controller RP functionality into common functions and functions for legacy PCIe RP controller. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../cadence/pcie-cadence-ep-common.h | 8 +- .../cadence/pcie-cadence-host-common.c | 181 ++++++++++++++++++ .../cadence/pcie-cadence-host-common.h | 25 +++ .../controller/cadence/pcie-cadence-host.c | 156 +-------------- 5 files changed, 212 insertions(+), 160 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .h diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 80c1c4be7e80..e45f72388bbb 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o -obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o +obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-common.o pcie-caden= ce-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.h index a91084bdedd5..9cfd0cfa7459 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0 */ // Copyright (c) 2017 Cadence -// Cadence PCIe Endpoint controller driver. +// Cadence PCIe Endpoint controller driver // Author: Manikandan K Pillai =20 -#ifndef _PCIE_CADENCE_EP_COMMON_H_ -#define _PCIE_CADENCE_EP_COMMON_H_ +#ifndef _PCIE_CADENCE_EP_COMMON_H +#define _PCIE_CADENCE_EP_COMMON_H =20 #include #include @@ -33,4 +33,4 @@ const struct pci_epc_features *cdns_pcie_ep_get_features(= struct pci_epc *epc, u8 func_no, u8 vfunc_no); =20 -#endif /* _PCIE_CADENCE_EP_COMMON_H_ */ +#endif /* _PCIE_CADENCE_EP_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c new file mode 100644 index 000000000000..5625c64c7974 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define LINK_RETRAIN_TIMEOUT HZ + +u64 bar_max_size[] =3D { + [RP_BAR0] =3D _ULL(128 * SZ_2G), + [RP_BAR1] =3D SZ_2G, + [RP_NO_BAR] =3D _BITULL(63), +}; +EXPORT_SYMBOL_GPL(bar_max_size); + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) +{ + u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + unsigned long end_jiffies; + u16 lnk_stat; + + /* Wait for link training to complete. Exit after timeout. */ + end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; + do { + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + break; + usleep_range(0, 1000); + } while (time_before(jiffies, end_jiffies)); + + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + return 0; + + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_training_complete); + +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link); + +int cdns_pcie_retrain(struct cdns_pcie *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + int ret =3D 0; + + /* + * Set retrain bit if current speed is 2.5 GB/s, + * but the PCIe root port support is > 2.5 GB/s. + */ + + lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) + return ret; + + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl =3D cdns_pcie_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |=3D PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + ret =3D cdns_pcie_host_training_complete(pcie); + if (ret) + return ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + } + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_retrain); + +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + + /* + * Retrain link for Gen2 training defect + * if quirk flag is set. + */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size <=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] < bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_find_min_bar); + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size >=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] > bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_find_max_bar); + +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b) +{ + struct resource_entry *entry1, *entry2; + + entry1 =3D container_of(a, struct resource_entry, node); + entry2 =3D container_of(b, struct resource_entry, node); + + return resource_size(entry2->res) - resource_size(entry1->res); +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_dma_ranges_cmp); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.h new file mode 100644 index 000000000000..f8eae2e963d8 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_HOST_COMMON_H +#define _PCIE_CADENCE_HOST_COMMON_H + +#include +#include + +extern u64 bar_max_size[]; + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_retrain(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b); + +#endif /* _PCIE_CADENCE_HOST_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/p= ci/controller/cadence/pcie-cadence-host.c index 59a4631de79f..bfdd0f200cfb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -12,14 +12,7 @@ #include =20 #include "pcie-cadence.h" - -#define LINK_RETRAIN_TIMEOUT HZ - -static u64 bar_max_size[] =3D { - [RP_BAR0] =3D _ULL(128 * SZ_2G), - [RP_BAR1] =3D SZ_2G, - [RP_NO_BAR] =3D _BITULL(63), -}; +#include "pcie-cadence-host-common.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x1F, @@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops =3D { .write =3D pci_generic_config_write, }; =20 -static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) -{ - u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - unsigned long end_jiffies; - u16 lnk_stat; - - /* Wait for link training to complete. Exit after timeout. */ - end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; - do { - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - break; - usleep_range(0, 1000); - } while (time_before(jiffies, end_jiffies)); - - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - return 0; - - return -ETIMEDOUT; -} - -static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) -{ - struct device *dev =3D pcie->dev; - int retries; - - /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (cdns_pcie_link_up(pcie)) { - dev_info(dev, "Link up\n"); - return 0; - } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); - } - - return -ETIMEDOUT; -} - -static int cdns_pcie_retrain(struct cdns_pcie *pcie) -{ - u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - u16 lnk_stat, lnk_ctl; - int ret =3D 0; - - /* - * Set retrain bit if current speed is 2.5 GB/s, - * but the PCIe root port support is > 2.5 GB/s. - */ - - lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + - PCI_EXP_LNKCAP)); - if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) - return ret; - - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { - lnk_ctl =3D cdns_pcie_rp_readw(pcie, - pcie_cap_off + PCI_EXP_LNKCTL); - lnk_ctl |=3D PCI_EXP_LNKCTL_RL; - cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, - lnk_ctl); - - ret =3D cdns_pcie_host_training_complete(pcie); - if (ret) - return ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - } - return ret; -} - static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) { u32 val; @@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct c= dns_pcie *pcie) cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL= _PTMRSEN); } =20 -static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) -{ - struct cdns_pcie *pcie =3D &rc->pcie; - int ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - - /* - * Retrain link for Gen2 training defect - * if quirk flag is set. - */ - if (!ret && rc->quirk_retrain_flag) - ret =3D cdns_pcie_retrain(pcie); - - return ret; -} - static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; @@ -290,54 +195,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pc= ie_rc *rc, return 0; } =20 -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size <=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] < bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size >=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] > bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, struct resource_entry *entry) { @@ -410,17 +267,6 @@ static int cdns_pcie_host_bar_config(struct cdns_pcie_= rc *rc, return 0; } =20 -static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_hea= d *a, - const struct list_head *b) -{ - struct resource_entry *entry1, *entry2; - - entry1 =3D container_of(a, struct resource_entry, node); - entry2 =3D container_of(b, struct resource_entry, node); - - return resource_size(entry2->res) - resource_size(entry1->res); -} - static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; --=20 2.49.0 From nobody Sat Oct 4 21:00:49 2025 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023110.outbound.protection.outlook.com [52.101.127.110]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3963D2BEC25; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id AD2244143A8D; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 06/13] PCI: cadence: Split the common functions for PCIe controller support Date: Wed, 13 Aug 2025 12:23:24 +0800 Message-ID: <20250813042331.1258272-7-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C7:EE_|KU2PPF1A2CB34C0:EE_ X-MS-Office365-Filtering-Correlation-Id: 152ac205-c07c-4c7e-5b41-08ddda21aa59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?E9KQKkj87Lw6q/IYIPwU6TGZy3+rX5JGiKhTnULH/60U/VCIoiVTYttRzt2Y?= =?us-ascii?Q?A3R2/W1Tp+oBDr/5nyLi+mX4lEPLcfI3J+chx/3sK0PmZnBBCaEu+FGfLVCt?= =?us-ascii?Q?66BvByx6bwTnUrkNRDQxt0votId3r2OlS2QvHCcTfn7wV0UNmxKuyMWUBUsC?= =?us-ascii?Q?ElY7nLb+zd7AJQudwrIzkd1vUMmaxz7V3ehd8lE4/7GFrB/L1M5i5hxHQYjd?= =?us-ascii?Q?1xW9e/J2PRPpFmPJZjfL+FWbaIAvQyKcdLxilhzqSlhTcrewtskHj1Lpw6wk?= =?us-ascii?Q?ZwuRmrlTl8uKJPG/oKjx7PtL1G+pZk6nd5o2K488/b2khlwPqpn2iyWGkP87?= =?us-ascii?Q?/T63eFcsf5BehJiKmWD0pjLyBm1NJdRbmpA8RGFhWgWhWbBr2vA2OfXgN535?= =?us-ascii?Q?8DKLnckuXwZHsB+YvHkp8iBruQa06NBLiJcXdXYtzsTGbER5LKDDwzgrxJKG?= =?us-ascii?Q?JdOi0z9rszq0vVZmvIn3VMh7SgmaKakMs2piMFnD/VEXIktdPyLcRMEQTBSb?= =?us-ascii?Q?evAKIPfI66eOWlNMG0svV+2YGlBexbLq4xsdDE/L5/Vf3BAz1aS1Avt0iwRr?= =?us-ascii?Q?0hniDRIhk+ULvJLkjaPJeBYfXNVMgmwWhotUGkFPbx4yUssUWmMTeG4kmurz?= =?us-ascii?Q?QMR8cHfErOaKYuXyIwH1kgaIkAolwXNBeecVXlJUB8jODa9jrST8ga/GcvsL?= =?us-ascii?Q?GYF1zhuWOxaHWi5MPE15hSJixYy0YsEbOyAIFampMsjVkaXBONNZA0W0GFrT?= =?us-ascii?Q?PTFV+0KB6DjFsIcHzwwf8Fl+OdiBiP+jNzKmSCf5GelqTDyB2XKQzDE4Fkbn?= =?us-ascii?Q?ZFm1mrYJf5LnFX60n/PFy5LQZLrRzHa3QIq77mxvg5tOQMaR0zPz3QC4S8HD?= =?us-ascii?Q?d1dzNtJXMVh48wvlUIs6sqOuJcevXZNZUeBP3+OREKnQMFCNR/usWt9umI0x?= =?us-ascii?Q?gbMQ8qiy0QS4uBpC9MbysxhJF5w61Oe/9LJ1RCWHsrwJqBa/MRAOj+8mHwed?= =?us-ascii?Q?70XUYUKfQWopV3RL9estEoNnw1KHeVbotOsExoLnw7gM6PFOGRUYnp6RuZU2?= =?us-ascii?Q?2JeOY/CGm6ta5umO0OQsJWses3xBo/dpGe61gSi1lH6vIrgJRecNSixySgYt?= =?us-ascii?Q?ZHKyI62kBQ2zhH63/x5BD99zpujXfqlEZB6Li8Kl/1Yx6pUWwNrPuDoLOxBk?= =?us-ascii?Q?iNDefe0ZZXu+AiAhxoOHU2prlh0fB1+lyQtDQPKu5t8GIHPMf07CA5cvf/vX?= =?us-ascii?Q?YFiG7vZ9ecpr22YmpvuJiP/CioqYDUZxvqWOFC+a78/IOAcMLRyMQhshzrlE?= =?us-ascii?Q?PpbjhzR2TFHzWAnL4AyYg50g16UY9Twm1sbrnbVgdwPqoDV/fzm6hX+cg3vX?= =?us-ascii?Q?kBBmYKiW07ErWqK7hoSE98JTBXgvWbT+YecpsnMQNzq+MgZI8mGZrmsyCOty?= =?us-ascii?Q?ZVTek7xu6gcemnfneT0iTlrcn2uIRl/eP3h8HHj8duaAshw4nxkVIb+1h0G0?= =?us-ascii?Q?zIFCmyrIVK3opSGTyM0uHUbwyKfHbnloDm28?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:08.1133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 152ac205-c07c-4c7e-5b41-08ddda21aa59 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C7.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KU2PPF1A2CB34C0 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Separate the functions for platform specific tasks and common library tasks into different files. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../controller/cadence/pcie-cadence-common.c | 142 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.c | 129 ---------------- 3 files changed, 143 insertions(+), 130 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-common.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index e45f72388bbb..b104562fb86a 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-common.o pcie-caden= ce-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-common.c b/drivers= /pci/controller/cadence/pcie-cadence-common.c new file mode 100644 index 000000000000..23c5ab6637fb --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-common.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#include +#include + +#include "pcie-cadence.h" + +void cdns_pcie_disable_phy(struct cdns_pcie *pcie) +{ + int i =3D pcie->phy_count; + + while (i--) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } +} +EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); + +int cdns_pcie_enable_phy(struct cdns_pcie *pcie) +{ + int ret; + int i; + + for (i =3D 0; i < pcie->phy_count; i++) { + ret =3D phy_init(pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret =3D phy_power_on(pcie->phy[i]); + if (ret < 0) { + phy_exit(pcie->phy[i]); + goto err_phy; + } + } + + return 0; + +err_phy: + while (--i >=3D 0) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); + +int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) +{ + struct device_node *np =3D dev->of_node; + int phy_count; + struct phy **phy; + struct device_link **link; + int i; + int ret; + const char *name; + + phy_count =3D of_property_count_strings(np, "phy-names"); + if (phy_count < 1) { + dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); + pcie->phy_count =3D 0; + return 0; + } + + phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); + if (!link) + return -ENOMEM; + + for (i =3D 0; i < phy_count; i++) { + of_property_read_string_index(np, "phy-names", i, &name); + phy[i] =3D devm_phy_get(dev, name); + if (IS_ERR(phy[i])) { + ret =3D PTR_ERR(phy[i]); + goto err_phy; + } + link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); + if (!link[i]) { + devm_phy_put(dev, phy[i]); + ret =3D -EINVAL; + goto err_phy; + } + } + + pcie->phy_count =3D phy_count; + pcie->phy =3D phy; + pcie->link =3D link; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) + goto err_phy; + + return 0; + +err_phy: + while (--i >=3D 0) { + device_link_del(link[i]); + devm_phy_put(dev, phy[i]); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); + +static int cdns_pcie_suspend_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + + cdns_pcie_disable_phy(pcie); + + return 0; +} + +static int cdns_pcie_resume_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + int ret; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable PHY\n"); + return ret; + } + + return 0; +} + +const struct dev_pm_ops cdns_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, + cdns_pcie_resume_noirq) +}; +EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 5603f214f4c7..51c9bc4eb174 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -152,135 +152,6 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie= *pcie, u32 r) } EXPORT_SYMBOL_GPL(cdns_pcie_reset_outbound_region); =20 -void cdns_pcie_disable_phy(struct cdns_pcie *pcie) -{ - int i =3D pcie->phy_count; - - while (i--) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } -} -EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); - -int cdns_pcie_enable_phy(struct cdns_pcie *pcie) -{ - int ret; - int i; - - for (i =3D 0; i < pcie->phy_count; i++) { - ret =3D phy_init(pcie->phy[i]); - if (ret < 0) - goto err_phy; - - ret =3D phy_power_on(pcie->phy[i]); - if (ret < 0) { - phy_exit(pcie->phy[i]); - goto err_phy; - } - } - - return 0; - -err_phy: - while (--i >=3D 0) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); - -int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) -{ - struct device_node *np =3D dev->of_node; - int phy_count; - struct phy **phy; - struct device_link **link; - int i; - int ret; - const char *name; - - phy_count =3D of_property_count_strings(np, "phy-names"); - if (phy_count < 1) { - dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); - pcie->phy_count =3D 0; - return 0; - } - - phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); - if (!link) - return -ENOMEM; - - for (i =3D 0; i < phy_count; i++) { - of_property_read_string_index(np, "phy-names", i, &name); - phy[i] =3D devm_phy_get(dev, name); - if (IS_ERR(phy[i])) { - ret =3D PTR_ERR(phy[i]); - goto err_phy; - } - link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); - if (!link[i]) { - devm_phy_put(dev, phy[i]); - ret =3D -EINVAL; - goto err_phy; - } - } - - pcie->phy_count =3D phy_count; - pcie->phy =3D phy; - pcie->link =3D link; - - ret =3D cdns_pcie_enable_phy(pcie); - if (ret) - goto err_phy; - - return 0; - -err_phy: - while (--i >=3D 0) { - device_link_del(link[i]); - devm_phy_put(dev, phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); - -static int cdns_pcie_suspend_noirq(struct device *dev) -{ - struct cdns_pcie *pcie =3D dev_get_drvdata(dev); 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id B2A8041604E0; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 07/13] PCI: cadence: Add support for High Performance Arch(HPA) controller Date: Wed, 13 Aug 2025 12:23:25 +0800 Message-ID: <20250813042331.1258272-8-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB87:EE_|SI2PR06MB5314:EE_ X-MS-Office365-Filtering-Correlation-Id: d9828159-00a5-4c39-2f8a-08ddda21aabc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024|7053199007; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:08.7459 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9828159-00a5-4c39-2f8a-08ddda21aabc X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB87.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SI2PR06MB5314 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add support for Cadence PCIe RP and EP configuration for High Performance Architecture(HPA) controllers Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 10 +- .../controller/cadence/pcie-cadence-ep-hpa.c | 528 ++++++++++++++++ .../cadence/pcie-cadence-host-hpa.c | 586 ++++++++++++++++++ .../pci/controller/cadence/pcie-cadence-hpa.c | 207 +++++++ .../controller/cadence/pcie-cadence-plat.c | 20 +- drivers/pci/controller/cadence/pcie-cadence.c | 11 + drivers/pci/controller/cadence/pcie-cadence.h | 91 ++- 7 files changed, 1438 insertions(+), 15 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index b104562fb86a..de4ddae7aca4 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o -obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-common.o pcie-caden= ce-host.o -obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o +pcie-cadence-mod-y :=3D pcie-cadence-hpa.o pcie-cadence-common.o pcie-cade= nce.o +pcie-cadence-host-mod-y :=3D pcie-cadence-host-common.o pcie-cadence-host.= o pcie-cadence-host-hpa.o +pcie-cadence-ep-mod-y :=3D pcie-cadence-ep-common.o pcie-cadence-ep.o pcie= -cadence-ep-hpa.o + +obj-$(CONFIG_PCIE_CADENCE) =3D pcie-cadence-mod.o +obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-mod.o +obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-mod.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c b/drivers= /pci/controller/cadence/pcie-cadence-ep-hpa.c new file mode 100644 index 000000000000..36f757820f61 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe endpoint controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-ep-common.h" + +static int cdns_pcie_hpa_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u64 pci_addr, size_t size) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 r; + + r =3D find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG); + if (r >=3D ep->max_regions - 1) { + dev_err(&epc->dev, "no free outbound region\n"); + return -EINVAL; + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, = size); + + set_bit(r, &ep->ob_region_map); + ep->ob_addr[r] =3D addr; + + return 0; +} + +static void cdns_pcie_hpa_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 r; + + for (r =3D 0; r < ep->max_regions - 1; r++) + if (ep->ob_addr[r] =3D=3D addr) + break; + + if (r =3D=3D ep->max_regions - 1) + return; + + cdns_pcie_hpa_reset_outbound_region(pcie, r); + + ep->ob_addr[r] =3D 0; + clear_bit(r, &ep->ob_region_map); +} + +static void cdns_pcie_hpa_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u= 8 intx, + bool is_asserted) +{ + struct cdns_pcie *pcie =3D &ep->pcie; + unsigned long flags; + u32 offset; + u16 status; + u8 msg_code; + + intx &=3D 3; + + /* Set the outbound region if needed. */ + if (unlikely(ep->irq_pci_addr !=3D CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY || + ep->irq_pci_fn !=3D fn)) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, 0, fn, 0, ep->irq= _phys_addr); + ep->irq_pci_addr =3D CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY; + ep->irq_pci_fn =3D fn; + } + + if (is_asserted) { + ep->irq_pending |=3D BIT(intx); + msg_code =3D PCIE_MSG_CODE_ASSERT_INTA + intx; + } else { + ep->irq_pending &=3D ~BIT(intx); + msg_code =3D PCIE_MSG_CODE_DEASSERT_INTA + intx; + } + + spin_lock_irqsave(&ep->lock, flags); + status =3D cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); + if (((status & PCI_STATUS_INTERRUPT) !=3D 0) ^ (ep->irq_pending !=3D 0)) { + status ^=3D PCI_STATUS_INTERRUPT; + cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); + } + spin_unlock_irqrestore(&ep->lock, flags); + + offset =3D CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | + CDNS_PCIE_NORMAL_MSG_CODE(msg_code); + writel(0, ep->irq_cpu_addr + offset); +} + +static int cdns_pcie_hpa_ep_send_intx_irq(struct cdns_pcie_ep *ep, u8 fn, = u8 vfn, + u8 intx) +{ + u16 cmd; + + cmd =3D cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND); + if (cmd & PCI_COMMAND_INTX_DISABLE) + return -EINVAL; + + cdns_pcie_hpa_ep_assert_intx(ep, fn, intx, true); + + /* The mdelay() value was taken from dra7xx_pcie_raise_intx_irq() */ + mdelay(1); + cdns_pcie_hpa_ep_assert_intx(ep, fn, intx, false); + return 0; +} + +static int cdns_pcie_hpa_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u= 8 vfn, + u8 interrupt_num) +{ + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags, mme, data, data_mask; + u8 msi_count; + u64 pci_addr, pci_addr_mask =3D 0xff; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + msi_count =3D 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask =3D msi_count - 1; + data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data =3D (data & ~data_mask) | ((interrupt_num - 1) & data_mask); + + /* Get the PCI address where to write the data into. */ + pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<=3D 32; + pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &=3D GENMASK_ULL(63, 2); + + /* Set the outbound region if needed. */ + if (unlikely(ep->irq_pci_addr !=3D (pci_addr & ~pci_addr_mask) || + ep->irq_pci_fn !=3D fn)) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, 0, + false, + ep->irq_phys_addr, + pci_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr =3D (pci_addr & ~pci_addr_mask); + ep->irq_pci_fn =3D fn; + } + writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); + + return 0; +} + +static int cdns_pcie_hpa_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, = u8 vfn, + u16 interrupt_num) +{ + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 tbl_offset, msg_data, reg; + struct cdns_pcie *pcie =3D &ep->pcie; + struct pci_epf_msix_tbl *msix_tbl; + struct cdns_pcie_epf *epf; + u64 pci_addr_mask =3D 0xff; + u64 msg_addr; + u16 flags; + u8 bir; + + epf =3D &ep->epf[fn]; + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI-X feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS); + if (!(flags & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + reg =3D cap + PCI_MSIX_TABLE; + tbl_offset =3D cdns_pcie_ep_fn_readl(pcie, fn, reg); + bir =3D FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); + tbl_offset &=3D PCI_MSIX_TABLE_OFFSET; + + msix_tbl =3D epf->epf_bar[bir]->addr + tbl_offset; + msg_addr =3D msix_tbl[(interrupt_num - 1)].msg_addr; + msg_data =3D msix_tbl[(interrupt_num - 1)].msg_data; + + /* Set the outbound region if needed. */ + if (ep->irq_pci_addr !=3D (msg_addr & ~pci_addr_mask) || + ep->irq_pci_fn !=3D fn) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, 0, + false, + ep->irq_phys_addr, + msg_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr =3D (msg_addr & ~pci_addr_mask); + ep->irq_pci_fn =3D fn; + } + writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask)); + + return 0; +} + +static int cdns_pcie_hpa_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, + unsigned int type, u16 interrupt_num) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + struct device *dev =3D pcie->dev; + + switch (type) { + case PCI_IRQ_INTX: + if (vfn > 0) { + dev_err(dev, "Cannot raise INTX interrupts for VF\n"); + return -EINVAL; + } + return cdns_pcie_hpa_ep_send_intx_irq(ep, fn, vfn, 0); + + case PCI_IRQ_MSI: + return cdns_pcie_hpa_ep_send_msi_irq(ep, fn, vfn, interrupt_num); + + case PCI_IRQ_MSIX: + return cdns_pcie_hpa_ep_send_msix_irq(ep, fn, vfn, interrupt_num); + + default: + break; + } + + return -EINVAL; +} + +static int cdns_pcie_hpa_ep_start(struct pci_epc *epc) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + struct device *dev =3D pcie->dev; + int max_epfs =3D sizeof(epc->function_num_map) * 8; + int ret, epf, last_fn; + u32 reg, value; + + /* + * BIT(0) is hardwired to 1, hence function 0 is always enabled + * and can't be disabled anyway. + */ + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_LM_EP_FUNC_CFG, epc->function_num_map); + + /* + * Next function field in ARI_CAP_AND_CTR register for last function + * should be 0. Clear Next Function Number field for the last + * function used. + */ + last_fn =3D find_last_bit(&epc->function_num_map, BITS_PER_LONG); + reg =3D CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn); + value =3D cdns_pcie_readl(pcie, reg); + value &=3D ~CDNS_PCIE_ARI_CAP_NFN_MASK; + cdns_pcie_writel(pcie, reg, value); + + if (ep->quirk_disable_flr) { + for (epf =3D 0; epf < max_epfs; epf++) { + if (!(epc->function_num_map & BIT(epf))) + continue; + + value =3D cdns_pcie_ep_fn_readl(pcie, epf, + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP); + value &=3D ~PCI_EXP_DEVCAP_FLR; + cdns_pcie_ep_fn_writel(pcie, epf, + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP, value); + } + } + + ret =3D cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + return 0; +} + +static int cdns_pcie_hpa_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_bar *epf_bar) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie_epf *epf =3D &ep->epf[fn]; + struct cdns_pcie *pcie =3D &ep->pcie; + dma_addr_t bar_phys =3D epf_bar->phys_addr; + enum pci_barno bar =3D epf_bar->barno; + int flags =3D epf_bar->flags; + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; + u64 sz; + + /* BAR size is 2^(aperture + 7) */ + sz =3D max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE); + + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values. + */ + sz =3D 1ULL << fls64(sz - 1); + + /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ + aperture =3D ilog2(sz) - 7; + + if ((flags & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_IO) { + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS; + } else { + bool is_prefetch =3D !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); + bool is_64bits =3D !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64); + + if (is_64bits && (bar & 1)) + return -EINVAL; + + if (is_64bits && is_prefetch) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; + else if (is_prefetch) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; + else if (is_64bits) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS; + else + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS; + } + + addr0 =3D lower_32_bits(bar_phys); + addr1 =3D upper_32_bits(bar_phys); + + if (vfn =3D=3D 1) + reg =3D CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn); + else + reg =3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn); + b =3D (bar < BAR_4) ? bar : bar - BAR_4; + + if (vfn =3D=3D 0 || vfn =3D=3D 1) { + cfg =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, reg); + cfg &=3D ~(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |=3D (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, reg, cfg); + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), addr1); + + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + epf->epf_bar[bar] =3D epf_bar; + + return 0; +} + +static void cdns_pcie_hpa_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_bar *epf_bar) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie_epf *epf =3D &ep->epf[fn]; + struct cdns_pcie *pcie =3D &ep->pcie; + enum pci_barno bar =3D epf_bar->barno; + u32 reg, cfg, b, ctrl; + + if (vfn =3D=3D 1) + reg =3D CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn); + else + reg =3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn); + b =3D (bar < BAR_4) ? bar : bar - BAR_4; + + if (vfn =3D=3D 0 || vfn =3D=3D 1) { + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; + cfg =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, reg); + cfg &=3D ~(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |=3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, reg, cfg); + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); + + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + epf->epf_bar[bar] =3D NULL; +} + +static const struct pci_epc_ops cdns_pcie_hpa_epc_ops =3D { + .write_header =3D cdns_pcie_ep_write_header, + .set_bar =3D cdns_pcie_hpa_ep_set_bar, + .clear_bar =3D cdns_pcie_hpa_ep_clear_bar, + .map_addr =3D cdns_pcie_hpa_ep_map_addr, + .unmap_addr =3D cdns_pcie_hpa_ep_unmap_addr, + .set_msi =3D cdns_pcie_ep_set_msi, + .get_msi =3D cdns_pcie_ep_get_msi, + .set_msix =3D cdns_pcie_ep_set_msix, + .get_msix =3D cdns_pcie_ep_get_msix, + .raise_irq =3D cdns_pcie_hpa_ep_raise_irq, + .map_msi_irq =3D cdns_pcie_ep_map_msi_irq, + .start =3D cdns_pcie_hpa_ep_start, + .get_features =3D cdns_pcie_ep_get_features, +}; + +int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) +{ + struct device *dev =3D ep->pcie.dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct device_node *np =3D dev->of_node; + struct cdns_pcie *pcie =3D &ep->pcie; + struct cdns_pcie_epf *epf; + struct resource *res; + struct pci_epc *epc; + int ret; + int i; + + pcie->is_rc =3D false; + + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); + if (!res) { + dev_err(dev, "missing \"mem\"\n"); + return -EINVAL; + } + pcie->mem_res =3D res; + + ep->max_regions =3D CDNS_PCIE_MAX_OB; + of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions); + + ep->ob_addr =3D devm_kcalloc(dev, + ep->max_regions, sizeof(*ep->ob_addr), + GFP_KERNEL); + if (!ep->ob_addr) + return -ENOMEM; + + epc =3D devm_pci_epc_create(dev, &cdns_pcie_hpa_epc_ops); + if (IS_ERR(epc)) { + dev_err(dev, "failed to create epc device\n"); + return PTR_ERR(epc); + } + + epc_set_drvdata(epc, ep); + + if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) + epc->max_functions =3D 1; + + ep->epf =3D devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf), + GFP_KERNEL); + if (!ep->epf) + return -ENOMEM; + + epc->max_vfs =3D devm_kcalloc(dev, epc->max_functions, + sizeof(*epc->max_vfs), GFP_KERNEL); + if (!epc->max_vfs) + return -ENOMEM; + + ret =3D of_property_read_u8_array(np, "max-virtual-functions", + epc->max_vfs, epc->max_functions); + if (ret =3D=3D 0) { + for (i =3D 0; i < epc->max_functions; i++) { + epf =3D &ep->epf[i]; + if (epc->max_vfs[i] =3D=3D 0) + continue; + epf->epf =3D devm_kcalloc(dev, epc->max_vfs[i], + sizeof(*ep->epf), GFP_KERNEL); + if (!epf->epf) + return -ENOMEM; + } + } + + ret =3D pci_epc_mem_init(epc, pcie->mem_res->start, + resource_size(pcie->mem_res), PAGE_SIZE); + if (ret < 0) { + dev_err(dev, "failed to initialize the memory space\n"); + return ret; + } + + ep->irq_cpu_addr =3D pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, + SZ_128K); + if (!ep->irq_cpu_addr) { + dev_err(dev, "failed to reserve memory space for MSI\n"); + ret =3D -ENOMEM; + goto free_epc_mem; + } + ep->irq_pci_addr =3D CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; + /* Reserve region 0 for IRQs */ + set_bit(0, &ep->ob_region_map); + + if (ep->quirk_detect_quiet_flag) + cdns_pcie_hpa_detect_quiet_min_delay_set(&ep->pcie); + + spin_lock_init(&ep->lock); + + pci_epc_init_notify(epc); + + return 0; + + free_epc_mem: + pci_epc_mem_exit(epc); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_ep_setup); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-host-hpa.c new file mode 100644 index 000000000000..f930b745bc33 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c @@ -0,0 +1,586 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +static u8 bar_aperture_mask[] =3D { + [RP_BAR0] =3D 0x1F, + [RP_BAR1] =3D 0xF, +}; + +void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct pci_host_bridge *bridge =3D pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc =3D pci_host_bridge_priv(bridge); + struct cdns_pcie *pcie =3D &rc->pcie; + unsigned int busn =3D bus->number; + u32 addr0, desc0, desc1, ctrl0; + u32 regval; + + if (pci_is_root_bus(bus)) { + /* + * Only the root port (devfn =3D=3D 0) is connected to this bus. + * All other PCI devices are behind some bridge hence on another + * bus. + */ + if (devfn) + return NULL; + + return pcie->reg_base + (where & 0xfff); + } + + /* Clear AXI link-down status */ + regval =3D cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT= _LINKDOWN); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN, + (regval & ~GENMASK(0, 0))); + + desc0 =3D 0; + desc1 =3D 0; + ctrl0 =3D 0; + + /* Update Output registers for AXI region 0. */ + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) | + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0); + + desc1 =3D cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0)); + desc1 &=3D ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK; + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + + if (busn =3D=3D bridge->busnr + 1) + desc0 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; + else + desc0 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0); + + return rc->cfg_base + (where & 0xfff); +} + +int cdns_pcie_hpa_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_wait_for_link); + +int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + + /* + * Retrain link for Gen2 training defect + * if quirk flag is set. + */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_start_link); + +static struct pci_ops cdns_pcie_hpa_host_ops =3D { + .map_bus =3D cdns_pci_hpa_map_bus, + .read =3D pci_generic_config_read, + .write =3D pci_generic_config_write, +}; + +static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie) +{ + u32 val; + + val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_C= TRL); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL, + val | CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN); +} + +static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc, + enum cdns_pcie_rp_bar bar, + u64 cpu_addr, u64 size, + unsigned long flags) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + u32 addr0, addr1, aperture, value; + + if (!rc->avail_ib_bar[bar]) + return -EBUSY; + + rc->avail_ib_bar[bar] =3D false; + + aperture =3D ilog2(size); + addr0 =3D CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, + CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, + CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1); + + if (bar =3D=3D RP_NO_BAR) + return 0; + + value =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_H= PA_LM_RC_BAR_CFG); + value &=3D ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | + HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2)); + if (size + cpu_addr >=3D SZ_4G) { + if (!(flags & IORESOURCE_PREFETCH)) + value |=3D HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); + value |=3D HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); + } else { + if (!(flags & IORESOURCE_PREFETCH)) + value |=3D HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); + value |=3D HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); + } + + value |=3D HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_= BAR_CFG, value); + + return 0; +} + +static int cdns_pcie_hpa_host_bar_config(struct cdns_pcie_rc *rc, + struct resource_entry *entry) +{ + u64 cpu_addr, pci_addr, size, winsize; + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + enum cdns_pcie_rp_bar bar; + unsigned long flags; + int ret; + + cpu_addr =3D entry->res->start; + pci_addr =3D entry->res->start - entry->offset; + flags =3D entry->res->flags; + size =3D resource_size(entry->res); + + if (entry->offset) { + dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n", + pci_addr, cpu_addr); + return -EINVAL; + } + + while (size > 0) { + /* + * Try to find a minimum BAR whose size is greater than + * or equal to the remaining resource_entry size. This will + * fail if the size of each of the available BARs is less than + * the remaining resource_entry size. + * If a minimum BAR is found, IB ATU will be configured and + * exited. + */ + bar =3D cdns_pcie_host_find_min_bar(rc, size); + if (bar !=3D RP_BAR_UNDEFINED) { + ret =3D cdns_pcie_hpa_host_bar_ib_config(rc, bar, cpu_addr, + size, flags); + if (ret) + dev_err(dev, "IB BAR: %d config failed\n", bar); + return ret; + } + + /* + * If the control reaches here, it would mean the remaining + * resource_entry size cannot be fitted in a single BAR. So we + * find a maximum BAR whose size is less than or equal to the + * remaining resource_entry size and split the resource entry + * so that part of resource entry is fitted inside the maximum + * BAR. The remaining size would be fitted during the next + * iteration of the loop. + * If a maximum BAR is not found, there is no way we can fit + * this resource_entry, so we error out. + */ + bar =3D cdns_pcie_host_find_max_bar(rc, size); + if (bar =3D=3D RP_BAR_UNDEFINED) { + dev_err(dev, "No free BAR to map cpu_addr %llx\n", + cpu_addr); + return -EINVAL; + } + + winsize =3D bar_max_size[bar]; + ret =3D cdns_pcie_hpa_host_bar_ib_config(rc, bar, cpu_addr, winsize, fla= gs); + if (ret) { + dev_err(dev, "IB BAR: %d config failed\n", bar); + return ret; + } + + size -=3D winsize; + cpu_addr +=3D winsize; + } + + return 0; +} + +static int cdns_pcie_hpa_host_map_dma_ranges(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + struct device_node *np =3D dev->of_node; + struct pci_host_bridge *bridge; + struct resource_entry *entry; + u32 no_bar_nbits =3D 32; + int err; + + bridge =3D pci_host_bridge_from_priv(rc); + if (!bridge) + return -ENOMEM; + + if (list_empty(&bridge->dma_ranges)) { + of_property_read_u32(np, "cdns,no-bar-match-nbits", + &no_bar_nbits); + err =3D cdns_pcie_hpa_host_bar_ib_config(rc, RP_NO_BAR, 0x0, + (u64)1 << no_bar_nbits, 0); + if (err) + dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); + return err; + } + + list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); + + resource_list_for_each_entry(entry, &bridge->dma_ranges) { + err =3D cdns_pcie_hpa_host_bar_config(rc, entry); + if (err) { + dev_err(dev, "Fail to configure IB using dma-ranges\n"); + return err; + } + } + + return 0; +} + +static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + u32 value, ctrl; + + /* + * Set the root complex BAR configuration register: + * - disable both BAR0 and BAR1. + * - enable Prefetchable Memory Base and Limit registers in type 1 + * config space (64 bits). + * - enable IO Base and Limit registers in type 1 config + * space (32 bits). + */ + + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; + value =3D CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, + CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); + + if (rc->vendor_id !=3D 0xffff) + cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); + + if (rc->device_id !=3D 0xffff) + cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); + + cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0); + cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0); + cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); + + return 0; +} + +static void cdns_pcie_hpa_create_region_for_ecam(struct cdns_pcie_rc *rc) +{ + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource *cfg_res =3D rc->cfg_res; + struct cdns_pcie *pcie =3D &rc->pcie; + u32 value, root_port_req_id_reg, pcie_bus_number_reg; + u32 ecam_addr_0, region_size_0, request_id_0; + int busnr =3D 0, secbus =3D 0, subbus =3D 0; + struct resource_entry *entry; + resource_size_t size; + u32 axi_address_low; + int nbits; + u64 sz; + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) { + busnr =3D entry->res->start; + secbus =3D (busnr < 0xff) ? (busnr + 1) : 0xff; + subbus =3D entry->res->end; + } + size =3D resource_size(cfg_res); + sz =3D 1ULL << fls64(size - 1); + nbits =3D ilog2(sz); + if (nbits < 8) + nbits =3D 8; + + root_port_req_id_reg =3D ((busnr & 0xff) << 8); + pcie_bus_number_reg =3D ((subbus & 0xff) << 16) | ((secbus & 0xff) << 8) | + (busnr & 0xff); + ecam_addr_0 =3D cfg_res->start; + region_size_0 =3D nbits - 1; + request_id_0 =3D ((busnr & 0xff) << 8); + +#define CDNS_PCIE_HPA_TAG_MANAGEMENT (0x0) + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x200000); + + /* Taking slave err as OKAY */ +#define CDNS_PCIE_HPA_SLAVE_RESP (0x100) + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_SLAVE_RESP, + 0x0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_SLAVE_RESP + 0x4, 0x0); + + /* Program the register "i_root_port_req_id_reg" with RP's BDF */ +#define I_ROOT_PORT_REQ_ID_REG (0x141c) + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, I_ROOT_PORT_REQ_ID_REG, + root_port_req_id_reg); + + /** + * Program the register "i_pcie_bus_numbers" with Primary(RP's bus number= ), + * secondary and subordinate bus numbers + */ +#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18) + cdns_pcie_hpa_writel(pcie, REG_BANK_RP, I_PCIE_BUS_NUMBERS, + pcie_bus_number_reg); + + /* Program the register "lm_hal_sbsa_ctrl[0]" to enable the sbsa */ +#define LM_HAL_SBSA_CTRL (0x1170) + value =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, LM_HAL_SBSA_CTRL); + value |=3D BIT(0); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, LM_HAL_SBSA_CTRL, value); + + /* Program region[0] for ECAM */ + axi_address_low =3D (ecam_addr_0 & 0xfff00000) | region_size_0; + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), + axi_address_low); + + /* rc0-high-axi-address */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), 0x0); + /* Type-1 CFG */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), + (request_id_0 << 16)); + + /* All AXI bits pass through PCIe */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), 0x1b); + /* PCIe address-high */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000); +} + +static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource *cfg_res =3D rc->cfg_res; + struct resource_entry *entry; + u64 cpu_addr =3D cfg_res->start; + u32 addr0, addr1, desc1; + int busnr =3D 0; + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr =3D entry->res->start; + + /* + * Reserve region 0 for PCI configure space accesses: + * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by + * cdns_pci_map_bus(), other region registers are set here once for all. + */ + addr1 =3D 0; + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1); +} + +static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc= *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource_entry *entry; + int r =3D 0, busnr =3D 0; + + if (rc->ecam_support_flag) + cdns_pcie_hpa_create_region_for_ecam(rc); + else + cdns_pcie_hpa_create_region_for_cfg(rc); + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr =3D entry->res->start; + + r++; + if (pcie->msg_res) + cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r, + pcie->msg_res->start); + + r++; + resource_list_for_each_entry(entry, &bridge->windows) { + struct resource *res =3D entry->res; + u64 pci_addr =3D res->start - entry->offset; + + if (resource_type(res) =3D=3D IORESOURCE_IO) + cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, + true, + pci_pio_to_address(res->start), + pci_addr, + resource_size(res)); + else + cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, + false, + res->start, + pci_addr, + resource_size(res)); + + r++; + } + + if (rc->no_inbound_flag) + return 0; + else + return cdns_pcie_hpa_host_map_dma_ranges(rc); +} + +int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc) +{ + int err; + + err =3D cdns_pcie_hpa_host_init_root_port(rc); + if (err) + return err; + + return cdns_pcie_hpa_host_init_address_translation(rc); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_init); + +int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D rc->pcie.dev; + int ret; + + if (rc->quirk_detect_quiet_flag) + cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie); + + cdns_pcie_hpa_host_enable_ptm_response(pcie); + + ret =3D cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + ret =3D cdns_pcie_hpa_host_start_link(rc); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup); + +int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) +{ + struct device *dev =3D rc->pcie.dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct pci_host_bridge *bridge; + enum cdns_pcie_rp_bar bar; + struct cdns_pcie *pcie; + struct resource *res; + int ret; + + bridge =3D pci_host_bridge_from_priv(rc); + if (!bridge) + return -ENOMEM; + + pcie =3D &rc->pcie; + pcie->is_rc =3D true; + + if (!pcie->reg_base) { + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + } + + /* ECAM config space is remapped at glue layer */ + if (!rc->cfg_base) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + rc->cfg_base =3D devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(rc->cfg_base)) + return PTR_ERR(rc->cfg_base); + rc->cfg_res =3D res; + } + + ret =3D cdns_pcie_hpa_host_link_setup(rc); + if (ret) + return ret; + + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) + rc->avail_ib_bar[bar] =3D true; + + ret =3D cdns_pcie_hpa_host_init(rc); + if (ret) + return ret; + + if (!bridge->ops) + bridge->ops =3D &cdns_pcie_hpa_host_ops; + + return pci_host_probe(bridge); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa.c b/drivers/pc= i/controller/cadence/pcie-cadence-hpa.c new file mode 100644 index 000000000000..1152d2dcae77 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver +// Author: Manikandan K Pillai + +#include +#include + +#include "pcie-cadence.h" + +bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_DBG_STS_REG0); + if (pl_reg_val & GENMASK(0, 0)) + return true; + return false; +} + +int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_LAYER_CFG0); + pl_reg_val |=3D CDNS_PCIE_HPA_LINK_TRNG_EN_MASK; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_LAYER_CFG0,= pl_reg_val); + return 0; +} + +void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_LAYER_CFG0); + pl_reg_val &=3D ~CDNS_PCIE_HPA_LINK_TRNG_EN_MASK; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_LAYER_CFG0,= pl_reg_val); +} + +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie) +{ + u32 delay =3D 0x3; + u32 ltssm_control_cap; + + /* + * Set the LTSSM Detect Quiet state min. delay to 2ms. + */ + ltssm_control_cap =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_LAYER_CFG0); + ltssm_control_cap =3D ((ltssm_control_cap & + ~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) | + CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay)); + + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_detect_quiet_min_delay_set); + +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u= 8 fn, + u32 r, bool is_io, + u64 cpu_addr, u64 pci_addr, size_t size) +{ + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values. + */ + u64 sz =3D 1ULL << fls64(size - 1); + int nbits =3D ilog2(sz); + u32 addr0, addr1, desc0, desc1, ctrl0; + + if (nbits < 8) + nbits =3D 8; + + /* Set the PCI address */ + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | + (lower_32_bits(pci_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(pci_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1); + + /* Set the PCIe header descriptor */ + if (is_io) + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO; + else + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM; + desc1 =3D 0; + ctrl0 =3D 0; + + /* + * Whether Bit [26] is set or not inside DESC0 register of the outbound + * PCIe descriptor, the PCI function number must be set into + * Bits [31:24] of DESC1 anyway. + * + * In Root Complex mode, the function number is always 0 but in Endpoint + * mode, the PCIe controller may support more than one function. This + * function number needs to be set properly into the outbound PCIe + * descriptor. + * + * Besides, setting Bit [26] is mandatory when in Root Complex mode: + * then the driver must provide the bus, resp. device, number in + * Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function + * number, the device number is always 0 in Root Complex mode. + * + * However when in Endpoint mode, we can clear Bit [26] of DESC0, hence + * the PCIe controller will use the captured values for the bus and + * device numbers. + */ + if (pcie->is_rc) { + /* The device and function numbers are always 0. */ + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | + CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + } else { + /* + * Use captured values for bus and device numbers but still + * need to set the function number. + */ + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); + } + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region); + +void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pc= ie, + u8 busnr, u8 fn, + u32 r, u64 cpu_addr) +{ + u32 addr0, addr1, desc0, desc1, ctrl0; + + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG; + desc1 =3D 0; + ctrl0 =3D 0; + + /* + * See cdns_pcie_set_outbound_region() comments above. + */ + if (pcie->is_rc) { + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | + CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + } else { + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); + } + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region_for_normal_msg); + +void cdns_pcie_hpa_reset_outbound_region(struct cdns_pcie *pcie, u32 r) +{ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), 0); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), 0); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_reset_outbound_region); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index ced030cc0fda..6ce18a0cf564 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -12,8 +12,7 @@ #include #include "pcie-cadence.h" =20 -#define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF - +void cdns_pcie_disable_phy(struct cdns_pcie *pcie); /** * struct cdns_plat_pcie - private data for this PCIe platform driver * @pcie: Cadence PCIe controller @@ -24,13 +23,8 @@ struct cdns_plat_pcie { =20 static const struct of_device_id cdns_plat_pcie_of_match[]; =20 -static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) -{ - return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR; -} - static const struct cdns_pcie_ops cdns_plat_ops =3D { - .cpu_addr_fixup =3D cdns_plat_cpu_addr_fixup, + .link_up =3D cdns_pcie_linkup, }; =20 static int cdns_plat_pcie_probe(struct platform_device *pdev) @@ -68,6 +62,11 @@ static int cdns_plat_pcie_probe(struct platform_device *= pdev) rc =3D pci_host_bridge_priv(bridge); rc->pcie.dev =3D dev; rc->pcie.ops =3D &cdns_plat_ops; + rc->pcie.is_rc =3D data->is_rc; + + /* Store the register bank offsets pointer */ + rc->pcie.cdns_pcie_reg_offsets =3D data; + cdns_plat_pcie->pcie =3D &rc->pcie; =20 ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); @@ -95,6 +94,11 @@ static int cdns_plat_pcie_probe(struct platform_device *= pdev) =20 ep->pcie.dev =3D dev; ep->pcie.ops =3D &cdns_plat_ops; + ep->pcie.is_rc =3D data->is_rc; + + /* Store the register bank offset pointer */ + ep->pcie.cdns_pcie_reg_offsets =3D data; + cdns_plat_pcie->pcie =3D &ep->pcie; =20 ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 51c9bc4eb174..aaf921ea70e0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -9,6 +9,17 @@ =20 #include "pcie-cadence.h" =20 +bool cdns_pcie_linkup(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); + if (pl_reg_val & GENMASK(0, 0)) + return true; + return false; +} +EXPORT_SYMBOL_GPL(cdns_pcie_linkup); + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { u32 delay =3D 0x3; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 8048bef215d0..3e0fd6bb21b1 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -7,10 +7,12 @@ #define _PCIE_CADENCE_H =20 #include +#include #include #include #include #include + #include "pcie-cadence-lga-regs.h" #include "pcie-cadence-hpa-regs.h" =20 @@ -29,6 +31,26 @@ struct cdns_pcie_rp_ib_bar { struct cdns_pcie; struct cdns_pcie_rc; =20 +enum cdns_pcie_msg_routing { + /* Route to Root Complex */ + MSG_ROUTING_TO_RC, + + /* Use Address Routing */ + MSG_ROUTING_BY_ADDR, + + /* Use ID Routing */ + MSG_ROUTING_BY_ID, + + /* Route as Broadcast Message from Root Complex */ + MSG_ROUTING_BCAST, + + /* Local message; terminate at receiver (INTx messages) */ + MSG_ROUTING_LOCAL, + + /* Gather & route to Root Complex (PME_TO_Ack message) */ + MSG_ROUTING_GATHER, +}; + enum cdns_pcie_reg_bank { REG_BANK_RP, REG_BANK_IP_REG, @@ -43,9 +65,9 @@ enum cdns_pcie_reg_bank { }; =20 struct cdns_pcie_ops { - int (*start_link)(struct cdns_pcie *pcie); - void (*stop_link)(struct cdns_pcie *pcie); - bool (*link_up)(struct cdns_pcie *pcie); + int (*start_link)(struct cdns_pcie *pcie); + void (*stop_link)(struct cdns_pcie *pcie); + bool (*link_up)(struct cdns_pcie *pcie); u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 @@ -77,6 +99,7 @@ struct cdns_plat_pcie_of_data { * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base * @mem_res: start/end offsets in the physical system memory to map PCI ac= cesses + * @msg_res: Region for send message to map PCI accesses * @dev: PCIe controller * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoi= nt. * @phy_count: number of supported PHY devices @@ -89,6 +112,7 @@ struct cdns_plat_pcie_of_data { struct cdns_pcie { void __iomem *reg_base; struct resource *mem_res; + struct resource *msg_res; struct device *dev; bool is_rc; int phy_count; @@ -111,6 +135,7 @@ struct cdns_pcie { * available * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk + * @ecam_support_flag: Whether the ECAM flag is supported */ struct cdns_pcie_rc { struct cdns_pcie pcie; @@ -121,6 +146,8 @@ struct cdns_pcie_rc { bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; unsigned int quirk_retrain_flag:1; unsigned int quirk_detect_quiet_flag:1; + unsigned int ecam_support_flag:1; + unsigned int no_inbound_flag:1; }; =20 /** @@ -304,6 +331,29 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie = *pcie, u32 reg) return cdns_pcie_read_sz(addr, 0x2); } =20 +static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, + u32 reg, u8 value) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x1, value); +} + +static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie, + u32 reg, u16 value) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x2, value); +} + +static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) @@ -368,6 +418,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); #else static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) { @@ -384,6 +435,11 @@ static inline int cdns_pcie_host_setup(struct cdns_pci= e_rc *rc) return 0; } =20 +static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) +{ + return 0; +} + static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) { } @@ -398,17 +454,25 @@ static inline void __iomem *cdns_pci_map_bus(struct p= ci_bus *bus, unsigned int d #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); +int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep); #else static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) { return 0; } =20 +static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) +{ + return 0; +} + static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) { } #endif - +bool cdns_pcie_linkup(struct cdns_pcie *pcie); +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, u32 r, bool is_io, @@ -421,6 +485,25 @@ void cdns_pcie_disable_phy(struct cdns_pcie *pcie); int cdns_pcie_enable_phy(struct cdns_pcie *pcie); int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); =20 +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie); +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u= 8 fn, + u32 r, bool is_io, + u64 cpu_addr, u64 pci_addr, size_t size); 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id C242241604E5; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 08/13] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings Date: Wed, 13 Aug 2025 12:23:26 +0800 Message-ID: <20250813042331.1258272-9-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E8:EE_|JH0PR06MB6776:EE_ X-MS-Office365-Filtering-Correlation-Id: 30643d32-2f17-4c61-5a1b-08ddda21aa68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?IfFKWGs1QOa/zzCAAIYhKpmGHRz6BuEkwCgH0FRu5qJMQ+KDtXrkuSNizhDw?= =?us-ascii?Q?F6GQKfxMf5kemB+TsO5Lf3rMTlXITfnmwspLT3PHXOkCT/OjkTNskCN/L/aD?= =?us-ascii?Q?toBRbF4mET+M5lLct24+zq4WTENL5Q8BvAgMjjzIY062bbyQBSTJ7gC43A+P?= =?us-ascii?Q?q3PkprfOfza73HG2HIUwpv4dmZslNy1DvqwRO5rX2OcAGta86hS6DYlhXzoM?= =?us-ascii?Q?snxgdRS6l/CAPioK/aB9ibblUhDd2yempKqnnHuvnL8acNLykL2+QP14CDoK?= =?us-ascii?Q?TwoqRtBKbzoJc0Pk9tQQad6iEgZ80IwqeelZPDtqUGCgWAnnOQ9z3+GzH5ZY?= =?us-ascii?Q?4nkerIa6lFW0eMPaV1lh93KNOj/xFlJxJfU2LLMwCcXesWnoVQqwmbbyamFI?= =?us-ascii?Q?23O6Ue3Ljq1b3t5MlvjbLOPO/E8qijAR676v4m6PCoNS4BdJc0gTdijBOO4B?= =?us-ascii?Q?YdCrhB7VOa3MMKSP3Ecpn6Cj/oShePYBri4Wmd499ZwpINcK8V22xMghRv0t?= =?us-ascii?Q?oORPh/YmqZOOkIjQqSNVOURZzxZJcAWk/AdZQBJM/TCqg170/i/IR2DPmhtM?= =?us-ascii?Q?O4jBj91BLzsaYT9UW0bllSJmjuMZd+IjvVlFiX/1BbV3N4LuBHPQguMifLlA?= =?us-ascii?Q?0neluPIN4cDvOs4i/Jf0ePCrZ76SOv+1lVSmo5sSoxLemHe4F/io+upV1Xs0?= =?us-ascii?Q?hWziCiXsH+fG1ByNqjBxJjbj5fP6hXI58o2webh75XTbqJ2NO4pmwZ5zT9Rw?= =?us-ascii?Q?zziP/Wk9+Ir8Xx2o/RL4aLy9DgHh1tKPA7dag2aXth9w9uzdaL77o0iYBt1R?= =?us-ascii?Q?To7gP/yG+uF0/Pixpudwh5ra1WAh99aC32PaoIqtu0Fs9UUftCsSJG1xXAeR?= =?us-ascii?Q?CU64KFzdhEtMtMIHjh9qgctkT2YcVxzV8rcYh3O+/OpcRhcVm7yxvUes/R6i?= =?us-ascii?Q?Guha3AeRqlBWoAXiNzJ/mVbQ678r0OWrVaZU/PEdja5Qcy0NAgyW9HElia/H?= =?us-ascii?Q?mRebMw+pQI/26TGLUG7QiC8cFvYEJlem0IqEhh2Wxjpg76z+mcISdUx01ML7?= =?us-ascii?Q?H/LA81nGHH97jKVbM9oC/I6lzLFeglQ26FTn5UE9Yy/RzKIjQcqkcI1G5K2s?= =?us-ascii?Q?zAXQDweXJyAz13ljcYUat2yzLDtPNdAX9rt3LD8vbrTKt2zEXcpXRM3J2E5I?= =?us-ascii?Q?ViD3jEPkw49oHqBe1kl26S3dpMT7u31tIQjNo5648iE3DTSg4Dbtr5IizANC?= =?us-ascii?Q?Xcq+HeJMvZFV2UD6q7ZJl9a88fBIpvCJmbEQqqAX9PnoUvQEMxj1Rv2fdevD?= =?us-ascii?Q?CfgeAxA4rHlDfenEeWrwVe8sXDJ0HXzH3AFLyMz6h7D57HE/GOVl49kI/xT3?= =?us-ascii?Q?4lW0nLlS6FTh7x66P1LsrhkC9JYRcuH9qKTNPCGarNYyqV92QQwT6NTj2mej?= =?us-ascii?Q?oojdOHRAX/JPaP+lDyXZLBvwHRNDA/hWrQILKBFX/blrLZ9h2cK1Rg=3D=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:08.2392 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30643d32-2f17-4c61-5a1b-08ddda21aa68 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: JH0PR06MB6776 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Document the bindings for CIX Sky1 PCIe Controller configured in root complex mode with five root port. Supports 4 INTx, MSI and MSI-x interrupts from the ARM GICv3 controller. Signed-off-by: Hans Zhang --- .../bindings/pci/cix,sky1-pcie-host.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/cix,sky1-pcie-hos= t.yaml diff --git a/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml = b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml new file mode 100644 index 000000000000..2bd66603ac24 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 PCIe Root Complex + +maintainers: + - Hans Zhang + +description: + PCIe root complex controller based on the Cadence PCIe core. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + const: cix,sky1-pcie-host + + reg: + items: + - description: PCIe controller registers. + - description: ECAM registers. + - description: Remote CIX System Unit registers. + - description: Region for sending messages registers. + + reg-names: + items: + - const: reg + - const: cfg + - const: rcsu + - const: msg + + ranges: + maxItems: 3 + +required: + - compatible + - ranges + - bus-range + - device_type + - interrupt-map + - interrupt-map-mask + - msi-map + +unevaluatedProperties: false + +examples: + - | + #include + / { + #address-cells =3D <2>; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id C6BB241604E6; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 09/13] PCI: Add Cix Technology Vendor and Device ID Date: Wed, 13 Aug 2025 12:23:27 +0800 Message-ID: <20250813042331.1258272-10-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CD:EE_|TYSPR06MB6315:EE_ X-MS-Office365-Filtering-Correlation-Id: dc502970-b2c1-48bc-544d-08ddda21ab08 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?O0NGO0SvYAdhCMT+h9WtNKVFOWzHSiFdxTaBRMeJXNadAZ72QZwF05SyurHL?= =?us-ascii?Q?Nn4Tc+LZxO1uGVjxM4/L6vBH9J0Zlu8HH0uenU/vat6oLUgbKs5ekE8KMKvk?= =?us-ascii?Q?5VcGUoRJETLgsOLqPjnESbQjRxDPFAFrcuz5qa6Gx4em7kMxuAt8kSMAGF8J?= =?us-ascii?Q?vc789ZLgKyXm3ELmgOM+F6BDXI/BMcpTsEXgY6t2QsOjQI9ccf6IC9zYgeVH?= =?us-ascii?Q?szV6YncxFY9iRqKqdhjDKP81/WXlBg/x5a/h+IDhK750Onlx5PbtlOAltM6q?= =?us-ascii?Q?pSZAh8MO6udifk9vmXbjal1o3ms2mVC+TsUBChFdRhGnZ4T8S/dytGbSpNnX?= =?us-ascii?Q?wF247dctjJ5fzD69kP+n9cyvlJHCbNf172f5xjcEcAscVQf2XZkOnTXD1897?= =?us-ascii?Q?+Z2eos8cVNxfqQimebXKZ8bO5dNHlnrjbk6g+05+oQj56DmMAxsXuO9k5osj?= =?us-ascii?Q?K78QidffClIPrWi3jTuK/gQSSrQ8M5RhXPQBq03V4PRhBiRPhckoJD/beaP6?= =?us-ascii?Q?bSLhctOFMGPQQTliGzus6Um0BrUTO2g0LibVRMnfTPKsx7d0fO+wVN3BsViw?= =?us-ascii?Q?QpFM9F4GzFfDfE1GcEipAwlJI68xBZznicBfekTq7EsuCC9p6V7PAryoZBz8?= =?us-ascii?Q?+KppIyGzi+h7DqAduP3EiuP+u45AgeSPVJ5CpPy1f29j43Jb7ab0to68UELb?= =?us-ascii?Q?eMN4FguzylVW6qxN1GGt7/VQC0XAlb5fWazyynY7v33eduMcHx+Kqf4KVqoA?= =?us-ascii?Q?sOERq0JWKy41yYvSFZM+5q6lDbf+Ot6N5TcW9OX3LSSaRTkiqcBwMXjWgk7A?= =?us-ascii?Q?hBYPgI0qL1FJBa005dvTNS73yLJZZdt3vbwGtJSxlxd78oioP1V0UktL2zzv?= =?us-ascii?Q?45X2DD+DKm0VI1AgtxCBxEOn0etyQGETJkHg7MsxEhyk/16k2vuNZkCnczf7?= =?us-ascii?Q?horNlYuVSVp760UKXnTdFzComiCHaoJS4mAR/1mBxWPyNeQp6aps+7fTDHjJ?= =?us-ascii?Q?mBY7ySK/X09GmSQ10CGrAmDjnySATs1j8OidyyqTojLQJYiSjzcTTVfpaepS?= =?us-ascii?Q?pW97LDDDz9heoNlqCFmPG3gOOTHfQNwyXiu71Eo6gs6OtpfNYJVbAvWYAoWB?= =?us-ascii?Q?8q3rS53AoYyM//caC7RRXj267suu5LUQCKQRa3Ncor4jIwjAVSyl4rQd3/D0?= =?us-ascii?Q?/FeB6vg9q2QX169ysogLt2YMGD+jv3WbyZkoPx2g+n1Td3ZQ7+GA6H/lgsma?= =?us-ascii?Q?TFqAFJkVGwWXvJBesVoiEUp6rAaB5+GpkayQM059jfFoTE4SHrV8D3kocr3H?= =?us-ascii?Q?CV7/OJlLBi4v/ZT/P4PNlJmD/V32nhnT8X9F/VOByXCLzhkwlRb7w53BIexj?= =?us-ascii?Q?ABEzvBv9rRZeycW0Yr3abdcAGwAveGSkopLbbHn1QHCEQigcuuB8CXcHOS+5?= =?us-ascii?Q?1w0hiIxDZys+vyAJOEpvICT0XwixbniRG08EEhEEsc96efh/kMy2mTNxZi2P?= =?us-ascii?Q?d1nv2QfJelUy6O9YcdrSypEhfQkcQtez29nA?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:09.2455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc502970-b2c1-48bc-544d-08ddda21ab08 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CD.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6315 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add Cixtech P1 (internal name sky1) as a vendor and device ID for PCI devices. This ID will be used by the CIX Sky1 PCIe host controller driver. Signed-off-by: Hans Zhang --- include/linux/pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 92ffc4373f6d..24b04d085920 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2631,6 +2631,9 @@ =20 #define PCI_VENDOR_ID_CXL 0x1e98 =20 +#define PCI_VENDOR_ID_CIX 0x1f6c +#define PCI_DEVICE_ID_CIX_SKY1 0x0001 + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 --=20 2.49.0 From nobody Sat Oct 4 21:00:50 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023083.outbound.protection.outlook.com [40.107.44.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E2672BE045; Wed, 13 Aug 2025 04:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.44.83 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755059238; cv=fail; b=ZZE3c2r6K/f0qDnM8HQjjEgo16+p3JmXKtWOnewm+WN+bxCfFQnqW12CrXezQStDIybD1UeTz95bmBdmOD7Jp8Y4MVv6mUdGNIZS152SSFCCExG9w8BKh2pY7B9M3SPgvsC+KJwV/4Qnh3xDxWofii7P6T3odZgF+5QoYe+cOZE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755059238; c=relaxed/simple; bh=45LQUL5YuPbyD35oSShQwQZc+ZlYNOSRsd8Eapd5aiE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qcrAaBEYonU075P98+ocppNT56Gf/X5WLLjeO/a6RrSC44RscULO6dmDC2YNkJVOxEhQSb5eEGlftWUeXy/L85P4h3J/uhWrLk4HKXUBomu6K3zNZp1Q1M4B4jlafrDmN7+lf7SXD5Jo2NsUDzAIZBFMNW3hPCcGdYtWrM2gua0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.44.83 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=BzEm83mZvHdtlsq/sEmZIfz5wOb6Jz+R4XPtkAiZ4ZIlznxinrmUo4/pODTdPionBPke6d4TWdPh1mgJ6ZfUZC91raB0qtEHBcerT59tfeEUAXcdFPxbSFfPi864oacDMlxYD/JtgW88KZbtsAs02W+poK6X0D16UFwliwfkW7zsB4pZIN85D6L44BIxXIZrtHYicktGBD8jONiM/UQgP+6Ai/EnYGddVuGxci0pSG2otdJ3cXqJR1bt15llvzxXv7AYbdA3ML0jBPQFLVH5Gdw+IwNb8jxgpEv5SUpctKtsC4hcPukB3rUSht4adbKYIU0TKMlhzTb1f0VCvqmvWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=G1lhlew3XVDqFz347KZazD9OuPmP1EPoDWqzRj2kcXs=; b=Mrc69twmFWt9tZddqaRBVI47ATNCOJnHsJc8fmgbhRL3lGDqMHNz210frPGy0VRbjqcX6WVPDWtQKg2kR/tj61IlCIG/DM3QKc3XmFHKWEPpWTGI89v6eI7dkUcYUVNqaCoKx3Yk6aLLFx8iDFu4Cqmx2apW+b/v4ukALPicepEIEWGkWCsbP0uU12WYU0IPvnRXFaeJd/remCj5z6Hgn68gxrg13NVvXLh6WTIERQOhXGNSkwnBqdMYv/uFkZJKRc2dnxTZrbk1+dX+F7f0a9F6QpdANVjH6J8e/iNpuuIU1rFbqCf/YxBCihR+gv6KZ/OThwsdbpT6UX3pQKZ2CA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SG2PR02CA0027.apcprd02.prod.outlook.com (2603:1096:3:18::15) by TYSPR06MB6390.apcprd06.prod.outlook.com (2603:1096:400:433::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9031.15; Wed, 13 Aug 2025 04:27:11 +0000 Received: from SG2PEPF000B66CB.apcprd03.prod.outlook.com (2603:1096:3:18:cafe::f5) by SG2PR02CA0027.outlook.office365.com (2603:1096:3:18::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9031.15 via Frontend Transport; Wed, 13 Aug 2025 04:27:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CB.mail.protection.outlook.com (10.167.240.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9031.11 via Frontend Transport; Wed, 13 Aug 2025 04:27:08 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id CDE4B41604E7; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 10/13] PCI: sky1: Add PCIe host support for CIX Sky1 Date: Wed, 13 Aug 2025 12:23:28 +0800 Message-ID: <20250813042331.1258272-11-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CB:EE_|TYSPR06MB6390:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d1efb34-428a-445f-4092-08ddda21aad3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WLl8LfvOqMvL460nudYfFzr1xIn1DGKi9Rb1ECzhIjsmU4AdeMw6Drqxq6XY?= =?us-ascii?Q?HYCYUy1tff49dgD5ZPJWwdJ0m3M69lOePyl9wFTpeDe9Ffo01323vedvu+FO?= =?us-ascii?Q?eGXy7As+9CXwOiRwjtI/te69GDEU1jR+BukvZy0KbcCbwIMY9ie8EzrDXXxd?= =?us-ascii?Q?Ltb8kpcdSwqHVZB5wj77Ol+xwP1tMkALbwU9s4eE7hv6KQMfl0zZ+TuPzoJS?= =?us-ascii?Q?kY6T9nQNBnvMdd8Qu+DEtaLDFA78SvM7Ke87rVR5aQg/86TLkq/mafLxBoQt?= =?us-ascii?Q?YjEKTbUngMup1HIk+edo+AaGcRWc1WEsJR5Kt0UsCU0jdkW5mTnh4te7ZEGz?= =?us-ascii?Q?Ypr7ronUgI4NMPWxF6/DvHXg18zfBBLuFvh6iil10oE+rOI7ncTjJe+RRYc8?= =?us-ascii?Q?nrm5qgfFqAB02PgMpqFOrq4qWqDKdaPIBDCmUaVUHR2PMWdT9z5jmyh5DXyS?= =?us-ascii?Q?DO/3BW2imDWv0AkvebYvb9qyHMKV0N2eLID2Tl/rxbRnpSLZM1+OBCsXU6F9?= =?us-ascii?Q?ESK1F8qnDFHClPYBBg3y4hr6adnrurYd3Z7EUddbqTikSaG/QtSP7Z9wQ3Me?= =?us-ascii?Q?n3Muu3216dcq00HcgqzUwH0e/A+8FKvr0LbKEfTBNbrLTT1Dt1vktOLxLI72?= =?us-ascii?Q?buRzZcFoLSHP6ud4Kvub7izTny0bv+WwlDq3pYoAy4Qy6TIW+bi9/5w/eoBq?= =?us-ascii?Q?3DY2f3C86q8aSaeccV0EgwtABaMzJPiZEOJCC1cAp06xxaBe7qnCv5mLvC+L?= =?us-ascii?Q?YLRXkSYw0JXfbmpGWezpF8Q+QApHvIiViHx9y69O6BARlQBaHPLYMVNFiLBO?= =?us-ascii?Q?N4xs7CPL/HDqBq02Sasv/witdNNw3YxS92FUXhuA4jRUgdYfw4q5YtYQyzMw?= =?us-ascii?Q?rzdmnzUkG+KiqOGBgeBZZeiJyStDZLB/+Ul72Yk3Kf2Yd1BYrs2/s8nTsurl?= =?us-ascii?Q?oG2DIGDYcsJPp0ntCjyFrqAH7FvOqCJJp2XuZHccz8Lx3NqEdpJIprGbSTnE?= =?us-ascii?Q?9fFr8P/LLQuBjLNpoxmoggsqumjHSW+WNE3r1k0L0l2lHSI1iLV8B6oVUtyl?= =?us-ascii?Q?UPGteHbiFdorLQFp4zp4nr90YeLKVassQTxspWvDyrQlXDGcmWBlo3S+s6M2?= =?us-ascii?Q?VfEvz6U6ij4Er15EptgHn1qFDu6gcCHEoPDaElZ4nAE32oVQxkWKrg0adI1o?= =?us-ascii?Q?sbjZT7PCFtxGWaY6s36UQll7GVUPkOJ1y5f3CeRETcy0EdHqH6hOnjxeLtaU?= =?us-ascii?Q?wQF5iUlDw0eGcBoulMvc0yRv7KntJPur0JyT+M3xO3EuBVq/Hi9eGBT2azQz?= =?us-ascii?Q?xqotXO0bUJU4RYnZgupuHO8Xztu4LGZw6ti4RTndhTY60Sfz85tW771Xxvja?= =?us-ascii?Q?H3Xh2RegFeJWGv9WTE08X7UubxDy35R/uLkuQLO5V67+s3M3ydm7cdpUck7f?= =?us-ascii?Q?BQWh+vcJvKIYNBtoGr5t075KDE7YIsI3nIrRMcRNWZswyCiMe/pWCRN8e7s0?= =?us-ascii?Q?XtPAnqNs1YwXlIodUIs6/VJYALfyyspBCa/7?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:08.8950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d1efb34-428a-445f-4092-08ddda21aad3 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CB.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6390 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based on the Cadence PCIe core. Supports MSI/MSI-x via GICv3, Single Virtual Channel, Single Function. Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 13 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-sky1.c | 294 ++++++++++++++++++++++ 3 files changed, 308 insertions(+) create mode 100644 drivers/pci/controller/cadence/pci-sky1.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 117677a23d68..1716b7300fa1 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -67,4 +67,17 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. + +config PCI_SKY1_HOST + tristate "CIX SKY1 PCIe controller (host mode)" + depends on OF + select PCIE_CADENCE_HOST + select PCI_ECAM + help + Say Y here if you want to support the CIX SKY1 PCIe platform + controller in host mode. CIX SKY1 PCIe controller uses Cadence HPA(High + Performance Architecture IP[Second generation of cadence PCIe IP]) + + This driver requires Cadence PCIe core infrastructure (PCIE_CADENCE_HOS= T) + and hardware platform adaptation layer to function. endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index de4ddae7aca4..40d7c6e98b4d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-mod.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-mod.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o +obj-$(CONFIG_PCI_SKY1_HOST) +=3D pci-sky1.o diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/contro= ller/cadence/pci-sky1.c new file mode 100644 index 000000000000..36267d0bb5b6 --- /dev/null +++ b/drivers/pci/controller/cadence/pci-sky1.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe controller driver for CIX's sky1 SoCs + * + * Author: Hans Zhang + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define STRAP_REG(n) ((n) * 0x04) +#define STATUS_REG(n) ((n) * 0x04) + +#define RCSU_STRAP_REG 0x300 +#define RCSU_STATUS_REG 0x400 + +#define SKY1_IP_REG_BANK_OFFSET 0x1000 +#define SKY1_IP_CFG_CTRL_REG_BANK_OFFSET 0x4c00 +#define SKY1_IP_AXI_MASTER_COMMON_OFFSET 0xf000 +#define SKY1_AXI_SLAVE_OFFSET 0x9000 +#define SKY1_AXI_MASTER_OFFSET 0xb000 +#define SKY1_AXI_HLS_REGISTERS_OFFSET 0xc000 +#define SKY1_AXI_RAS_REGISTERS_OFFSET 0xe000 +#define SKY1_DTI_REGISTERS_OFFSET 0xd000 + +#define IP_REG_I_DBG_STS_0 0x420 + +#define LINK_TRAINING_ENABLE BIT(0) +#define LINK_COMPLETE BIT(0) + +enum cix_soc_type { + CIX_SKY1, +}; + +struct sky1_pcie_data { + struct cdns_plat_pcie_of_data reg_off; + enum cix_soc_type soc_type; +}; + +struct sky1_pcie { + struct device *dev; + const struct sky1_pcie_data *data; + struct cdns_pcie *cdns_pcie; + struct cdns_pcie_rc *cdns_pcie_rc; + + struct resource *cfg_res; + struct resource *msg_res; + struct pci_config_window *cfg; + void __iomem *rcsu_base; + void __iomem *strap_base; + void __iomem *status_base; + void __iomem *reg_base; + void __iomem *cfg_base; + void __iomem *msg_base; +}; + +static void sky1_pcie_clear_and_set_dword(void __iomem *addr, u32 clear, + u32 set) +{ + u32 val; + + val =3D readl(addr); + val &=3D ~clear; + val |=3D set; + writel(val, addr); +} + +static void sky1_pcie_init_bases(struct sky1_pcie *pcie) +{ + pcie->strap_base =3D pcie->rcsu_base + RCSU_STRAP_REG; + pcie->status_base =3D pcie->rcsu_base + RCSU_STATUS_REG; +} + +static int sky1_pcie_parse_mem(struct sky1_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct resource *res; + void __iomem *base; + int ret =3D 0; + + base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(base)) { + dev_err(dev, "Parse \"reg\" resource err\n"); + return PTR_ERR(base); + } + pcie->reg_base =3D base; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + if (!res) { + dev_err(dev, "Parse \"cfg\" resource err\n"); + return -ENXIO; + } + pcie->cfg_res =3D res; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "rcsu"); + if (!res) { + dev_err(dev, "Parse \"rcsu\" resource err\n"); + return -ENXIO; + } + pcie->rcsu_base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!pcie->rcsu_base) { + dev_err(dev, "ioremap failed for resource %pR\n", res); + return -ENOMEM; + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg"); + if (!res) { + dev_err(dev, "Parse \"msg\" resource err\n"); + return -ENXIO; + } + pcie->msg_res =3D res; + pcie->msg_base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!pcie->msg_base) { + dev_err(dev, "ioremap failed for resource %pR\n", res); + return -ENOMEM; + } + + return ret; +} + +static int sky1_pcie_parse_property(struct platform_device *pdev, + struct sky1_pcie *pcie) +{ + int ret =3D 0; + + ret =3D sky1_pcie_parse_mem(pcie); + if (ret < 0) + return ret; + + sky1_pcie_init_bases(pcie); + + return ret; +} + +static int sky1_pcie_start_link(struct cdns_pcie *cdns_pcie) +{ + struct sky1_pcie *pcie =3D dev_get_drvdata(cdns_pcie->dev); + + sky1_pcie_clear_and_set_dword(pcie->strap_base + STRAP_REG(1), + 0, LINK_TRAINING_ENABLE); + + return 0; +} + +static void sky1_pcie_stop_link(struct cdns_pcie *cdns_pcie) +{ + struct sky1_pcie *pcie =3D dev_get_drvdata(cdns_pcie->dev); + + sky1_pcie_clear_and_set_dword(pcie->strap_base + STRAP_REG(1), + LINK_TRAINING_ENABLE, 0); +} + + +static bool sky1_pcie_link_up(struct cdns_pcie *cdns_pcie) +{ + u32 val; + + val =3D cdns_pcie_hpa_readl(cdns_pcie, REG_BANK_IP_REG, + IP_REG_I_DBG_STS_0); + return val & LINK_COMPLETE; +} + +static const struct cdns_pcie_ops sky1_pcie_ops =3D { + .start_link =3D sky1_pcie_start_link, + .stop_link =3D sky1_pcie_stop_link, + .link_up =3D sky1_pcie_link_up, +}; + +static int sky1_pcie_probe(struct platform_device *pdev) +{ + const struct sky1_pcie_data *data; + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct cdns_pcie *cdns_pcie; + struct resource_entry *bus; + struct cdns_pcie_rc *rc; + struct sky1_pcie *pcie; + int ret; + + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + pcie->data =3D data; + pcie->dev =3D dev; + dev_set_drvdata(dev, pcie); + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) + return -ENOMEM; + + bus =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + ret =3D sky1_pcie_parse_property(pdev, pcie); + if (ret < 0) + return -ENXIO; + + pcie->cfg =3D pci_ecam_create(dev, pcie->cfg_res, bus->res, + &pci_generic_ecam_ops); + if (IS_ERR(pcie->cfg)) + return PTR_ERR(pcie->cfg); + + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + rc =3D pci_host_bridge_priv(bridge); + rc->ecam_support_flag =3D 1; + rc->cfg_base =3D pcie->cfg->win; + rc->cfg_res =3D &pcie->cfg->res; + + cdns_pcie =3D &rc->pcie; + cdns_pcie->dev =3D dev; + cdns_pcie->ops =3D &sky1_pcie_ops; + cdns_pcie->reg_base =3D pcie->reg_base; + cdns_pcie->msg_res =3D pcie->msg_res; + cdns_pcie->cdns_pcie_reg_offsets =3D &data->reg_off; + cdns_pcie->is_rc =3D data->reg_off.is_rc; + + pcie->cdns_pcie =3D cdns_pcie; + pcie->cdns_pcie_rc =3D rc; + pcie->cfg_base =3D rc->cfg_base; + bridge->sysdata =3D pcie->cfg; + + if (data->soc_type =3D=3D CIX_SKY1) { + rc->vendor_id =3D PCI_VENDOR_ID_CIX; + rc->device_id =3D PCI_DEVICE_ID_CIX_SKY1; + rc->no_inbound_flag =3D 1; + } + + ret =3D cdns_pcie_hpa_host_setup(rc); + if (ret < 0) { + pci_ecam_free(pcie->cfg); + return ret; + } + + return 0; +} + +static const struct sky1_pcie_data sky1_pcie_rc_data =3D { + .reg_off =3D { + .is_rc =3D true, + .ip_reg_bank_offset =3D SKY1_IP_REG_BANK_OFFSET, + .ip_cfg_ctrl_reg_offset =3D SKY1_IP_CFG_CTRL_REG_BANK_OFFSET, + .axi_mstr_common_offset =3D SKY1_IP_AXI_MASTER_COMMON_OFFSET, + .axi_slave_offset =3D SKY1_AXI_SLAVE_OFFSET, + .axi_master_offset =3D SKY1_AXI_MASTER_OFFSET, + .axi_hls_offset =3D SKY1_AXI_HLS_REGISTERS_OFFSET, + .axi_ras_offset =3D SKY1_AXI_RAS_REGISTERS_OFFSET, + .axi_dti_offset =3D SKY1_DTI_REGISTERS_OFFSET, + }, + .soc_type =3D CIX_SKY1, +}; + +static const struct of_device_id of_sky1_pcie_match[] =3D { + { + .compatible =3D "cix,sky1-pcie-host", + .data =3D &sky1_pcie_rc_data, + }, + {}, +}; + +static void sky1_pcie_remove(struct platform_device *pdev) +{ + struct sky1_pcie *pcie =3D platform_get_drvdata(pdev); + + pci_ecam_free(pcie->cfg); +} + +static struct platform_driver sky1_pcie_driver =3D { + .probe =3D sky1_pcie_probe, + .remove =3D sky1_pcie_remove, + .driver =3D { + .name =3D "sky1-pcie", + .of_match_table =3D of_sky1_pcie_match, + }, +}; +module_platform_driver(sky1_pcie_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("PCIe controller driver for CIX's sky1 SoCs"); +MODULE_AUTHOR("Hans Zhang "); --=20 2.49.0 From nobody Sat Oct 4 21:00:50 2025 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023072.outbound.protection.outlook.com [52.101.127.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4956429E0FB; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id D2B6A41604E9; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 11/13] MAINTAINERS: add entry for CIX Sky1 PCIe driver Date: Wed, 13 Aug 2025 12:23:29 +0800 Message-ID: <20250813042331.1258272-12-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C9:EE_|TY0PR06MB5834:EE_ X-MS-Office365-Filtering-Correlation-Id: 8eb77a9f-6166-4ca0-b239-08ddda21ab39 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:09.5648 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8eb77a9f-6166-4ca0-b239-08ddda21ab39 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C9.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY0PR06MB5834 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add myself as maintainer of Sky1 PCIe host driver Signed-off-by: Hans Zhang --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..d84062b632c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19253,6 +19253,13 @@ S: Orphan F: Documentation/devicetree/bindings/pci/cdns,* F: drivers/pci/controller/cadence/*cadence* =20 +PCI DRIVER FOR CIX Sky1 +M: Hans Zhang +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/cix,sky1-pcie-*.yaml +F: drivers/pci/controller/cadence/*sky1* + PCI DRIVER FOR FREESCALE LAYERSCAPE M: Minghuan Lian M: Mingkai Hu --=20 2.49.0 From nobody Sat Oct 4 21:00:50 2025 Received: from TYPPR03CU001.outbound.protection.outlook.com (mail-japaneastazon11022122.outbound.protection.outlook.com [52.101.126.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 245202BE039; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id DA06D41604EA; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 12/13] arm64: dts: cix: Add PCIe Root Complex on sky1 Date: Wed, 13 Aug 2025 12:23:30 +0800 Message-ID: <20250813042331.1258272-13-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB89:EE_|TY0PR06MB6802:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d199262-607c-4725-54ee-08ddda21ab31 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?qz3C4m5ctAlqEgG9qpvIm2v3XehBY2DCnxuoXwHZlxAQEXunJIuVtqJ04ySb?= =?us-ascii?Q?7X342gLg5iDOP+mdzbDDHJpJmjBRWrGVV7khUrZDBlLB4L3KZvQePk91bhoX?= =?us-ascii?Q?/8i9YaCz78/bsNF+lb9MVnQzNG4ZOd6rUyeEttHzbesIZVN7M/gieaqHn6Yc?= =?us-ascii?Q?TXxyNfmcDahFInwDlFHkvYM4Y6L+Oc3HvrMkn1H6ziG6CEXmgzOxLTnLrUZx?= =?us-ascii?Q?oRVgQDxLe1YXPZ6HYq+jMj03KlH0Vt9mp3fCGdyg5TEfBzpSIgJ/15tLLPnV?= =?us-ascii?Q?mtr4RR4TkUeb70U2dL1SGEm3ObGVSf3dN4kv2W2PtO72hbB0ApRpoALRA8c+?= =?us-ascii?Q?n1eBmcIMecwV631kEf8QOCY/ex9rx0gP8TxQ3J3LpZRuE6zm/MIR2KuZDzB6?= =?us-ascii?Q?v8YrfAqRZvm+cCb72HWUIplmWviQ3cnXKqglvQpBpN9etzmZoJgqYAJx8+Zl?= =?us-ascii?Q?UFlfCwdPNL6XpO2IbTJDEmenjq3ox6yJlYMltPm7JU4czmaTXdOO8iREuRcN?= =?us-ascii?Q?lgNuVLeVbYheuocNLR/Yb/+jSvNQz9/VAiDPH5+aUXoBqjtatw93hf104/Cz?= =?us-ascii?Q?7gnKopsmdl6zOJq86myJkdS1Aq5fbVPPnZ6r190+OvrpOmFyQPDMDvHGCXgF?= =?us-ascii?Q?aEGvK0Fne6/Z77ZAsIevxcUcdwQH0aDHgJpUAh7celWBelcVyZWXhAnYVLlL?= =?us-ascii?Q?lxubnRXj/ffLnpkJeRngCJJquQnctYI4tDgoMr14Y8p7hirpNYqc9Ypac874?= =?us-ascii?Q?KpRR6M5BHyTPhbq3KQPqkaUeUQL2RYKbzm+dZWKqdM3KOtYNK4jR6g9BaKnM?= =?us-ascii?Q?hT7Ldc/2Z+vFbnrtCtI1i0XSQAYnXfQF452WdInGCgtSwrn6wvQ9m+fnh7Ug?= =?us-ascii?Q?pkr4zLo1fUYxIeoCEmZaH6L+xzlJ5cimQ+BQsgN5eStIS+f7R+i9ugX4PW7Y?= =?us-ascii?Q?IwltmpHCra5MPaZT2stFGKSS5nllZmQk/xWjn+Tanba1aaRkeWEc2EvG3fEE?= =?us-ascii?Q?JYhz4MOk9nBAgUXHMy8W5yZwRnxVN6nfqvP8jPruaWU2GVkzrCenItRyOn3G?= =?us-ascii?Q?Fn4ckzwwsgHvsnPgnYOwxnymPpb1AVks93XB3zj5djgSNC2+5vlhF5K7PFC0?= =?us-ascii?Q?KchCLea78qG+n0zRXOkXGToAwwX7wxVF+UudrSBLuNSDK1wgW45JgxtiuOs1?= =?us-ascii?Q?zy7Pq5lcaM0gGbgP3aSS5AxcwtUZC5NurOpxdmdRHjx0auaYo9TggDswA9bW?= =?us-ascii?Q?UDd46AD4QtAHnSGaRkvRQpCCtozm64i+SjlZ3vkacOHfSPuhjwGFcKVEMboh?= =?us-ascii?Q?8n9+iSs8GNoGPCdwilBM043+U7XR+jzw9tGYd48XCYw9H+KFZIZm6BtAtD9x?= =?us-ascii?Q?QJS3N5WTyE1FINfWtggmkTCZQ5i7vfvfk7kSfV/TalcGArDP/X6t5cczAwNC?= =?us-ascii?Q?i/L8vLYO3U6EClZ7bFC2VTlxsZEF5doQ+XqrJ9NBcYMEfn9AtiX8qOQ/KPVp?= =?us-ascii?Q?P2Ki+FkUs7sj/s2e5NfhEJMMHkpjYd+hEhsB?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:09.5301 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d199262-607c-4725-54ee-08ddda21ab31 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB89.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY0PR06MB6802 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core. Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using the ARM GICv3. Signed-off-by: Hans Zhang --- arch/arm64/boot/dts/cix/sky1.dtsi | 121 ++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 7dfe7677e649..04ba80d4fc06 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -288,6 +288,127 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir =3D "tx"; }; =20 + pcie_x8_rc: pcie@a010000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000000 0x00 0x10000>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; + status =3D "disabled"; + }; + + pcie_x4_rc: pcie@a070000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a070000 0x00 0x10000>, + <0x00 0x29000000 0x00 0x3000000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x50000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x90 0xbf>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x9000 &gic_its 0x9000 0x3000>; + status =3D "disabled"; + }; + + pcie_x2_rc: pcie@a0c0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0c0000 0x00 0x10000>, + <0x00 0x26000000 0x00 0x3000000>, + <0x00 0x0a060040 0x00 0x10000>, + <0x00 0x40000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x60 0x8f>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x6000 &gic_its 0x6000 0x3000>; + status =3D "disabled"; + }; + + pcie_x1_0_rc: pcie@a0d0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0d0000 0x00 0x10000>, + <0x00 0x20000000 0x00 0x3000000>, + <0x00 0x0a060060 0x00 0x10000>, + <0x00 0x30000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x00 0x2f>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x0000 &gic_its 0x0000 0x3000>; + status =3D "disabled"; + }; + + pcie_x1_1_rc: pcie@a0e0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0e0000 0x00 0x10000>, + <0x00 0x23000000 0x00 0x3000000>, + <0x00 0x0a060080 0x00 0x10000>, + <0x00 0x38000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, + <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, + <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x30 0x5f>; + device_type =3D "pci"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x3000 &gic_its 0x3000 0x3000>; + status =3D "disabled"; + }; + gic: interrupt-controller@e010000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x0e010000 0 0x10000>, /* GICD */ --=20 2.49.0 From nobody Sat Oct 4 21:00:50 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023104.outbound.protection.outlook.com [40.107.44.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD2FE2BE640; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id DCF2141604EB; Wed, 13 Aug 2025 12:27:04 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v7 13/13] arm64: dts: cix: Enable PCIe on the Orion O6 board Date: Wed, 13 Aug 2025 12:23:31 +0800 Message-ID: <20250813042331.1258272-14-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250813042331.1258272-1-hans.zhang@cixtech.com> References: <20250813042331.1258272-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E2:EE_|SE1PPF215029121:EE_ X-MS-Office365-Filtering-Correlation-Id: 86611f47-5c25-4e9c-9d0a-08ddda21ab43 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?lp5/uYNXUVBL/t3kxlwocgEV8le8xyHlkWKITu89j+s+rKkDhGm49VtkVLu1?= =?us-ascii?Q?SpjXmeYm+O3ODieELwSmS+66BQJgSZOJUr9wtBR1rk6UwbHwRd8np3dLoZnn?= =?us-ascii?Q?Vq6aqlYvQqMsmRh5dOGhIaa91zWqLz81zip9nHm5COg/w9xVYHrb1P1xhXhx?= =?us-ascii?Q?p6oGpzBaAY6EliW00tU4fxFvGJGEwP+p/i7oWc3x+BKYCJO1wP+8Ue2VCybx?= =?us-ascii?Q?hDJtaEYNGjS3Ue2x1mNKP3WdFv+rAwe1aFbmeOWN7VYIOS30fMLdst6h+4zt?= =?us-ascii?Q?2KL7CLeQ4iZ0WrVAWLPcpN9Q8EpbQBYFNObbnECJ6qb9gBr2da+e0VcXHHRV?= =?us-ascii?Q?vpx5Z/LsaG3E31qsZTx+85+PXk/UDeEBJZ/Aa09VbUiTxbJBL8oXFnt5CfFr?= =?us-ascii?Q?aKwkKCl4h9tWIEwCwA0Ljsa5r2kFNhAO9TKIoKmIQklQ/DWLe6WxzgW2K4fY?= =?us-ascii?Q?gpn2VrDo5eX0b5+9HUjdGwUQBRYd949Ig6f50tRreFTT0G3Qzz7C2PjvyHDJ?= =?us-ascii?Q?UVDkYXUPGdAvGujTmF3fiDBt877LBTt2pfW/kHgAdlNJGbNquqdJ/Q1AknF9?= =?us-ascii?Q?Cdo+cIFE9LimHKwTLxePSUSiw8pBjI46fQABbgb05oZQn7Bm1ecGYaGbELfc?= =?us-ascii?Q?UjAKA1xPbEi8KVS5cMWVd+4s5iLENsYc74iPK5nE32PtUR6h8Ls9BQgBQzAR?= =?us-ascii?Q?P+HCTVALCIesys1iY3Z224/I6ZRx+2DSbLLhI/QcROOrDxIBXH9WfeFNUypw?= =?us-ascii?Q?0tWG1sYAhwvbcldI//77A5eWG5OWxa2oVkKrsGUmJV4tsRnxVm0jGXdRcMHa?= =?us-ascii?Q?3vtlVRMCAV3KWbXUE4T0HpHT7T2toP6D0pfzASUEU58PYZYqgSbo4CJLX9CU?= =?us-ascii?Q?SM6g5Q5B8o/90spi7v60rBntzQjEwDRj3nH/f1aaaEbzFAPvshOeGrVYUqGG?= =?us-ascii?Q?SWNPLnc0RMd0PSjsyAhr1IMO1u3VuJufqG80BmqkJURGPjScSUOaFRy04gMv?= =?us-ascii?Q?rKV3igaHChuXnI/Ip+S3/3a4wv9WcbvvMm5R4LTHz+YHFf8Pc754u1rGrKDb?= =?us-ascii?Q?ua1A5IxD9z6Rgsx9b2K4JT1pG/hD5pfg4iU/t9ZgJzPKKXocQKhS8aWR7MCy?= =?us-ascii?Q?pDIgszyAOUMRtZQdjgV+uI7ihq0kv2lycWQo8mEDPrlv2jISSeLyjfQMAsqN?= =?us-ascii?Q?XL2I//6GLjzxOb6zuB8cVbYY3PtZqrLKT9ekJLvGimJjC2F4UcDbYq35NtQn?= =?us-ascii?Q?yVDr2cRDc+M4ikhHcz/2U4rr99H2Oa39OgZd7WTb8wBJDvkwSlRcXp4LCVgN?= =?us-ascii?Q?Xmm3YHERef5RW4h/cVgn7Eyi4SIki8MBA9Fu3g0ogbN+lvB0GbOLZJXzd+IQ?= =?us-ascii?Q?w0llogHw+ppAFIxNEOzawRnG//20BdTKa/EOfoosIvB4JDPQTwD+cexk7xyt?= =?us-ascii?Q?oPMCpC+USx1LGZBm3cSeAD53kkV50gGEogjP6OZnwDMVGNgjvsHSFIcJEzkS?= =?us-ascii?Q?9c7SQsrQJmq2JAA0VQSMo920++Hes8c1HnEd?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2025 04:27:09.6742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86611f47-5c25-4e9c-9d0a-08ddda21ab43 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E2.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE1PPF215029121 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add PCIe RC support on Orion O6 board. Signed-off-by: Hans Zhang --- Dear Krzysztof, Due to the fact that the GPIO, PINCTRL and other modules of our platform are not yet ready for upstream. Attributes that PCIe depends on, such as reset-= gpios and pinctrl*, have not been added for the time being. It will be added grad= ually in the future. The following are Arnd's previous comments. We can go to upsteam separately. https://lore.kernel.org/all/422deb4d-db29-48c1-b0c9-7915951df500@app.fastma= il.com/ --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dt= s/cix/sky1-orion-o6.dts index d74964d53c3b..be3ec4f5d11e 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -34,6 +34,26 @@ linux,cma { =20 }; =20 +&pcie_x8_rc { + status =3D "okay"; +}; + +&pcie_x4_rc { + status =3D "okay"; +}; + +&pcie_x2_rc { + status =3D "okay"; +}; + +&pcie_x1_0_rc { + status =3D "okay"; +}; + +&pcie_x1_1_rc { + status =3D "okay"; +}; + &uart2 { status =3D "okay"; }; --=20 2.49.0