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Wed, 13 Aug 2025 07:53:46 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57D7rjCg002007 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Aug 2025 07:53:45 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 13 Aug 2025 00:53:42 -0700 From: Dikshita Agarwal Date: Wed, 13 Aug 2025 13:23:25 +0530 Subject: [PATCH v2] media: iris: vpu3x: Add MNoC low power handshake during hardware power-off Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250813-sm8650-power-sequence-fix-v2-1-9ed0fc2c45cb@quicinc.com> X-B4-Tracking: v=1; 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Introduce a handshake loop to ensure MNoC enters low power mode reliably during VPU3 hardware power-off with timeout handling. Signed-off-by: Dikshita Agarwal Tested-by: Neil Armstrong # on SM8650-HDK Tested-by: Neil Armstrong # on SM8650-QRD --- Changes in v2: - Restructured loop for readability (Jorge) - Used defines for bits (Konrad, Jorge) - Used udelay for short waits (Konrad) - Link to v1: https://lore.kernel.org/r/20250812-sm8650-power-sequence-fix-= v1-1-a51e7f99c56c@quicinc.com Please note that I have not added "Tested-by" tag from Neil in this update, as the NOC handshake loop has been restructured. --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 30 +++++++++++++++++++++++= ++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 9b7c9a1495ee2f51c60b1142b2ed4680ff798f0a..a621878f02f7196de29c9e290a6= c5acea34eba8c 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -19,6 +19,9 @@ #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) #define REQ_POWER_DOWN_PREP BIT(0) #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is com= plete */ +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is den= ied */ +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) #define CORE_CLK_RUN 0x0 =20 @@ -109,7 +112,9 @@ static void iris_vpu3_power_off_hardware(struct iris_co= re *core) =20 static void iris_vpu33_power_off_hardware(struct iris_core *core) { + bool handshake_done =3D false, handshake_busy =3D false; u32 reg_val =3D 0, value, i; + u32 count =3D 0; int ret; =20 if (iris_vpu3x_hw_power_collapsed(core)) @@ -128,13 +133,34 @@ static void iris_vpu33_power_off_hardware(struct iris= _core *core) goto disable_power; } =20 + /* set MNoC to low power */ + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONT= ROL); + + do { + value =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); + + handshake_done =3D value & NOC_LPI_STATUS_DONE; + handshake_busy =3D value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + udelay(15); + + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CON= TROL); + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + dev_err(core->dev, "LPI handshake timeout\n"); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, reg_val, reg_val & BIT(0), 200, 2000); if (ret) goto disable_power; =20 - /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ - writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); =20 writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); --- base-commit: d968e50b5c26642754492dea23cbd3592bde62d8 change-id: 20250812-sm8650-power-sequence-fix-ba9a92098233 Best regards, --=20 Dikshita Agarwal