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Wed, 13 Aug 2025 00:56:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHgKQmjdlT8hx0GkhErVH+MkRlpaJID1vtl2bTLhbL/jf7nb5EbDTpqOzaW/6jMYUTl2/rtmA== X-Received: by 2002:a05:6a00:1492:b0:76b:d93a:69e2 with SMTP id d2e1a72fcca58-76e20f818acmr3372599b3a.19.1755071772697; Wed, 13 Aug 2025 00:56:12 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfbd22csm31395754b3a.65.2025.08.13.00.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Aug 2025 00:56:12 -0700 (PDT) From: Taniya Das Date: Wed, 13 Aug 2025 13:25:20 +0530 Subject: [PATCH v4 4/7] clk: qcom: rpmh: Add support for Glymur rpmh clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250813-glymur-clock-controller-v4-v4-4-a408b390b22c@oss.qualcomm.com> References: <20250813-glymur-clock-controller-v4-v4-0-a408b390b22c@oss.qualcomm.com> In-Reply-To: <20250813-glymur-clock-controller-v4-v4-0-a408b390b22c@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=G6EcE8k5 c=1 sm=1 tr=0 ts=689c451e cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=RRvC4NyyfoRIYhV0TvUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA5NyBTYWx0ZWRfX/xabFEY+meCC Sku/Lt5vE+Tawaz94cgEM8SZ0c+GCWciq6UYnlTKQyJdRUgHankAqrc/NXuTbrm5lIEEvATFHdx RmWoPVVaIc7trvA59VciF0FfuLAhDw5km/9+iIw5N9/VDQmHW1NjotSHPPOzyRhd9S/EIo8kgdd MsDEAlTvsz7tnp740Iigp2NEjafH5Cr6DreUyJ9rJDcUspc/jHrRIvY/0NiJDGfy0QG/Sjq785N Sikt0quSFlAjBhyL+bnsbpqiveeYrgUVCvp67s2O/ka3lWUUziPdn+J7icve+OVIvTcFQrKucdt cBGEriZdfRk6RMTj+oODTb90qJKA00UUQPzZ6e4iKuSQ36hgu6+imjumig81ITUKpFfn/X09ZnT PrEcbPVi X-Proofpoint-ORIG-GUID: VPzUCYv4j6JhQ0d5aabLsu99e8qvAP-Y X-Proofpoint-GUID: VPzUCYv4j6JhQ0d5aabLsu99e8qvAP-Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_08,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110097 Add RPMH clock support for the Glymur SoC to allow enable/disable of the clocks. Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-rpmh.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 1496fb3de4be8db0cae13e6358745660f286267a..d31b1ea963e3a54ecfa25e6c5cb= 0806e562525e4 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -390,6 +390,11 @@ DEFINE_CLK_RPMH_VRM(clk7, _a4, "clka7", 4); =20 DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); =20 +DEFINE_CLK_RPMH_VRM(clk3, _a, "C3A_E0", 1); +DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1); +DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1); +DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1); + DEFINE_CLK_RPMH_BCM(ce, "CE0"); DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); DEFINE_CLK_RPMH_BCM(ipa, "IP0"); @@ -879,6 +884,22 @@ static const struct clk_rpmh_desc clk_rpmh_sm8750 =3D { .clka_optional =3D true, }; =20 +static struct clk_hw *glymur_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_RF_CLK3] =3D &clk_rpmh_clk3_a.hw, + [RPMH_RF_CLK3_A] =3D &clk_rpmh_clk3_a_ao.hw, + [RPMH_RF_CLK4] =3D &clk_rpmh_clk4_a.hw, + [RPMH_RF_CLK4_A] =3D &clk_rpmh_clk4_a_ao.hw, + [RPMH_RF_CLK5] =3D &clk_rpmh_clk5_a.hw, + [RPMH_RF_CLK5_A] =3D &clk_rpmh_clk5_a_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_glymur =3D { + .clks =3D glymur_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(glymur_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -968,6 +989,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) } =20 static const struct of_device_id clk_rpmh_match_table[] =3D { + { .compatible =3D "qcom,glymur-rpmh-clk", .data =3D &clk_rpmh_glymur}, { .compatible =3D "qcom,milos-rpmh-clk", .data =3D &clk_rpmh_milos}, { .compatible =3D "qcom,qcs615-rpmh-clk", .data =3D &clk_rpmh_qcs615}, { .compatible =3D "qcom,qdu1000-rpmh-clk", .data =3D &clk_rpmh_qdu1000}, --=20 2.34.1