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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a16dde163sm297645e9.12.2025.08.12.13.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 13:03:49 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Prabhakar Subject: [PATCH 04/13] arm64: dts: renesas: r9a09g087: Add pinctrl node Date: Tue, 12 Aug 2025 21:03:35 +0100 Message-ID: <20250812200344.3253781-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250812200344.3253781-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250812200344.3253781-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add pinctrl node to RZ/N2H ("R9A09G087") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 7dcaee711486..3d243096b04c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ =20 +#define RZN2H_PINS_PER_PORT 8 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZN2H_PORT_PINMUX(b, p, f) ((b) * RZN2H_PINS_PER_PORT + (p) | = ((f) << 16)) + +/* Convert a port and pin label to its global pin index */ +#define RZN2H_GPIO(port, pin) ((port) * RZN2H_PINS_PER_PORT + (pin)) + #include #include =20 @@ -216,6 +227,19 @@ cpg: clock-controller@80280000 { #power-domain-cells =3D <0>; }; =20 + pinctrl: pinctrl@802c0000 { + compatible =3D "renesas,r9a09g087-pinctrl"; + reg =3D <0 0x802c0000 0 0x10000>, + <0 0x812c0000 0 0x10000>, + <0 0x802b0000 0 0x10000>; + reg-names =3D "nsr", "srs", "srn"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 280>; + power-domains =3D <&cpg>; + }; + gic: interrupt-controller@83000000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x83000000 0 0x40000>, --=20 2.50.1