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(unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1f211b6c8; Tue, 12 Aug 2025 20:31:23 +0800 (GMT+08:00) From: Albert Yang To: krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v3 1/8] dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd. Date: Tue, 12 Aug 2025 20:31:03 +0800 Message-ID: <20250812123110.2090460-2-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812123110.2090460-1-yangzh0906@thundersoft.com> References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a989e438b7209cckunm52c5de628442ec X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDTkhIVk9MGE1CTBhOHhpNSFYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=aXG6ZGLvgfa51rSTBlHiXg3xtd8dcVusATZ4pNvePrkUUSPb4nUavkAp1UfjzAAA9ubUQoFCl78X1otCU5YgBLROXuZzTtgcA3w3SFKwXVewCmlUMlQat6xquYEKG3uJEmjrx7LbD3pJaHlJDgkIrnm0mxY9vRgl74bHl0kcoyE=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=uMF9MVoCt3oNiVLaSeefyEyPgFYdHQbwhghyc6DPFLE=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Black Sesame Technologies Co., Ltd.s a leading automotive-grade computing SoC and SoC-based intelligent vehicle solution provider. Link: https://bst.ai/. Acked-by: Rob Herring (Arm) Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Changes for v3: - No changes Changes for v2: - No changes --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 5d2a7a8d3ac6..3c2031417232 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -222,6 +222,8 @@ patternProperties: description: Shenzhen BigTree Tech Co., LTD "^bitmain,.*": description: Bitmain Technologies + "^bst,.*": + description: Black Sesame Technologies Co., Ltd. "^blaize,.*": description: Blaize, Inc. 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(unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1f211b6cb; Tue, 12 Aug 2025 20:31:26 +0800 (GMT+08:00) From: Albert Yang To: krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v3 2/8] dt-bindings: arm: add Black Sesame Technologies (bst) SoC Date: Tue, 12 Aug 2025 20:31:04 +0800 Message-ID: <20250812123110.2090460-3-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812123110.2090460-1-yangzh0906@thundersoft.com> References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a989e43969c09cckunm52c5de62844321 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaGE0aVk9MGBhDTkhMGU0YT1YVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=lADkWNuXX4qQkO4/jkHrO3mxeTcnlnqRPL0FyIGU1cqO+5wB9P7IG9onma9SDIECZ/qc59RfQanmAcZgh0vfQoccZZ64vXjZInuhcxTxyqx2hTv9TvKX7yg9cu5Yuel68/l3JKXl7L2mF0BxdWHwFBbaaerAmU5Ptte3sPXQbDw=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=aJBsDwM35xGEHOWQiQCs6y3IgY32G8frXv2cxix0Nx0=; h=date:mime-version:subject:message-id:from; Add device tree bindings for Black Sesame Technologies Arm SoC, it consists several SoC models like C1200, etc. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang Reviewed-by: Krzysztof Kozlowski --- Changes for v3: - Add Signed-off-by: Ge Gordon Changes for v2: - Removed unnecessary pipe (`|`) in description - Dropped invalid=C2=A0`compatible`=C2=A0entry for standalone SoC - Removed root node (`$nodename: '/'`) definition --- .../devicetree/bindings/arm/bst.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bst.yaml diff --git a/Documentation/devicetree/bindings/arm/bst.yaml b/Documentation= /devicetree/bindings/arm/bst.yaml new file mode 100644 index 000000000000..a3a7f424fd57 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bst.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BST platforms + +description: + Black Sesame Technologies (BST) is a semiconductor company that produces + automotive-grade system-on-chips (SoCs) for intelligent driving, focusing + on computer vision and AI capabilities. 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(unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1f211b6ce; Tue, 12 Aug 2025 20:31:28 +0800 (GMT+08:00) From: Albert Yang To: krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v3 3/8] arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs Date: Tue, 12 Aug 2025 20:31:05 +0800 Message-ID: <20250812123110.2090460-4-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812123110.2090460-1-yangzh0906@thundersoft.com> References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a989e439eab09cckunm52c5de62844346 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDQx9PVktKQkpPQkoeHU1OTVYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=McbTzGke7qRrlKTuxiDsOwdTXAQmdvv0q9YnddOnQOYYWYa3bE00ayXsLDWMo8KiAkITrltpt46MfXAp+c8ZDqwjqoTy+KLv8ki/cuUpjtzCr922cl7deSFYHSmbfJoVJjXSZFDyvKnoXCrZpb+22NUmayt5HDfrmTQ1nvL0/tU=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=5azJ5qEoVzNoXa2DOglubsbylWr8QeDyzeiW7uUhUmU=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add ARCH_BST configuration option to enable support for Black Sesame Technologies SoC family. BST produces automotive-grade system-on-chips for intelligent driving, focusing on computer vision and AI capabilities. The BST C1200 family includes SoCs for ADAS and autonomous driving applications. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Changes for v3: - Reword subject from "for bst silicons" to "for Black Sesame Technologies SoCs" - drop unrelated whitespace hunk Changes for v2: - Placed the configuration entry in correct alphabetical order - Used generic family name (ARCH_BST) instead of SoC-specific naming - Followed upstream kernel naming and description conventions --- arch/arm64/Kconfig.platforms | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a541bb029aa4..b078b70ded0c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -106,6 +106,14 @@ config ARCH_BLAIZE help This enables support for the Blaize SoC family =20 +config ARCH_BST + bool "Black Sesame Technologies SoC Family" + help + This enables support for Black Sesame Technologies (BST) SoC family. + BST produces automotive-grade system-on-chips for intelligent driving, + focusing on computer vision and AI capabilities. The BST C1200 family + includes SoCs for ADAS and autonomous driving applications. + config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG --=20 2.43.0 From nobody Sat Oct 4 22:35:33 2025 Received: from mail-m49236.qiye.163.com (mail-m49236.qiye.163.com [45.254.49.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E806F7494; Tue, 12 Aug 2025 12:36:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.236 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755002206; cv=none; b=Ki0Fn+nhVvbSR/BLPp/yflgMmUmse1El3KQ0TXTy6Nk7ii7HmY9rH1R1NUyMjcgG1NOjlONMrV7bJryhItwY8NcHgvEKQciTjiteYyA+I0jxJB1cBvMW50cnRgeg+7MvZvMOvE6llcz/Q/3Ec0Yt8IK3KV+RR3KkO4VMxpNu2XI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755002206; c=relaxed/simple; bh=W0xpLXS4t7sIy92AyJg6Tcaom5x2x8cM3Z63JmAuOi4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=czsUcFT9ZH5GX7LN2C3ihflB2PCn8wt2jtISR8OcfNHP5sjdsUi+PIcomgQYLNunu69FFkHd30qz5lnG4zOqe/12dObVyoSPG2MPwv63AfF/rErdSEE4qadhu3asQZ3MEr21AGpF5O3XHf8lm4SGo+F/XipY/3y2jOY7HRHOhKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=ipb3Z4ar; arc=none smtp.client-ip=45.254.49.236 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="ipb3Z4ar" Received: from albert-OptiPlex-7080.. (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1f211b6d1; Tue, 12 Aug 2025 20:31:30 +0800 (GMT+08:00) From: Albert Yang To: krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v3 4/8] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Date: Tue, 12 Aug 2025 20:31:06 +0800 Message-ID: <20250812123110.2090460-5-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812123110.2090460-1-yangzh0906@thundersoft.com> References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a989e43a55a09cckunm52c5de62844361 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZGEgeVk5OSR4ZSEIZSUpKHVYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=ipb3Z4arhnKQUWgsF0SV/Ku9sNBABtr9l7gIr5DIQvM30KBARP5eZo9LkmQQixWbV63qMbl/KmEM6TSmxE4UcJNUUjohqnatIW3gnCFo+NzBYMYyeYZ0TcYXS5ycZ06Ng95gmad6+ZisOLyAjK0EwVwL8vAK4iDRsWyNVyt+U/I=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=0Ri6zMj/+h5ih+JWU6WL0UfhfS5rxCY0NiL6EaniZCg=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree binding documentation for the Black Sesame Technologies (BST) DWCMSHC SDHCI controller. This binding describes the required and optional properties for the bst,c1200-dwcmshc-sdhci compatible controller, including register layout, interrupts, bus width, clock configuration, and other controller-specific features. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Changes for v3: - Switch reg schema from maxItems to explicit items with per-entry descriptions - Improve example: add irq.h include and wrap under a bus node with address/size cells - Drop status =3D "disabled" from example; keep example concise - Add Signed-off-by: Ge Gordon Changes for v2: - Simplified description, removed redundant paragraphs - Updated $schema to reference mmc-specific scheme - Corrected compatible to add soc name (bst,c1200-dwcmshc-sdhci) - Removed all redundant property descriptions - Dropped invalid mmc_crm_base/size properties, use reg for all address ranges - Cleaned up required properties to only essential entries - Standardized example DTS format, fixed reg syntax and property ordering - Removed additionalProperties: true --- .../bindings/mmc/bst,dwcmshc-sdhci.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci= .yaml diff --git a/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml b= /Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml new file mode 100644 index 000000000000..aa72ce60259f --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/bst,dwcmshc-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Black Sesame Technologies DWCMSHC SDHCI Controller + +maintainers: + - Ge Gordon + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + const: bst,c1200-dwcmshc-sdhci + + reg: + items: + - description: Core SDHCI registers + - description: CRM registers + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + memory-region: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + mmc@22200000 { + compatible =3D "bst,c1200-dwcmshc-sdhci"; + reg =3D <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_mmc>; + clock-names =3D "core"; + memory-region =3D <&mmc0_reserved>; + max-frequency =3D <200000000>; + bus-width =3D <8>; + non-removable; + dma-coherent; + }; + }; --=20 2.43.0 From nobody Sat Oct 4 22:35:33 2025 Received: from mail-m49244.qiye.163.com (mail-m49244.qiye.163.com [45.254.49.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78B9D24679A; Tue, 12 Aug 2025 12:36:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.244 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755002215; cv=none; b=CVGwFZSo9BSmFSXp26x/fk1UDeHNVrDkzx4OoNqUAqKsCMtnE8UTPLLsD2UuVyVxoO2J6EPyCll7FPOgc7+Zuzw4VdQxseYMQx7iiZ6gArODrcWK8ZQCKR25Zu93xnKDAC42i/Qi7+6rAIRF/ZyPlrIrW2/whSGZX426y7fmjJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755002215; c=relaxed/simple; bh=f4F+eKmATLws29WFY+zObNocf6EolvlM87MPMD6t9yQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AFw8bVyGROmwfH6ZnIUdBUuo4/xGLhGtPi06ucBCpxbDtRyS7eQBORiqRo2lq2tIxpToh9mQRgLdtwgFQItsGxIyOCf+gCCK8m6VgeO60aWL7OiwR3DnzF1ESZwlLSY6h88CUcElfWDMR7l10+C+02oiezpCIEn6dTxtMDOO4+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=YFWiz8kt; arc=none smtp.client-ip=45.254.49.244 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="YFWiz8kt" Received: from albert-OptiPlex-7080.. (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1f211b6d3; Tue, 12 Aug 2025 20:31:32 +0800 (GMT+08:00) From: Albert Yang To: krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v3 5/8] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver Date: Tue, 12 Aug 2025 20:31:07 +0800 Message-ID: <20250812123110.2090460-6-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812123110.2090460-1-yangzh0906@thundersoft.com> References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a989e43aef409cckunm52c5de62844382 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZSkgfVk1KQkpCSUkfGk1LS1YVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpPTUxOT0xVSk tLVUpCS0JZBg++ DKIM-Signature: a=rsa-sha256; b=YFWiz8ktO58vFuiueejbT4ZlTdTEx/9JgeauFqUUXNld6eQOnuqyOWgrhBIENkoVtvR8Yic44kewgrNUCucHC7vEwEKKFXw7bcyNt7lOhMlKY4NolpoHayhL17QQ+mOLsyBwAobyW3glront1ZAGisXr18Dq0QFJMXitTh7mnkE=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=UsKBMN+CskiWlJDd2yOa0vELygIUKw2NLMSaM/goJpc=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add SDHCI controller driver for Black Sesame Technologies C1200 SoC. This driver supports the DWCMSHC SDHCI controller with BST-specific enhancements including: - Custom clock management and tuning - Power management support - BST-specific register configurations - Support for eMMC and SD card interfaces - Hardware limitation workaround for 32-bit DMA addressing The driver addresses specific hardware constraints where: - System memory uses 64-bit bus, eMMC controller uses 32-bit bus - eMMC controller cannot access memory through SMMU due to hardware bug - All system DRAM is configured outside 4GB boundary (ZONE_DMA32) - Uses SRAM-based bounce buffer within 32-bit address space Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Change for v3: Code improvements based on review feedback: - Simplified dwcmshc_priv structure by removing unused fields - Improved helper functions with better encapsulation - Used devm_platform_ioremap_resource() for resource management - Updated Kconfig description and alphabetical ordering - clarify documentation on hardware limitations and bounce buffer approach - remove duplicate sdhci_writew SDHCI_CLOCK_CONTROL Changes for v2: 1. Dependency Simplification : - Removed COMMON_CLK dependency from Kconfig (MMC_SDHCI_BST) - Add ARCH_BST || COMPILE_TEST dependency from Kconfig (MMC_SDHCI_BST) 2. Resource Management Improvements : - Replaced temporary ioremap with persistent mapping * Mapped CRM registers once during probe instead of per-access * Added proper cleanup in remove callback - Refactored bounce buffer allocation: * Simplified error handling and memory management * Removed unnecessary DMA configuration layers 3. Code Cleanup & Optimization : - Pruned unused headers and legacy vendor debug code - Removed deprecated sdhci_bst_print_vendor() export - Converted internal functions to static scope - Standardized naming conventions: * Renamed DRIVER_NAME to match kernel standards * Changed default_max_freq to DEFAULT_MAX_FREQ - Optimized clock configuration routines 4. Hardware Integration Fixes : - Fixed register access macros for EMMC_CTRL * Added proper offset calculation via SDHCI_VENDOR_PTR_R - Corrected device tree compatibility string to: "bst,c1200-dwcmshc-sdhci" 5. Error Handling Enhancements : - Added robust ioremap error checking - Improved bounce buffer allocation failure handling - Streamlined probe/remove flow 6. Maintainability : - Updated MODULE_DESCRIPTION and AUTHOR fields - Added explanatory comments for hardware limitations - Removed redundant multi-host setup infrastructure 7. fix build warnings from lkp | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202505290615.GZzN5rNL-lkp@intel.com/ --- drivers/mmc/host/Kconfig | 14 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-bst-c1200.c | 510 ++++++++++++++++++++++++++ 3 files changed, 525 insertions(+) create mode 100644 drivers/mmc/host/sdhci-of-bst-c1200.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index c3f0f41a426d..fb057c46949b 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -429,6 +429,20 @@ config MMC_SDHCI_BCM_KONA =20 If you have a controller with this interface, say Y or M here. =20 +config MMC_SDHCI_BST + tristate "SDHCI support for Black Sesame Technologies BST C1200 controlle= r" + depends on ARCH_BST || COMPILE_TEST + depends on MMC_SDHCI_PLTFM + depends on OF + help + This selects the Secure Digital Host Controller Interface (SDHCI) + for Black Sesame Technologies BST C1200 SoC. The controller is + based on Synopsys DesignWare Cores Mobile Storage Controller but + requires platform-specific workarounds for hardware limitations. + + If you have a controller with this interface, say Y or M here. + If unsure, say N. + config MMC_SDHCI_F_SDH30 tristate "SDHCI support for Fujitsu Semiconductor F_SDH30" depends on MMC_SDHCI_PLTFM diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 75bafc7b162b..bb5df05c3174 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXS) +=3D mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) +=3D sdhci.o obj-$(CONFIG_MMC_SDHCI_UHS2) +=3D sdhci-uhs2.o obj-$(CONFIG_MMC_SDHCI_PCI) +=3D sdhci-pci.o +obj-$(CONFIG_MMC_SDHCI_BST) +=3D sdhci-of-bst-c1200.o sdhci-pci-y +=3D sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o= \ sdhci-pci-dwc-mshc.o sdhci-pci-gli.o obj-$(CONFIG_MMC_SDHCI_ACPI) +=3D sdhci-acpi.o diff --git a/drivers/mmc/host/sdhci-of-bst-c1200.c b/drivers/mmc/host/sdhci= -of-bst-c1200.c new file mode 100644 index 000000000000..6d2ba4232306 --- /dev/null +++ b/drivers/mmc/host/sdhci-of-bst-c1200.c @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Black Sesame Technologies SDHCI driver + * + * Copyright (C) 2024 Black Sesame Technologies. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "sdhci.h" +#include "sdhci-pltfm.h" + +struct dwcmshc_priv { + void __iomem *crm_reg_base; +}; + +#define SDHCI_CLOCK_PLL_EN 0x0008 +#define SDHCI_TUNING_COUNT 0x20 +#define SDHCI_VENDOR_PTR_R 0xE8 +#define MBIU_CTRL 0x510 +#define BURST_INCR16_EN BIT(3) +#define BURST_INCR8_EN BIT(2) +#define BURST_INCR4_EN BIT(1) +#define BURST_EN (BURST_INCR16_EN | BURST_INCR8_EN | BURST_INCR4_EN) + +/* Synopsys vendor specific registers */ +#define SDHC_EMMC_CTRL_R_OFFSET 0x2C + +#define SDEMMC_CRM_BCLK_DIV_CTRL 0x08 +#define SDEMMC_CRM_RX_CLK_CTRL 0x14 +#define SDEMMC_CRM_TIMER_DIV_CTRL 0x0C +#define SDEMMC_CRM_VOL_CTRL 0x1C +#define REG_WR_PROTECT 0x88 +#define REG_WR_PROTECT_KEY 0x1234abcd +#define DELAY_CHAIN_SEL 0x94 +#define BST_VOL_STABLE_ON BIT(7) +#define DEFAULT_MAX_FREQ 200000UL + +static u32 bst_crm_read(struct sdhci_pltfm_host *pltfm_host, u32 offset) +{ + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + + return ioread32(priv->crm_reg_base + offset); +} + +static void bst_crm_write(struct sdhci_pltfm_host *pltfm_host, u32 offset,= u32 value) +{ + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + + iowrite32(value, priv->crm_reg_base + offset); +} + +static unsigned int bst_get_max_clock(struct sdhci_host *host) +{ + return host->mmc->f_max; +} + +static unsigned int bst_get_min_clock(struct sdhci_host *host) +{ + return host->mmc->f_min; +} + +struct rx_ctrl { + struct { + u32 rx_revert:1; + u32 rx_clk_sel_sec:1; + u32 rx_clk_div:4; + u32 rx_clk_phase_inner:2; + u32 rx_clk_sel_first:1; + u32 rx_clk_phase_out:2; + u32 rx_clk_en:1; + u32 res0:20; + } bit; + u32 reg; +}; + +struct sdmmc_iocfg { + struct { + u32 res0:16; + u32 SC_SDMMC0_PVDD18POCSD0:2; + u32 SC_SDMMC0_PVDD18POCSD1:2; + u32 SC_SDMMC0_PVDD18POCSD2:2; + u32 SC_SDMMC1_PVDD18POCSD0:2; + u32 SC_SDMMC1_PVDD18POCSD1:2; + u32 SC_SDMMC1_PVDD18POCSD2:2; + u32 res1:4; + } bit; + u32 reg; +}; + +static void sdhci_enable_bst_clk(struct sdhci_host *host, unsigned int clk) +{ + struct sdhci_pltfm_host *pltfm_host; + unsigned int div; + u32 val; + struct rx_ctrl rx_reg; + + pltfm_host =3D sdhci_priv(host); + if (clk =3D=3D 0) { + div =3D clk; + } else if (clk > DEFAULT_MAX_FREQ) { + div =3D clk / 1000; + div =3D DEFAULT_MAX_FREQ / div; + } else if (clk < 1500) { + div =3D clk; + } else { + div =3D DEFAULT_MAX_FREQ * 100; + div =3D div / clk; + div /=3D 100; + } + + clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &=3D ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk &=3D ~SDHCI_CLOCK_PLL_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + val =3D bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL); + val &=3D ~BIT(8); + bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL); + val &=3D ~0xff; + val |=3D 0x20; + bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL); + val |=3D BIT(8); + bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL); + val &=3D ~BIT(11); + bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val); + + rx_reg.reg =3D bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL); + + rx_reg.bit.rx_revert =3D 0; + rx_reg.bit.rx_clk_sel_sec =3D 1; + rx_reg.bit.rx_clk_div =3D 4; + rx_reg.bit.rx_clk_phase_inner =3D 2; + rx_reg.bit.rx_clk_sel_first =3D 0; + rx_reg.bit.rx_clk_phase_out =3D 2; + + bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, rx_reg.reg); + + val =3D bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL); + val |=3D BIT(11); + bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val); + + /* Disable clock first */ + val =3D bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL); + val &=3D ~BIT(10); + bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val); + + /* Setup clock divider */ + val =3D bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL); + val &=3D ~GENMASK(9, 0); + val |=3D div; + bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val); + + /* Enable clock */ + val =3D bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL); + val |=3D BIT(10); + bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val); + + sdhci_writew(host, (div & 0xff) << 8, SDHCI_CLOCK_CONTROL); + + clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk |=3D SDHCI_CLOCK_PLL_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk |=3D SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk |=3D SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +} + +static void sdhci_set_bst_clock(struct sdhci_host *host, unsigned int cloc= k) +{ + if (clock =3D=3D 0) + return; + sdhci_enable_bst_clk(host, clock); +} + +/** + * sdhci_bst_reset - Reset the SDHCI host controller + * @host: SDHCI host controller + * @mask: Reset mask + * + * Performs a reset of the SDHCI host controller with special handling for= eMMC. + */ +static void sdhci_bst_reset(struct sdhci_host *host, u8 mask) +{ + u16 vendor_ptr, emmc_ctrl_reg; + + if (host->mmc->caps2 & MMC_CAP2_NO_SD) { + vendor_ptr =3D sdhci_readw(host, SDHCI_VENDOR_PTR_R); + emmc_ctrl_reg =3D vendor_ptr + SDHC_EMMC_CTRL_R_OFFSET; + + sdhci_writew(host, + sdhci_readw(host, emmc_ctrl_reg) & (~BIT(2)), + emmc_ctrl_reg); + sdhci_reset(host, mask); + usleep_range(10, 20); + sdhci_writew(host, + sdhci_readw(host, emmc_ctrl_reg) | BIT(2), + emmc_ctrl_reg); + } else { + sdhci_reset(host, mask); + } +} + +/** + * sdhci_bst_timeout - Set timeout value for commands + * @host: SDHCI host controller + * @cmd: MMC command + * + * Sets the timeout control register to maximum value (0xE). + */ +static void sdhci_bst_timeout(struct sdhci_host *host, struct mmc_command = *cmd) +{ + sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL); +} + +/** + * sdhci_bst_set_power - Set power mode and voltage + * @host: SDHCI host controller + * @mode: Power mode to set + * @vdd: Voltage to set + * + * Sets power mode and voltage, also configures MBIU control register. + */ +static void sdhci_bst_set_power(struct sdhci_host *host, unsigned char mod= e, + unsigned short vdd) +{ + sdhci_set_power(host, mode, vdd); + sdhci_writeb(host, 0xF, SDHCI_POWER_CONTROL); + sdhci_writew(host, + (sdhci_readw(host, MBIU_CTRL) & (~0xf)) | BURST_EN, + MBIU_CTRL); +} + +/** + * bst_sdhci_execute_tuning - Execute tuning procedure + * @host: SDHCI host controller + * @opcode: Opcode to use for tuning + * + * Performs tuning procedure by trying different values and selecting the = best one. + * + * Return: 0 on success, negative errno on failure + */ +static int bst_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + struct sdhci_pltfm_host *pltfm_host; + unsigned int clk =3D 0, timeout; + int ret =3D 0, error; + int start0 =3D -1, end0 =3D -1, best =3D 0; + int start1 =3D -1, end1 =3D -1, flag =3D 0; + int i; + + pltfm_host =3D sdhci_priv(host); + + for (i =3D 0; i < SDHCI_TUNING_COUNT; i++) { + /* Protected write */ + bst_crm_write(pltfm_host, REG_WR_PROTECT, REG_WR_PROTECT_KEY); + /* Write tuning value */ + bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << i) - 1); + + timeout =3D 20; + while (!((clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & + SDHCI_CLOCK_INT_STABLE)) { + if (timeout =3D=3D 0) { + dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n"); + return -EBUSY; + } + timeout--; + usleep_range(1000, 1100); + } + + ret =3D mmc_send_tuning(host->mmc, opcode, &error); + if (ret !=3D 0) { + flag =3D 1; + } else { + if (flag =3D=3D 0) { + if (start0 =3D=3D -1) + start0 =3D i; + end0 =3D i; + } else { + if (start1 =3D=3D -1) + start1 =3D i; + end1 =3D i; + } + } + } + + /* Calculate best tuning value */ + if (end0 - start0 >=3D end1 - start1) + best =3D ((end0 - start0) >> 1) + start0; + else + best =3D ((end1 - start1) >> 1) + start1; + + if (best < 0) + best =3D 0; + + bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << best) - 1); + timeout =3D 20; + + while (!((clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & + SDHCI_CLOCK_INT_STABLE)) { + if (timeout =3D=3D 0) { + dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n"); + return -EBUSY; + } + timeout--; + usleep_range(1000, 1100); + } + + return 0; +} + +/** + * sdhci_bst_voltage_switch - Perform voltage switch + * @host: SDHCI host controller + * + * Enables voltage stable power. + */ +static void sdhci_bst_voltage_switch(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + + /* vol stable power on */ + bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, BST_VOL_STABLE_ON); +} + +static const struct sdhci_ops sdhci_dwcmshc_ops =3D { + .set_clock =3D sdhci_set_bst_clock, + .set_bus_width =3D sdhci_set_bus_width, + .set_uhs_signaling =3D sdhci_set_uhs_signaling, + .get_min_clock =3D bst_get_min_clock, + .get_max_clock =3D bst_get_max_clock, + .reset =3D sdhci_bst_reset, + .set_power =3D sdhci_bst_set_power, + .set_timeout =3D sdhci_bst_timeout, + .platform_execute_tuning =3D bst_sdhci_execute_tuning, + .voltage_switch =3D sdhci_bst_voltage_switch, +}; + +static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata =3D { + .ops =3D &sdhci_dwcmshc_ops, + .quirks =3D SDHCI_QUIRK_DELAY_AFTER_POWER | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_INVERTED_WRITE_PROTECT, + .quirks2 =3D SDHCI_QUIRK2_BROKEN_DDR50 | + SDHCI_QUIRK2_TUNING_WORK_AROUND | + SDHCI_QUIRK2_ACMD23_BROKEN, +}; + +static int bst_sdhci_reallocate_bounce_buffer(struct sdhci_host *host) +{ + struct mmc_host *mmc =3D host->mmc; + unsigned int max_blocks; + unsigned int bounce_size; + int ret; + + /* + * Cap the bounce buffer at 32KB. Using a bigger bounce buffer + * has diminishing returns, this is probably because SD/MMC + * cards are usually optimized to handle this size of requests. + */ + bounce_size =3D SZ_32K; + /* + * Adjust downwards to maximum request size if this is less + * than our segment size, else hammer down the maximum + * request size to the maximum buffer size. + */ + if (mmc->max_req_size < bounce_size) + bounce_size =3D mmc->max_req_size; + max_blocks =3D bounce_size / 512; + + ret =3D of_reserved_mem_device_init_by_idx(mmc_dev(mmc), mmc_dev(mmc)->of= _node, 0); + if (ret) { + dev_err(mmc_dev(mmc), "Failed to initialize reserved memory\n"); + return ret; + } + + host->bounce_buffer =3D dma_alloc_coherent(mmc_dev(mmc), bounce_size, + &host->bounce_addr, GFP_KERNEL); + if (!host->bounce_buffer) + return -ENOMEM; + + host->bounce_buffer_size =3D bounce_size; + + /* Lie about this since we're bouncing */ + mmc->max_segs =3D max_blocks; + mmc->max_seg_size =3D bounce_size; + mmc->max_req_size =3D bounce_size; + + return 0; +} + +static int dwcmshc_probe(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; + struct dwcmshc_priv *priv; + int err; + + host =3D sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata, + sizeof(struct dwcmshc_priv)); + if (IS_ERR(host)) + return PTR_ERR(host); + + pltfm_host =3D sdhci_priv(host); + priv =3D sdhci_pltfm_priv(pltfm_host); + + err =3D mmc_of_parse(host->mmc); + if (err) + goto err; + + sdhci_get_of_property(pdev); + + /* Get CRM registers from the second reg entry */ + priv->crm_reg_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(priv->crm_reg_base)) { + err =3D PTR_ERR(priv->crm_reg_base); + goto err; + } + + err =3D sdhci_add_host(host); + if (err) + goto err; + + /* + * Silicon constraints for BST C1200: + * - System RAM base is 0x800000000 (above 32-bit addressable range) + * - The eMMC controller DMA engine is limited to 32-bit addressing + * - SMMU cannot be used on this path due to hardware design flaws + * - These are fixed in silicon and cannot be changed in software + * + * Bus/controller mapping: + * - No registers are available to reprogram the address mapping + * - The 32-bit DMA limit is a hard constraint of the controller IP + * + * Given these constraints, an SRAM-based bounce buffer in the 32-bit + * address space is required to enable eMMC DMA on this platform. + */ + err =3D bst_sdhci_reallocate_bounce_buffer(host); + if (err) { + dev_err(&pdev->dev, "Failed to allocate bounce buffer: %d\n", err); + goto err_remove_host; + } + + return 0; + +err_remove_host: + sdhci_remove_host(host, 1); +err: + sdhci_pltfm_free(pdev); + return err; +} + +static void dwcmshc_remove(struct platform_device *pdev) +{ + struct sdhci_host *host =3D platform_get_drvdata(pdev); + + /* Free bounce buffer if allocated */ + if (host->bounce_buffer) { + dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size, + host->bounce_buffer, host->bounce_addr); + host->bounce_buffer =3D NULL; + } + + /* Release reserved memory */ + of_reserved_mem_device_release(mmc_dev(host->mmc)); + + sdhci_remove_host(host, 0); + sdhci_pltfm_free(pdev); +} + +static const struct of_device_id sdhci_dwcmshc_dt_ids[] =3D { + { .compatible =3D "bst,c1200-dwcmshc-sdhci" }, + {} +}; +MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); + +static struct platform_driver sdhci_dwcmshc_driver =3D { + .driver =3D { + .name =3D "sdhci-dwcmshc", + .of_match_table =3D sdhci_dwcmshc_dt_ids, + }, + .probe =3D dwcmshc_probe, + .remove =3D dwcmshc_remove, +}; +module_platform_driver(sdhci_dwcmshc_driver); + +MODULE_DESCRIPTION("Black Sesame Technologies DWCMSHC SDHCI driver"); +MODULE_AUTHOR("Black Sesame Technologies Co., Ltd."); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sat Oct 4 22:35:33 2025 Received: from mail-m32117.qiye.163.com (mail-m32117.qiye.163.com [220.197.32.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5468239E67; Tue, 12 Aug 2025 13:07:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.117 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755004030; cv=none; b=clm7B5sPhmyAnzxHM4YXMt59c0VpHJXe0wmPPXQ6Gb2Cf58dCkXqnnl9aZ5FVjIxagykAbiHA/vUImpDphNgjDswP2/hcr7LcTMOo/KfhZjC29qksmXIyJdbW3p2vJsI7wN0xF6Jql6OKXoDNA5NzKtdIwtxLkAydO8SN2Xna0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755004030; c=relaxed/simple; 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(unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1f211b6d5; Tue, 12 Aug 2025 20:31:34 +0800 (GMT+08:00) From: Albert Yang To: krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v3 6/8] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board Date: Tue, 12 Aug 2025 20:31:08 +0800 Message-ID: <20250812123110.2090460-7-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812123110.2090460-1-yangzh0906@thundersoft.com> References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a989e43b80909cckunm52c5de628443a1 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCGR9KVktJTU1NTR5CQk0ZH1YVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=UnZiAkF8OZuGRlSIc/9rcuYUmjLpOaGzWqjjZ+VMUbMY60dk0SAsuqK3rftpJuMaihQKuktXid82Ej+jPJGizcoRQJehqNmcQ2LWlpXuL8PoCSNHGWXjs/Ecp1Y7mwmM6s+7CcQgpJLqOLKfqCopZLsIiN9ZPkbavdYOclX5bpw=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=3HpFPSzH5BMSx25qJxY63JWzAKDMBMOt+NibaE+k1AM=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, MMC, watchdog timer, and interrupt controller. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Changes for v3: - Split defconfig enablement out into a dedicated defconfig patch - Refine memory description: consolidate ranges in memory node and delele unused memory ranges - Adjust the order of nodes - remove mask of gic Changes for v2: 1. Reorganized memory map into discrete regions 2. Updated MMC controller definition: - Split into core/CRM register regions - Removed deprecated properties - Updated compatible string 3. Standardized interrupt definitions and numeric formats 4. Removed reserved-memory node (superseded by bounce buffers) 5. Added root compatible string for platform identification 6. Add soc defconfig --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/bst/Makefile | 2 + .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 42 +++++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 117 ++++++++++++++++++ 4 files changed, 162 insertions(+) create mode 100644 arch/arm64/boot/dts/bst/Makefile create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..a39b6cafb644 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -12,6 +12,7 @@ subdir-y +=3D arm subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom +subdir-y +=3D bst subdir-y +=3D cavium subdir-y +=3D exynos subdir-y +=3D freescale diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Mak= efile new file mode 100644 index 000000000000..4c1b8b4cdad8 --- /dev/null +++ b/arch/arm64/boot/dts/bst/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BST) +=3D bstc1200-cdcu1.0-adas_4c2g.dtb diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/= arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts new file mode 100644 index 000000000000..d8fb07b0bc80 --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "bstc1200.dtsi" + +/ { + model =3D "BST C1200-96 CDCU1.0 4C2G"; + compatible =3D "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@810000000 { + device_type =3D "memory"; + reg =3D <0x8 0x10000000 0x0 0x30000000>, + <0x8 0xc0000000 0x1 0x0>, + <0xc 0x00000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + mmc0_reserved: mmc0-reserved@5160000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x5160000 0x0 0x10000>; + no-map; + }; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&mmc0 { + status =3D "okay"; + memory-region =3D <&mmc0_reserved>; +}; + diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bs= t/bstc1200.dtsi new file mode 100644 index 000000000000..5e9ca0ee17cf --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +/ { + compatible =3D "bst,c1200"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clk_mmc: clock-4000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <4000000>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0>; + }; + + cpu@1 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x100>; + }; + + cpu@2 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x200>; + }; + + cpu@3 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x300>; + }; + + l2_cache: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + interrupt-parent =3D <&gic>; + + uart0: serial@20008000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x20008000 0x0 0x1000>; + interrupts =3D ; + clock-frequency =3D <25000000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + mmc0: mmc@22200000 { + compatible =3D "bst,c1200-dwcmshc-sdhci"; + reg =3D <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_mmc>; + clock-names =3D "core"; + max-frequency =3D <200000000>; + bus-width =3D <8>; + non-removable; + dma-coherent; + status =3D "disabled"; + }; + + gic: interrupt-controller@32800000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-controller; + ranges; + reg =3D <0x0 0x32800000 0x0 0x10000>, + <0x0 0x32880000 0x0 0x100000>; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + always-on; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0 From nobody Sat Oct 4 22:35:33 2025 Received: from mail-m3290.qiye.163.com (mail-m3290.qiye.163.com [220.197.32.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BF9B23B63F; Tue, 12 Aug 2025 12:36:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.90 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755002212; cv=none; b=WYpkLASaDN1ZqVNSv6q8t4QNsCVXri3oSscR+HQEWN77DVWgKOl3nObss+B9OlAXBncr+4qIFzhs0g5zmsRKn0uFx5Bdk63r8Umkxj7P/opesfbvn8wm1FD4eBnLfFnk7gYxRvOgIzAnZxs1XWqt/S6HVkmyYP8npkSBHi0wXPw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755002212; c=relaxed/simple; bh=zTgB+HkIWxyZXYFmwnQgvESXKIPYQxN69x/bv377KDI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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(unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1f211b6d7; Tue, 12 Aug 2025 20:31:37 +0800 (GMT+08:00) From: Albert Yang To: krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v3 7/8] arm64: defconfig: enable BST platform and SDHCI controller support Date: Tue, 12 Aug 2025 20:31:09 +0800 Message-ID: <20250812123110.2090460-8-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812123110.2090460-1-yangzh0906@thundersoft.com> References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a989e43c28509cckunm52c5de628443cc X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZQ0JMVk0aTRlOSxhMShkZSVYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=OIOieOabStHm2JazoXydk/fhydRg4Q9mi/tfK3CChPUTmplGxJk27odPBGKfsxD7nu91J4PvuPOkcLMmPYdDuylEgKLRb3AaDn2I3Bz1YJ+G8nCZ7sG/LEWXd98fDgulxIDWrQ7rJ8hQxFqTv19mvXVzbaZl9jfFgmc3HTpZ8Q8=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=kJ742w8ZJVIuGW3jnwo9Rh3GEZ+ujaREsWARlA26Ou4=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Enable support for Black Sesame Technologies (BST) platform and drivers in the ARM64 defconfig: - CONFIG_ARCH_BST: Enable BST SoC platform support - CONFIG_MMC_SDHCI_BST: Enable BST C1200 DWCMSHC SDHCI controller driver This enables eMMC/SD card access on Black Sesame Technologies C1200 series SoCs. The SDHCI driver provides hardware-specific implementation for the Synopsys DesignWare Mobile Storage Host Controller integrated in BST SoCs. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Change for v3: - Also enable CONFIG_ARCH_BST in arm64 defconfig (in addition to CONFIG_MMC_SDHCI_BST) Change for v2: - No changes. --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 897fc686e6a9..8daf8cf3dc97 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=3Dy CONFIG_ARCH_BRCMSTB=3Dy CONFIG_ARCH_BERLIN=3Dy CONFIG_ARCH_BLAIZE=3Dy +CONFIG_ARCH_BST=3Dy CONFIG_ARCH_EXYNOS=3Dy CONFIG_ARCH_SPARX5=3Dy CONFIG_ARCH_K3=3Dy @@ -1187,6 +1188,7 @@ CONFIG_MMC_SDHCI_CADENCE=3Dy CONFIG_MMC_SDHCI_ESDHC_IMX=3Dy CONFIG_MMC_SDHCI_TEGRA=3Dy CONFIG_MMC_SDHCI_F_SDH30=3Dy +CONFIG_MMC_SDHCI_BST=3Dy CONFIG_MMC_MESON_GX=3Dy CONFIG_MMC_SDHCI_MSM=3Dy CONFIG_MMC_SPI=3Dy --=20 2.43.0 From nobody Sat Oct 4 22:35:33 2025 Received: from mail-m1973185.qiye.163.com (mail-m1973185.qiye.163.com [220.197.31.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 527D71898F8; Tue, 12 Aug 2025 13:47:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.85 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006449; cv=none; b=sfeyRKUiLI0h68P8Ol6aDQshxUr3lAquRJNdAD8aBP3QiG9WGiVEwGwxpnWvYUwVFz5UO25wB1KY67wjJy78jUUivRC21K24jLSXV9uwqnLH5XuOEkv0EfjTDeRF9HkYGF1NmMwkOgDOTWXfnoE2+0yWADiY9LpHfG0UB3xHIGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006449; c=relaxed/simple; bh=stMMaO5wLaUCV4mB05syLNssHPpeCsNJDHr689x5/8Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BjJw8BNT2DHNCtqWhAaA/zYZFScyj1XLMvSQYm8IgFVQUzIInBjnfxp3sCVdlZEg2ZvtegUp0WrHt48zUl7aKfJQpd5svf3TGrT2CXLbl8VRY2KGIQjHVlObIGwB7w5XipFzs2XyAjDOcWxa0GPb0n7u4cQb7PxoaLhjvHafgXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=TlyYPy41; arc=none smtp.client-ip=220.197.31.85 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="TlyYPy41" Received: from albert-OptiPlex-7080.. (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1f211b6d9; Tue, 12 Aug 2025 20:31:39 +0800 (GMT+08:00) From: Albert Yang To: krzk@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ulf.hansson@linaro.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, adrian.hunter@intel.com, robin.murphy@arm.com, ding.wang@bst.ai, gordon.ge@bst.ai Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, linux-kernel@vger.kernel.org, Albert Yang Subject: [PATCH v3 8/8] MAINTAINERS: add and consolidate Black Sesame Technologies (BST) ARM SoC support Date: Tue, 12 Aug 2025 20:31:10 +0800 Message-ID: <20250812123110.2090460-9-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250812123110.2090460-1-yangzh0906@thundersoft.com> References: <20250812123110.2090460-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a989e43c9c809cckunm52c5de628443e3 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCS04dVkpITUpKTUJPTkxLHlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=TlyYPy41p0fjSOSw/DXJYeY/u7nlf4/zwGoyL9ES27467blCjCHPRGpDBoOBehWgMXuHNftPWscE0sinYV7Y0m+A6A+fJMCbMhpju+CZV/pdmdCkTmtWZ6Tq7r85YIe1U3jqxD+Kdw2Zro8+kaBWI6OS80dWjux6NqDDP8utsuU=; s=default; c=relaxed/relaxed; d=thundersoft.com; v=1; bh=5XY1+cf0NTb0xRpC03OIMhJWcVNtQLjQy5avmpN1TZY=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add and consolidate the MAINTAINERS entry for Black Sesame Technologies ARM SoC support. This entry covers device tree bindings, drivers, and board files for BST SoCs, including MMC, and platform support. Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- Change for v3: - No changes Change for v2: - No changes --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index efb51ee92683..e3236384c28a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2441,6 +2441,16 @@ S: Maintained F: Documentation/devicetree/bindings/arm/blaize.yaml F: arch/arm64/boot/dts/blaize/ =20 +ARM/BST SOC SUPPORT +M: Ge Gordon +R: BST Linux Kernel Upstream Group +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/arm/bst.yaml +F: Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml +F: arch/arm64/boot/dts/bst/ +F: drivers/mmc/host/sdhci-of-bst-c1200.c + ARM/CALXEDA HIGHBANK ARCHITECTURE M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.43.0