From nobody Sun Oct 5 00:16:34 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24BA62EF651; Tue, 12 Aug 2025 10:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754993324; cv=none; b=TtZEctbTrwlXVnmxtz6x493pYDQy8lBBUBQzI0AmH59mTR2BDTzasI73AdbZXeKz8Si9fIEjpJLZP7nDAZTh3qnXMYUkhGLecebHigDqVz4Jk711QUHTUVxAgh9YObm3QDyW13sE5e7OkwOdiIubYGDJ7wE/UmUHXHBZGpwpO78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754993324; c=relaxed/simple; bh=sDLN2BozXJb+Dv+rfdAAuoiT+Ufjq+r3/bi3B0ON6pw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aGa/CzuTIEYNZMJbF90DHHCeIEmyVLbw7GXJvoclgXk785s1zGwWF1D7j6WEkf4IRKi8saAckWIHloUkURCR1tDk6EEExcSySuFEORulo9kRiJIpCfMCwCYgjtmCMaZ1KlxDlYmeWKE4uHLVYaQpHyvNYkiywPIgEFadw+kMtHo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 18:08:30 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 18:08:30 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kevin Chen , , , , Subject: [PATCH v4 1/2] dt-bindings: interrupt-controller: aspeed: Add parent compatibles and refine documentation Date: Tue, 12 Aug 2025 18:08:29 +0800 Message-ID: <20250812100830.145578-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250812100830.145578-1-ryan_chen@aspeedtech.com> References: <20250812100830.145578-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2700 contains two independent top-level interrupt controllers (INTC0, INTC1). Each occupies its own register space and handles different sets of peripherals. Above them, the PSP (CA35) GIC is the root interrupt aggregator. In hardware, INTC1 outputs are routed into INTC0, and INTC0 outputs are routed into the GIC. Introduce distinct compatibles for these parent blocks so the DT can model the hierarchy and register space layout accurately: - aspeed,ast2700-intc0 (parent node at 0x12100000) - aspeed,ast2700-intc1 (parent node at 0x14c18000) The existing child compatible: - aspeed,ast2700-intc-ic continues to describe the interrupt-controller instances within each INTC block (e.g. INTC0_0..INTC0_11 and INTC1_0..INTC1_5). Signed-off-by: Ryan Chen --- .../aspeed,ast2700-intc.yaml | 158 +++++++++++++----- 1 file changed, 115 insertions(+), 43 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml index 55636d06a674..81304b53c112 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -10,6 +10,33 @@ description: This interrupt controller hardware is second level interrupt controller = that is hooked to a parent interrupt controller. It's useful to combine multi= ple interrupt sources into 1 interrupt to parent interrupt controller. + Depend to which INTC0 or INTC1 used. + INTC0 and INTC1 are two kinds of interrupt controller with enable and raw + status registers for use. + INTC0 is used to assert GIC if interrupt in INTC1 asserted. + INTC1 is used to assert INTC0 if interrupt of modules asserted. + +-----+ +---------+ + | GIC |---| INTC0 | + +-----+ +---------+ + +---------+ + | |---module0 + | INTC0_0 |---module1 + | |---... + +---------+---module31 + |---.... | + +---------+ + | | +---------+ + | INTC0_11| +---| INTC1 | + | | +---------+ + +---------+ +---------+---module0 + | INTC1_0 |---module1 + | |---... + +---------+---module31 + ... + +---------+---module0 + | INTC1_5 |---module1 + | |---... + +---------+---module31 =20 maintainers: - Kevin Chen @@ -17,49 +44,70 @@ maintainers: properties: compatible: enum: - - aspeed,ast2700-intc-ic + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 =20 reg: maxItems: 1 =20 - interrupt-controller: true + '#address-cells': + const: 2 =20 - '#interrupt-cells': + '#size-cells': const: 2 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - maxItems: 6 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 =20 + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: Interrupt group child nodes + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger + type. + + interrupts: + minItems: 1 + maxItems: 6 + description: | + The interrupts provided by this interrupt controller. + + interrupts-extended: + minItems: 1 + maxItems: 6 + description: | + This property is required when defining a cascaded interrupt con= troller + that is connected under another interrupt controller. It specifi= es the + parent interrupt(s) in the upstream controller to which this con= troller + is connected. + + oneOf: + - required: [interrupts] + - required: [interrupts-extended] + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' =20 required: - compatible - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts =20 additionalProperties: false =20 @@ -68,19 +116,43 @@ examples: #include =20 bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + intc0: interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0"; + reg =3D <0 0x12100000 0 0x4000>; + ranges =3D <0x0 0x0 0x0 0x12100000 0x0 0x4000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + intc0_11: interrupt-controller@1b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0 0x12101b00 0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D , + , + , + , + , + ; + }; + }; + + intc1: interrupt-controller@14c18000 { + compatible =3D "aspeed,ast2700-intc1"; + reg =3D <0 0x14c18000 0 0x400>; + ranges =3D <0x0 0x0 0x0 0x14c18000 0x0 0x400>; #address-cells =3D <2>; #size-cells =3D <2>; =20 - interrupt-controller@12101b00 { - compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <2>; - interrupt-controller; - interrupts =3D , - , - , - , - , - ; + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x100 0x0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | I= RQ_TYPE_LEVEL_HIGH)>; }; + }; }; --=20 2.34.1