From nobody Sat Oct 4 22:34:43 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24BA62EF651; Tue, 12 Aug 2025 10:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754993324; cv=none; b=TtZEctbTrwlXVnmxtz6x493pYDQy8lBBUBQzI0AmH59mTR2BDTzasI73AdbZXeKz8Si9fIEjpJLZP7nDAZTh3qnXMYUkhGLecebHigDqVz4Jk711QUHTUVxAgh9YObm3QDyW13sE5e7OkwOdiIubYGDJ7wE/UmUHXHBZGpwpO78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754993324; c=relaxed/simple; bh=sDLN2BozXJb+Dv+rfdAAuoiT+Ufjq+r3/bi3B0ON6pw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aGa/CzuTIEYNZMJbF90DHHCeIEmyVLbw7GXJvoclgXk785s1zGwWF1D7j6WEkf4IRKi8saAckWIHloUkURCR1tDk6EEExcSySuFEORulo9kRiJIpCfMCwCYgjtmCMaZ1KlxDlYmeWKE4uHLVYaQpHyvNYkiywPIgEFadw+kMtHo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 18:08:30 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 18:08:30 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kevin Chen , , , , Subject: [PATCH v4 1/2] dt-bindings: interrupt-controller: aspeed: Add parent compatibles and refine documentation Date: Tue, 12 Aug 2025 18:08:29 +0800 Message-ID: <20250812100830.145578-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250812100830.145578-1-ryan_chen@aspeedtech.com> References: <20250812100830.145578-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2700 contains two independent top-level interrupt controllers (INTC0, INTC1). Each occupies its own register space and handles different sets of peripherals. Above them, the PSP (CA35) GIC is the root interrupt aggregator. In hardware, INTC1 outputs are routed into INTC0, and INTC0 outputs are routed into the GIC. Introduce distinct compatibles for these parent blocks so the DT can model the hierarchy and register space layout accurately: - aspeed,ast2700-intc0 (parent node at 0x12100000) - aspeed,ast2700-intc1 (parent node at 0x14c18000) The existing child compatible: - aspeed,ast2700-intc-ic continues to describe the interrupt-controller instances within each INTC block (e.g. INTC0_0..INTC0_11 and INTC1_0..INTC1_5). Signed-off-by: Ryan Chen --- .../aspeed,ast2700-intc.yaml | 158 +++++++++++++----- 1 file changed, 115 insertions(+), 43 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml index 55636d06a674..81304b53c112 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -10,6 +10,33 @@ description: This interrupt controller hardware is second level interrupt controller = that is hooked to a parent interrupt controller. It's useful to combine multi= ple interrupt sources into 1 interrupt to parent interrupt controller. + Depend to which INTC0 or INTC1 used. + INTC0 and INTC1 are two kinds of interrupt controller with enable and raw + status registers for use. + INTC0 is used to assert GIC if interrupt in INTC1 asserted. + INTC1 is used to assert INTC0 if interrupt of modules asserted. + +-----+ +---------+ + | GIC |---| INTC0 | + +-----+ +---------+ + +---------+ + | |---module0 + | INTC0_0 |---module1 + | |---... + +---------+---module31 + |---.... | + +---------+ + | | +---------+ + | INTC0_11| +---| INTC1 | + | | +---------+ + +---------+ +---------+---module0 + | INTC1_0 |---module1 + | |---... + +---------+---module31 + ... + +---------+---module0 + | INTC1_5 |---module1 + | |---... + +---------+---module31 =20 maintainers: - Kevin Chen @@ -17,49 +44,70 @@ maintainers: properties: compatible: enum: - - aspeed,ast2700-intc-ic + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 =20 reg: maxItems: 1 =20 - interrupt-controller: true + '#address-cells': + const: 2 =20 - '#interrupt-cells': + '#size-cells': const: 2 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - maxItems: 6 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 =20 + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: Interrupt group child nodes + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger + type. + + interrupts: + minItems: 1 + maxItems: 6 + description: | + The interrupts provided by this interrupt controller. + + interrupts-extended: + minItems: 1 + maxItems: 6 + description: | + This property is required when defining a cascaded interrupt con= troller + that is connected under another interrupt controller. It specifi= es the + parent interrupt(s) in the upstream controller to which this con= troller + is connected. + + oneOf: + - required: [interrupts] + - required: [interrupts-extended] + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' =20 required: - compatible - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts =20 additionalProperties: false =20 @@ -68,19 +116,43 @@ examples: #include =20 bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + intc0: interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0"; + reg =3D <0 0x12100000 0 0x4000>; + ranges =3D <0x0 0x0 0x0 0x12100000 0x0 0x4000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + intc0_11: interrupt-controller@1b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0 0x12101b00 0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D , + , + , + , + , + ; + }; + }; + + intc1: interrupt-controller@14c18000 { + compatible =3D "aspeed,ast2700-intc1"; + reg =3D <0 0x14c18000 0 0x400>; + ranges =3D <0x0 0x0 0x0 0x14c18000 0x0 0x400>; #address-cells =3D <2>; #size-cells =3D <2>; =20 - interrupt-controller@12101b00 { - compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <2>; - interrupt-controller; - interrupts =3D , - , - , - , - , - ; + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x100 0x0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | I= RQ_TYPE_LEVEL_HIGH)>; }; + }; }; --=20 2.34.1 From nobody Sat Oct 4 22:34:43 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C221D2EFD84; Tue, 12 Aug 2025 10:08:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754993326; cv=none; b=FsrgJzU3bpPwIyBXXx2Whj4whrODklVyst4tBib0LtzSslAAKb38Bgrzcs3BVRnuhd0lzZMwp7oEvzVL0L9jcxXFA3C8gUg2apB4ulCqqSOi6crXYXI1lzXA6EgSq08GxuWqwKZtaNrU18RawDyrf+QMHsWORU9GTcj9VFh/+SY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754993326; c=relaxed/simple; bh=boNUNTEbc1FZDsnH9y9PLw5Zh8iuulYiDkEv0attGC8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V3cmy8O8zlPZ34EdDuaZ5idttQ73BDCg2LX2PVGCjLyE5XWs+VPkazN7oY696oIHZVWNJU07c6C5caeYgHWrVGxfqeVMn5Dl/fUJMWN9hb30bgmbDtOtXIbEBYdIwZi82X8beLVeiwotCMzfgskiTG7tgSFT9f2Y5lPUm/vsgQ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 18:08:30 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 18:08:30 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kevin Chen , , , , Subject: [PATCH v4 2/2] Irqchip/ast2700-intc: add debugfs support and AST2700 INTC0/INTC1 routing/protection display Date: Tue, 12 Aug 2025 18:08:30 +0800 Message-ID: <20250812100830.145578-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250812100830.145578-1-ryan_chen@aspeedtech.com> References: <20250812100830.145578-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2700 INTC0/INTC1 nodes ("aspeed,ast2700-intc0/1") not only include the interrupt controller child node ("aspeed,ast2700-intc-ic"), but also provide interrupt routing and register protection features. Adds debugfs entries for interrupt routing and protection status for AST2700 INTC0/INTC1. Signed-off-by: Ryan Chen --- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ast2700-intc.c | 174 +++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 drivers/irqchip/irq-ast2700-intc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index c3928ef79344..9f6473bf4055 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -97,6 +97,12 @@ config AL_FIC help Support Amazon's Annapurna Labs Fabric Interrupt Controller. =20 +config AST2700_INTC + tristate "AST2700 Interrupt Controller" + depends on ARCH_ASPEED + help + Support AST2700 Interrupt Controller. + config ATMEL_AIC_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 23ca4959e6ce..eea0a8699204 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_LS_EXTIRQ) +=3D irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) +=3D irq-ls-scfg-msi.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-a= speed-scu-ic.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-intc.o +obj-$(CONFIG_AST2700_INTC) +=3D irq-ast2700-intc.o obj-$(CONFIG_STM32MP_EXTI) +=3D irq-stm32mp-exti.o obj-$(CONFIG_STM32_EXTI) +=3D irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) +=3D qcom-irq-combiner.o diff --git a/drivers/irqchip/irq-ast2700-intc.c b/drivers/irqchip/irq-ast27= 00-intc.c new file mode 100644 index 000000000000..7c7241539fe5 --- /dev/null +++ b/drivers/irqchip/irq-ast2700-intc.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AST2700 Interrupt Controller + */ + +#include +#include +#include +#include +#include +#include +#include + +/* INTC0 register layout */ +#define INTC0_PROT_OFFS 0x40 +#define INTC0_ROUTING_SEL0_BASE 0x200 +#define INTC0_ROUTING_GAP 0x100 +#define INTC0_GROUPS 4 + +/* INTC1 register layout */ +#define INTC1_PROT_OFFS 0x00 +#define INTC1_ROUTING_SEL0_BASE 0x80 +#define INTC1_ROUTING_GAP 0x20 +#define INTC1_GROUPS 6 + +struct aspeed_intc_data { + const char *name; + u32 prot_offs; + u32 rout_sel0_base; + u32 rout_gap; + unsigned int groups; +}; + +static const struct aspeed_intc_data aspeed_intc0_data =3D { + .name =3D "INTC0", + .prot_offs =3D INTC0_PROT_OFFS, + .rout_sel0_base =3D INTC0_ROUTING_SEL0_BASE, + .rout_gap =3D INTC0_ROUTING_GAP, + .groups =3D INTC0_GROUPS, +}; + +static const struct aspeed_intc_data aspeed_intc1_data =3D { + .name =3D "INTC1", + .prot_offs =3D INTC1_PROT_OFFS, + .rout_sel0_base =3D INTC1_ROUTING_SEL0_BASE, + .rout_gap =3D INTC1_ROUTING_GAP, + .groups =3D INTC1_GROUPS, +}; + +struct aspeed_intc { + void __iomem *base; + const struct aspeed_intc_data *data; +#ifdef CONFIG_DEBUG_FS + struct dentry *dbg_root; +#endif +}; + +#ifdef CONFIG_DEBUG_FS +static int aspeed_intc_regs_show(struct seq_file *s, void *unused) +{ + struct aspeed_intc *intc =3D s->private; + const struct aspeed_intc_data *d =3D intc->data; + void __iomem *base =3D intc->base; + unsigned int i; + + for (i =3D 0; i < d->groups; i++) { + void __iomem *b =3D base + d->rout_sel0_base + i * 4; + u32 r0 =3D readl(b); + u32 r1 =3D readl(b + d->rout_gap); + u32 r2 =3D readl(b + 2 * d->rout_gap); + + seq_printf(s, "ROUTE[%u]: 0x%08x 0x%08x 0x%08x\n", i, r0, r1, r2); + } + return 0; +} + +static int aspeed_intc_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, aspeed_intc_regs_show, inode->i_private); +} + +static const struct file_operations aspeed_intc_regs_fops =3D { + .owner =3D THIS_MODULE, + .open =3D aspeed_intc_regs_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static int aspeed_intc_prot_show(struct seq_file *s, void *unused) +{ + struct aspeed_intc *intc =3D s->private; + const struct aspeed_intc_data *d =3D intc->data; + u32 prot =3D readl(intc->base + d->prot_offs); + + seq_printf(s, "%s_PROT: 0x%08x\n", d->name, prot); + return 0; +} + +static int aspeed_intc_prot_open(struct inode *inode, struct file *file) +{ + return single_open(file, aspeed_intc_prot_show, inode->i_private); +} + +static const struct file_operations aspeed_intc_prot_fops =3D { + .owner =3D THIS_MODULE, + .open =3D aspeed_intc_prot_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; +#endif /* CONFIG_DEBUG_FS */ + +static int aspeed_intc_probe(struct platform_device *pdev) +{ + const struct aspeed_intc_data *data; + struct aspeed_intc *intc; + struct resource *res; + + data =3D of_device_get_match_data(&pdev->dev); + if (!data) + return -ENODEV; + + intc =3D devm_kzalloc(&pdev->dev, sizeof(*intc), GFP_KERNEL); + if (!intc) + return -ENOMEM; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + intc->base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(intc->base)) + return PTR_ERR(intc->base); + + intc->data =3D data; + + platform_set_drvdata(pdev, intc); + +#ifdef CONFIG_DEBUG_FS + intc->dbg_root =3D debugfs_create_dir(dev_name(&pdev->dev), NULL); + if (intc->dbg_root) { + debugfs_create_file("routing", 0400, intc->dbg_root, intc, + &aspeed_intc_regs_fops); + debugfs_create_file("protection", 0400, intc->dbg_root, intc, + &aspeed_intc_prot_fops); + } +#endif + return 0; +} + +static void aspeed_intc_remove(struct platform_device *pdev) +{ +#ifdef CONFIG_DEBUG_FS + struct aspeed_intc *intc =3D platform_get_drvdata(pdev); + + if (intc && intc->dbg_root) + debugfs_remove_recursive(intc->dbg_root); +#endif +} + +static const struct of_device_id aspeed_intc_of_match[] =3D { + { .compatible =3D "aspeed,ast2700-intc0", .data =3D &aspeed_intc0_data }, + { .compatible =3D "aspeed,ast2700-intc1", .data =3D &aspeed_intc1_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, aspeed_intc_of_match); + +static struct platform_driver aspeed_intc_driver =3D { + .probe =3D aspeed_intc_probe, + .remove =3D aspeed_intc_remove, + .driver =3D { + .name =3D "aspeed-ast2700-intc", + .of_match_table =3D aspeed_intc_of_match, + }, +}; +module_platform_driver(aspeed_intc_driver); --=20 2.34.1