From nobody Sat Oct 4 22:37:55 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A53D52D3A86; Tue, 12 Aug 2025 05:43:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754977420; cv=pass; b=bJ4sg5Y8dk3Tv0qb3LHXspfVbHQTJi+40nYMc3Jrn6aO8rNieJz2nXmcAH8F62lSfI3aTkJlvFLc5xJi2uulOhd6azQLtlyEqfXiui1ni0RtJC66wvP1GfVCH3KpKLaGwNA8XRBFkbRYyjNEUK9kJzYPMtmJY4TNTJqZp3aAKTE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754977420; c=relaxed/simple; bh=cEC9SR9p4KE1+omUnvPVyRkiYxn4fvf6NCz/Fun2YFY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SIsGzhEHzfelvWzbXimONpQenGNDMDdN5/ssCGvzBRa3PGoUo3IPV7qkBaJwtau9hqIdaBfOIpplaICVvG/Tjht0GmlOqfq2qKMzf8oAtn+H7C8Nkoi5w1yw8ZalotRm6+rI1nvT1FWLWJwyKoDjRknu4Ayh/ktN/o83L6YJH0M= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=jJdqH35y; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="jJdqH35y" ARC-Seal: i=1; a=rsa-sha256; t=1754977408; cv=none; d=zohomail.com; s=zohoarc; b=eAhIiWNmQ6ezpM1mxCLbOoGo7q8UUea4xRmCr8FPbJpmC5raikgQsSOsRQZ17G7bfWSKbzfhAk9XJSbQEf9GWH8VqS8MJC5qAkB1LzL/FW1fWd2KF0kdY6gq3iMLeCovrLdKdqg/38o9sSEg6Gb7EOZzKS7DyubAUtbO6MS1Pz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1754977408; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=ru2Vsb7/og+EijPXl6fKV4Ujus+LUwB94JMCeT6zV3E=; b=E49ACa9e1KlsFqR6tntCei7Gg+hj1n2Ak6CZ16s35GCrngNIkKsxl75skuNlv4sAVA1uBzWE+tGqhweoHnRzMXTGAPx9w6rFVQrmgh83LOOK8N4cYB4GT7uuW+ktImWPq03yHcqoEPmOS+2xHrZS8PoLKEK/u3p41gEFxdQiV/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1754977408; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=ru2Vsb7/og+EijPXl6fKV4Ujus+LUwB94JMCeT6zV3E=; b=jJdqH35y2BSVPgoURVbes57NTgZDZdGATmlg45vbV2oMEzJ4v7ydjFaOO7yduL6K WkBNuLZ7oXeJkML4RVJquQwC52k6kgqzap2fjYZwGo4zxeAiJu8qCgvUXUBq1vMLbRZ UjzbWN0IAwmCCQot+ncGlmRI6h5BdhgDWPvZcCuz0dgVzqBQcDm3rXtjV9oElAeAF2N dOZzuOX8IasspGRs/JV6ws/TS7du6v50LnnZDldj2G6D7ZrlZJjBNeLoV39R6czH9ly P6UYfbrj/YJaYdUwK3gJbHDMz1QJ48v/QzroTjtgyDjGO/HjMszDc8SizVXXV2MWF6S Q8nroX+eAw== Received: by mx.zohomail.com with SMTPS id 1754977406437790.7145889568351; Mon, 11 Aug 2025 22:43:26 -0700 (PDT) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Michal Wilczynski Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH 1/4] clk: thead: add support for enabling/disabling PLLs Date: Tue, 12 Aug 2025 13:42:55 +0800 Message-ID: <20250812054258.1968351-2-uwu@icenowy.me> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250812054258.1968351-1-uwu@icenowy.me> References: <20250812054258.1968351-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" The 2nd control word of T-Head TH1520 PLLs contains a bit to put the VCO into reset state, which means disabling the PLL. Some PLLs are put to disabled state by the bootloader, and the clock driver should be able to enable them. Add support for enabling/disabling PLLs. PLLs other than DPU ones are set CLK_IS_CRITICAL to prevent killing the system -- they're meant to drive CPU or system buses (even the GMAC/Video ones are driving arbitrary buses). Signed-off-by: Icenowy Zheng --- drivers/clk/thead/clk-th1520-ap.c | 38 +++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index dd6359441f7e8..2f87c7c2c3baf 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -18,6 +18,7 @@ #define TH1520_PLL_FBDIV GENMASK(19, 8) #define TH1520_PLL_REFDIV GENMASK(5, 0) #define TH1520_PLL_BYPASS BIT(30) +#define TH1520_PLL_VCO_RST BIT(29) #define TH1520_PLL_DSMPD BIT(24) #define TH1520_PLL_FRAC GENMASK(23, 0) #define TH1520_PLL_FRAC_BITS 24 @@ -242,6 +243,30 @@ static const struct clk_ops ccu_div_ops =3D { .determine_rate =3D clk_hw_determine_rate_no_reparent, }; =20 +static void ccu_pll_disable(struct clk_hw *hw) +{ + struct ccu_pll *pll =3D hw_to_ccu_pll(hw); + + regmap_set_bits(pll->common.map, pll->common.cfg1, + TH1520_PLL_VCO_RST); +} + +static int ccu_pll_enable(struct clk_hw *hw) +{ + struct ccu_pll *pll =3D hw_to_ccu_pll(hw); + + return regmap_clear_bits(pll->common.map, pll->common.cfg1, + TH1520_PLL_VCO_RST); +} + +static int ccu_pll_is_enabled(struct clk_hw *hw) +{ + struct ccu_pll *pll =3D hw_to_ccu_pll(hw); + + return !regmap_test_bits(pll->common.map, pll->common.cfg1, + TH1520_PLL_VCO_RST); +} + static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -299,6 +324,9 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw = *hw, } =20 static const struct clk_ops clk_pll_ops =3D { + .disable =3D ccu_pll_disable, + .enable =3D ccu_pll_enable, + .is_enabled =3D ccu_pll_is_enabled, .recalc_rate =3D ccu_pll_recalc_rate, }; =20 @@ -314,7 +342,7 @@ static struct ccu_pll cpu_pll0_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("cpu-pll0", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -326,7 +354,7 @@ static struct ccu_pll cpu_pll1_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("cpu-pll1", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -338,7 +366,7 @@ static struct ccu_pll gmac_pll_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("gmac-pll", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -358,7 +386,7 @@ static struct ccu_pll video_pll_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("video-pll", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -410,7 +438,7 @@ static struct ccu_pll tee_pll_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("tee-pll", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 --=20 2.50.1 From nobody Sat Oct 4 22:37:55 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 594882C21CA; Tue, 12 Aug 2025 05:43:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" The DPU pixel clock rate corresponds to the required dot clock of the display mode, so it needs to be tweakable. Add support to change it, by adding generic divider setting code, arming the code to the dpu0/dpu1 clocks, and setting the pixel clock connected to the DPU (after a gate) to CLK_SET_RATE_PARENT to propagate it to the dividers. Signed-off-by: Icenowy Zheng --- drivers/clk/thead/clk-th1520-ap.c | 87 +++++++++++++++++++++++++++++-- 1 file changed, 82 insertions(+), 5 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index 2f87c7c2c3baf..3e81f3051cd6c 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -55,6 +55,7 @@ struct ccu_gate { =20 struct ccu_div { u32 enable; + u32 div_en; struct ccu_div_internal div; struct ccu_internal mux; struct ccu_common common; @@ -198,6 +199,78 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw= *hw, return rate; } =20 +static long ccu_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + unsigned int val; + + if (!cd->div_en) { + regmap_read(cd->common.map, cd->common.cfg0, &val); + val =3D val >> cd->div.shift; + val &=3D GENMASK(cd->div.width - 1, 0); + return divider_ro_round_rate(hw, rate, parent_rate, + NULL, cd->div.width, cd->div.flags, + val); + } else { + return divider_round_rate(hw, rate, parent_rate, + NULL, cd->div.width, cd->div.flags); + } +} + +static int ccu_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + unsigned int val; + + if (!cd->div_en) { + regmap_read(cd->common.map, cd->common.cfg0, &val); + val =3D val >> cd->div.shift; + val &=3D GENMASK(cd->div.width - 1, 0); + return divider_ro_determine_rate(hw, req, NULL, + cd->div.width, + cd->div.flags, + val); + } else { + return divider_determine_rate(hw, req, NULL, + cd->div.width, cd->div.flags); + } +} + +static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + int val =3D divider_get_val(rate, parent_rate, NULL, + cd->div.width, cd->div.flags); + unsigned int curr_val, reg_val; + + if (val < 0) + return val; + + regmap_read(cd->common.map, cd->common.cfg0, ®_val); + curr_val =3D reg_val; + curr_val =3D curr_val >> cd->div.shift; + curr_val &=3D GENMASK(cd->div.width - 1, 0); + + if (!cd->div_en && curr_val !=3D val) + return -EINVAL; + + reg_val &=3D ~cd->div_en; + regmap_write(cd->common.map, cd->common.cfg0, reg_val); + udelay(1); + + reg_val &=3D ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift); + reg_val |=3D val << cd->div.shift; + regmap_write(cd->common.map, cd->common.cfg0, reg_val); + + reg_val |=3D cd->div_en; + regmap_write(cd->common.map, cd->common.cfg0, reg_val); + + return 0; +} + static u8 ccu_div_get_parent(struct clk_hw *hw) { struct ccu_div *cd =3D hw_to_ccu_div(hw); @@ -240,7 +313,9 @@ static const struct clk_ops ccu_div_ops =3D { .get_parent =3D ccu_div_get_parent, .set_parent =3D ccu_div_set_parent, .recalc_rate =3D ccu_div_recalc_rate, - .determine_rate =3D clk_hw_determine_rate_no_reparent, + .round_rate =3D ccu_div_round_rate, + .set_rate =3D ccu_div_set_rate, + .determine_rate =3D ccu_div_determine_rate, }; =20 static void ccu_pll_disable(struct clk_hw *hw) @@ -784,6 +859,7 @@ static struct ccu_div venc_clk =3D { }; =20 static struct ccu_div dpu0_clk =3D { + .div_en =3D BIT(8), .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), .common =3D { .clkid =3D CLK_DPU0, @@ -791,7 +867,7 @@ static struct ccu_div dpu0_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("dpu0", dpu0_pll_clk_parent, &ccu_div_ops, - 0), + CLK_SET_RATE_UNGATE), }, }; =20 @@ -800,6 +876,7 @@ static const struct clk_parent_data dpu0_clk_pd[] =3D { }; =20 static struct ccu_div dpu1_clk =3D { + .div_en =3D BIT(8), .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), .common =3D { .clkid =3D CLK_DPU1, @@ -807,7 +884,7 @@ static struct ccu_div dpu1_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("dpu1", dpu1_pll_clk_parent, &ccu_div_ops, - 0), + CLK_SET_RATE_UNGATE), }, }; =20 @@ -891,9 +968,9 @@ static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-c= lk", video_pll_clk_pd, static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", video_pll_clk_pd, 0x0, BIT(4), 0); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", - dpu0_clk_pd, 0x0, BIT(5), 0); + dpu0_clk_pd, 0x0, BIT(5), CLK_SET_RATE_PARENT); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", - dpu1_clk_pd, 0x0, BIT(6), 0); + dpu1_clk_pd, 0x0, BIT(6), CLK_SET_RATE_PARENT); static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0, BIT(7), 0); static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0, --=20 2.50.1 From nobody Sat Oct 4 22:37:55 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C35E51A5BB1; Tue, 12 Aug 2025 05:44:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754977475; cv=pass; b=F0C4VOGeqeQHYNDh4HPjwBrEB7ydrd75qTgwsFtvlk2NEepoOMpq2tVu7QhGxRiq9tqvRq0+Ofug/VYKirpEQFbBsoD8bJWcxZyqTeCHocgpjeGywEwtxY6vC6SLwG0TBwf5+sT+Plf6Wkeyv12KCkI6n/o6DX6XwDpKT/QVrbU= ARC-Message-Signature: i=2; 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charset="utf-8" The AXI crossbar of TH1520 has no proper timeout handling, which means gating AXI clocks can easily lead to bus timeout and thus system hang. Set all AXI clock gates to CLK_IS_CRITICAL. All these clock gates are ungated by default on system reset. In addition, convert all current CLK_IGNORE_UNUSED usage to CLK_IS_CRITICAL to prevent unwanted clock gating. Signed-off-by: Icenowy Zheng --- drivers/clk/thead/clk-th1520-ap.c | 42 ++++++++++++++++--------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index 3e81f3051cd6c..0117e5ea1bf58 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -589,7 +589,7 @@ static struct ccu_div axi4_cpusys2_aclk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("axi4-cpusys2-aclk", gmac_pll_clk_parent, &ccu_div_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -611,7 +611,7 @@ static struct ccu_div axi_aclk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("axi-aclk", axi_parents, &ccu_div_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -760,7 +760,7 @@ static struct ccu_div apb_pclk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("apb-pclk", apb_parents, &ccu_div_ops, - CLK_IGNORE_UNUSED), + CLK_IS_CRITICAL), }, }; =20 @@ -791,7 +791,7 @@ static struct ccu_div vi_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("vi", video_pll_clk_parent, &ccu_div_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -816,7 +816,7 @@ static struct ccu_div vo_axi_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("vo-axi", video_pll_clk_parent, &ccu_div_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -841,7 +841,7 @@ static struct ccu_div vp_axi_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("vp-axi", video_pll_clk_parent, &ccu_div_ops, - CLK_IGNORE_UNUSED), + CLK_IS_CRITICAL), }, }; =20 @@ -902,23 +902,25 @@ static const struct clk_parent_data emmc_sdio_ref_clk= _pd[] =3D { static CCU_GATE(CLK_BROM, brom_clk, "brom", ahb2_cpusys_hclk_pd, 0x100, BI= T(4), 0); static CCU_GATE(CLK_BMU, bmu_clk, "bmu", axi4_cpusys2_aclk_pd, 0x100, BIT(= 5), 0); static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpus= ys2_aclk_pd, - 0x134, BIT(8), 0); + 0x134, BIT(8), CLK_IS_CRITICAL); static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2= _aclk_pd, - 0x134, BIT(7), 0); + 0x134, BIT(7), CLK_IS_CRITICAL); static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_= pd, - 0x138, BIT(8), CLK_IGNORE_UNUSED); + 0x138, BIT(8), CLK_IS_CRITICAL); static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_c= pusys2_aclk_pd, - 0x140, BIT(9), CLK_IGNORE_UNUSED); + 0x140, BIT(9), CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hc= lk", perisys_ahb_hclk_pd, - 0x150, BIT(9), CLK_IGNORE_UNUSED); + 0x150, BIT(9), CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hc= lk", perisys_ahb_hclk_pd, - 0x150, BIT(10), CLK_IGNORE_UNUSED); + 0x150, BIT(10), CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hc= lk", perisys_ahb_hclk_pd, - 0x150, BIT(11), CLK_IGNORE_UNUSED); + 0x150, BIT(11), CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hc= lk", perisys_ahb_hclk_pd, 0x150, BIT(12), 0); static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, B= IT(5), 0); static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, BIT(= 13), 0); +static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, B= IT(5), CLK_IS_CRITICAL); +static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, BIT(= 13), CLK_IS_CRITICAL); static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", emmc_sdio_ref_c= lk_pd, 0x204, BIT(30), 0); static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd, 0x204, BIT= (26), 0); static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", perisys_apb_pclk_p= d, 0x204, BIT(24), 0); @@ -962,11 +964,11 @@ static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_ac= lk_pd, 0x20c, BIT(2), 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1),= 0); =20 static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", - video_pll_clk_pd, 0x0, BIT(0), 0); + video_pll_clk_pd, 0x0, BIT(0), CLK_IS_CRITICAL); static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_= pd, 0x0, BIT(3), 0); static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", - video_pll_clk_pd, 0x0, BIT(4), 0); + video_pll_clk_pd, 0x0, BIT(4), CLK_IS_CRITICAL); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", dpu0_clk_pd, 0x0, BIT(5), CLK_SET_RATE_PARENT); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", @@ -998,9 +1000,9 @@ static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk= , "mipi-dsi1-refclk", static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk", video_pll_clk_= pd, 0x0, BIT(19), 0); static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk", - video_pll_clk_pd, 0x0, BIT(20), 0); + video_pll_clk_pd, 0x0, BIT(20), CLK_IS_CRITICAL); static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk", - video_pll_clk_pd, 0x0, BIT(21), 0); + video_pll_clk_pd, 0x0, BIT(21), CLK_IS_CRITICAL); static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk", video_pll_clk_pd, 0x0, BIT(22), 0); static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk, @@ -1010,11 +1012,11 @@ static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vo= sys_dpu1_pclk, static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk, "iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, BIT(25), 0); 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charset="utf-8" The padctrl0 clock seems to be a child of the perisys_apb4_hclk clock, gating the later makes padctrl0 registers stuck. Fix this relationship. Signed-off-by: Icenowy Zheng --- drivers/clk/thead/clk-th1520-ap.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index 0117e5ea1bf58..19f6b0285390d 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -917,6 +917,11 @@ static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hc= lk, "perisys-apb3-hclk", p 0x150, BIT(11), CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hc= lk", perisys_ahb_hclk_pd, 0x150, BIT(12), 0); + +static const struct clk_parent_data perisys_apb4_hclk_pd[] =3D { + { .hw =3D &perisys_apb4_hclk.common.hw }, +}; + static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, B= IT(5), 0); static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, BIT(= 13), 0); static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, B= IT(5), CLK_IS_CRITICAL); @@ -925,7 +930,7 @@ static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdi= o", emmc_sdio_ref_clk_pd, static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd, 0x204, BIT= (26), 0); static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", perisys_apb_pclk_p= d, 0x204, BIT(24), 0); static CCU_GATE(CLK_DSMART, dsmart_clk, "dsmart", perisys_apb_pclk_pd, 0x2= 04, BIT(23), 0); -static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", perisys_apb_pclk_p= d, 0x204, BIT(22), 0); +static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", perisys_apb4_hclk_= pd, 0x204, BIT(22), 0); static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", axi4_cpusys2_aclk_= pd, 0x204, BIT(21), 0); static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", peri2sys_apb_pclk_pd, 0= x204, BIT(20), 0); static CCU_GATE(CLK_GMAC0, gmac0_clk, "gmac0", gmac_pll_clk_pd, 0x204, BIT= (19), 0); --=20 2.50.1