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Introduce a handshake loop to ensure MNoC enters low power mode reliably during VPU3 hardware power-off with timeout handling. Signed-off-by: Dikshita Agarwal Tested-by: Neil Armstrong # on SM8650-HDK --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 9b7c9a1495ee2f51c60b1142b2ed4680ff798f0a..c2e6af575cbe4b3e3f2a019b24e= ecf3a5d469566 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -110,6 +110,7 @@ static void iris_vpu3_power_off_hardware(struct iris_co= re *core) static void iris_vpu33_power_off_hardware(struct iris_core *core) { u32 reg_val =3D 0, value, i; + u32 count =3D 0; int ret; =20 if (iris_vpu3x_hw_power_collapsed(core)) @@ -128,13 +129,31 @@ static void iris_vpu33_power_off_hardware(struct iris= _core *core) goto disable_power; } =20 + /* set MNoC to low power */ + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONT= ROL); + + value =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); + + while (!(value & BIT(0)) && (value & BIT(2) || value & BIT(1))) { + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + usleep_range(10, 20); + + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CON= TROL); + + value =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); + if (++count >=3D 1000) { + dev_err(core->dev, "LPI handshake timeout\n"); + break; + } + } + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, reg_val, reg_val & BIT(0), 200, 2000); if (ret) goto disable_power; =20 - /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ - writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); =20 writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); --- base-commit: d968e50b5c26642754492dea23cbd3592bde62d8 change-id: 20250812-sm8650-power-sequence-fix-ba9a92098233 Best regards, --=20 Dikshita Agarwal