From nobody Sat Oct 4 21:02:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20E3128000A; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755003641; cv=none; b=TtKpZsKGpggBfRLTQ9MsMjXyMSSkvVdzNklz2LqkL3JEOH0xk8NNGMQxWDbfjyyf4FO40xudnRq88fLf71VjZ/v0eEXOKCsHj2bzdXrwn85a15u0ksYDf/Ue1jpVmexLWTmzx0twt2ppcxDcLutzhSAP8dCjDGWZ65979KfvIek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755003641; c=relaxed/simple; bh=CLMpKrTrD+1F6YeWwuDcqlirxHopHnUHK3PKeL3Qewc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=olFLDZ8tzrOiJj9e9cyjNNG+bQxWM0qVTCW4KNa0YUL8Mhb0lqfruLBWMVTuTqKFpt/6XNr9bLnwyY06umOu+MF0HDzxSHmQzDgVkuX7JbQxgM9bKjbZu64PZ2W2sQCxaQ584UDOrEcc9K3Nv7YIuVs3r2j0Wa3A8vl/XF8wh9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=W2nsH1WC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="W2nsH1WC" Received: by smtp.kernel.org (Postfix) with ESMTPS id B1642C4CEF5; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755003640; bh=CLMpKrTrD+1F6YeWwuDcqlirxHopHnUHK3PKeL3Qewc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=W2nsH1WCoOPpcG6BwZm4jJN+VcO6lsXEhCDY4IoKaxTkhXHXelTVNMmBaqwmBgEFT ZBpr8HxnNtK9G9qUIFAls4ode9JvMX9bXewdlEk3d08VFxhi/gRB+P0ZlQF2Ff5q7k mnhA9PHO4umklFRo/vbWR1YmdY3EVbo+GsdYT7eP9DUGD7liFKctuIRPoJoy1m/x24 MwU0tkufJEDuWOitKVPXMzJnxZe/VLQ2oojPOkDeAUyoWO/2gN5eRURvzotzrcjTvK BlCfAqwKpTsLFuMuOF8COZSUSyCb9W3AAf0+cB7f2+vH+WUiz6Q5JMbGrO3rC8VKXm mpvGZrta68aRg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A48F3C87FCB; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) From: Mahesh Rao via B4 Relay Date: Tue, 12 Aug 2025 20:59:24 +0800 Subject: [PATCH RESEND v2 1/4] dt-bindings: firmware: Add interrupt specification for Intel Stratix 10 Service Layer. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-sip_svc_irq-v2-1-53098e11705a@altera.com> References: <20250812-sip_svc_irq-v2-0-53098e11705a@altera.com> In-Reply-To: <20250812-sip_svc_irq-v2-0-53098e11705a@altera.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755003637; l=1851; i=mahesh.rao@altera.com; s=20250107; h=from:subject:message-id; bh=AOemBCgdL+N65O4/Not6GZwfFLWHmbGOTOms8z2w2Jo=; b=8S0XDud7rGHq5nBFQ8JWiz7ndCiGBA16NH2g3aA2nzxZLjooQTJ6gmSdIAd+o++rn8nS4hQGw eaxZtK7NPAYDdJu+vNaAqdulhgQA/H6DRbYbMKyjmD7jk6oaMVER+3d X-Developer-Key: i=mahesh.rao@altera.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= X-Endpoint-Received: by B4 Relay for mahesh.rao@altera.com/20250107 with auth_id=337 X-Original-From: Mahesh Rao Reply-To: mahesh.rao@altera.com From: Mahesh Rao Add interrupt specification for Intel Stratix10 Service layer for asynchronous communication. Reviewed-by: Matthew Gerlach Reviewed-by: Rob Herring (Arm) Signed-off-by: Mahesh Rao --- .../devicetree/bindings/firmware/intel,stratix10-svc.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc= .yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml index fac1e955852e4f9b966c991dcfac56222c5f7315..656cc50fd08217f270f95ae3901= 0152423315ed1 100644 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml @@ -54,6 +54,12 @@ properties: reserved memory region for the service layer driver to communicate with the secure device manager. =20 + interrupts: + maxItems: 1 + description: + This interrupt is used by the Secure Device Manager (SDM) to signal + completion of an asynchronous operation to service layer driver. + fpga-mgr: $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml description: Optional child node for fpga manager to perform fabric co= nfiguration. @@ -67,6 +73,8 @@ additionalProperties: false =20 examples: - | + #include + reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; @@ -84,6 +92,8 @@ examples: compatible =3D "intel,stratix10-svc"; method =3D "smc"; memory-region =3D <&service_reserved>; + interrupts =3D ; + interrupt-parent =3D <&intc0>; =20 fpga-mgr { compatible =3D "intel,stratix10-soc-fpga-mgr"; --=20 2.35.3 From nobody Sat Oct 4 21:02:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A1E3280024; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755003641; cv=none; b=s+kMXnhUPc9NIRS7tCQ0C/847AH2+jpK9lpUJRrF5kaEdiX+/dpZ5nLtVBYd+bjFH6ei0mzm0+6WK7fpKrEzyTM2hVmXm1R2RMJoIhCB0v7MtvvSv1JI3bAmBoSdNX86NN8OtHCBP+GzETu+isXIANbDUIeHHjCM55e6/9dWFgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755003641; c=relaxed/simple; bh=zYGMtM8fuI4HHjVC9uIuljEjH+ZKKu6iq7sDJh5FxKw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RF9Xn9ys7rEICWWzF/JgyjgN02Bgqn+7Hr0oIbdmAUQF9VXjkKi0gp3r8uIB3G5uiEzczt6rtOeQ+fgxVNDx9JkREy9+sqn26Nc6G5Kqw6xArDG7WKirplorTUy2EtH0NCxpzmuqVy39fC7G61XIgIPORjFcLnqf5qpgqx+9R7o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OCARbBi5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OCARbBi5" Received: by smtp.kernel.org (Postfix) with ESMTPS id C54B9C4CEF8; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755003640; bh=zYGMtM8fuI4HHjVC9uIuljEjH+ZKKu6iq7sDJh5FxKw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OCARbBi5fDhVrI5gh48ZwbcyJPTmd7ZYq6ACUYR6eRo50RRcsnYWn0OKCVUFMYgQe lI3i/LBennckxP2h5Q6s+dZvpT1uArqFGGlqFSqjsgiOdcd0leiTbk1PTjoAcpCfIn WkzWOv54Hherjw58iVOmlsMd0N6DiQTydA/D6ao579TFkmrXPAB+cIRaJV4xEuYh8o as74LtbmgH8FcjW807rLFa7OyMC+WAaf3l4zXE3vZ96avRvvYq3z5rQJJVrbej8VdZ zpYYV9AXOi+iGt7E/61dUmQozlL78V0Dc6AAvht4CQQ1exkeUxF7pLRX4a0MHQbaxx Omxjmvngh9Dmw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3AE4CA0EDB; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) From: Mahesh Rao via B4 Relay Date: Tue, 12 Aug 2025 20:59:25 +0800 Subject: [PATCH RESEND v2 2/4] dts: stratix10: Add support for SDM mailbox interrupt for Intel Stratix10 SoC FPGA. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-sip_svc_irq-v2-2-53098e11705a@altera.com> References: <20250812-sip_svc_irq-v2-0-53098e11705a@altera.com> In-Reply-To: <20250812-sip_svc_irq-v2-0-53098e11705a@altera.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755003637; l=1326; i=mahesh.rao@altera.com; s=20250107; h=from:subject:message-id; bh=3ob8k9A6zIADp0lruGxd1g5augXf3tZBlKtdVmhWZZI=; b=QDmzUwun/xgQqFFN4+DuH+uiOuoF/QBmwrB90Uyrqg31EOzLm47xWbWs1AquzPkOhYYYBlrb+ Do7ujBn5v7oC7qYfktIzQV2w4CYgPU7Xt5Huxw3qs5BbgYHOb1c9pXE X-Developer-Key: i=mahesh.rao@altera.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= X-Endpoint-Received: by B4 Relay for mahesh.rao@altera.com/20250107 with auth_id=337 X-Original-From: Mahesh Rao Reply-To: mahesh.rao@altera.com From: Mahesh Rao Add support for Secure Device Manager (SDM) mailbox doorbell interrupt on Stratix10 SoC FPGA for supporting asynchronous transactions. Signed-off-by: Mahesh Rao --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64= /boot/dts/altera/socfpga_stratix10.dtsi index effd242f6bf709a53659b4de2a2da728052d086f..9e8b3b07dde3ff57382044f528c= 34bd52f8df123 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -1,11 +1,13 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright Altera Corporation (C) 2015. All rights reserved. + * Copyright (C) 2025, Altera Corporation */ =20 /dts-v1/; #include #include +#include #include =20 / { @@ -74,6 +76,8 @@ svc { compatible =3D "intel,stratix10-svc"; method =3D "smc"; memory-region =3D <&service_reserved>; + interrupts =3D ; + interrupt-parent =3D <&intc>; =20 fpga_mgr: fpga-mgr { compatible =3D "intel,stratix10-soc-fpga-mgr"; --=20 2.35.3 From nobody Sat Oct 4 21:02:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A10328000B; Tue, 12 Aug 2025 13:00:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755003641; cv=none; b=f7wRZdOhZzORf+Sj0USgEh5LLgqC1En0v+/JMOjF6Fb5eCFUAG3WZUy1gOOjM+WjiH90M3a95v1q32fhJw14SuBzOI4AIt6cVvJlmaDSwgf2SnVJFtCytXudFqoDyMSyV01CNOzpgDxzmLvcIJD+6CA608k12XWyhnnatyA92Go= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755003641; c=relaxed/simple; bh=qEfGEH6TN3t5lb3uqMXrBy+umm7qijcK9imic70APas=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mfquWkhv9zIQTz1lvk9bvXShUlWtbQUGu2o03lih1DYZZFfJXjD+pR3XgA9IeV98N6Dqs/U0zbsXtxxxj2283jznyFmgPxNBUKt3/z6U3YQ/fVP6q85gisbqWLP0OPRwSVaJ86zozI2VKSyGld+6M+/ZtQyFu92mTY6b73zAqQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U4PmvtAS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U4PmvtAS" Received: by smtp.kernel.org (Postfix) with ESMTPS id CD333C4CEF6; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755003640; bh=qEfGEH6TN3t5lb3uqMXrBy+umm7qijcK9imic70APas=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=U4PmvtASICJxX96G89lxOIizL4ltkh6K7NI0K40PBCWby+fHmCmY8SrModbDYrNV7 o6mKq/O56/liJPYlcNi7CyTu/znLGZ4RoM2RjNdFPyGCbhiWufuKHWu6oZrtXRY3Xg ybcdzPXym35aLIJdWQHYrEtDDmvGtQBk+pycVU51MuAsZ5rPuWkZ6PjmIJ496J0Pev nqHKARX94qZnws34SbXegDX60oBnDMpzoHjW0AT2YWftU1v5JxugZQEOG26nivXDYk ZfNEY24jomAgv/sXVnXADM/xTxjGTJEpLQ66c/UyCzYDnV8qllaxJ1Xu5righAbITQ dmQblDlxwozrg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3D41CA0EC4; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) From: Mahesh Rao via B4 Relay Date: Tue, 12 Aug 2025 20:59:26 +0800 Subject: [PATCH RESEND v2 3/4] dts: agilex: Add support for SDM mailbox interrupt for Intel Agilex SoC FPGA. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-sip_svc_irq-v2-3-53098e11705a@altera.com> References: <20250812-sip_svc_irq-v2-0-53098e11705a@altera.com> In-Reply-To: <20250812-sip_svc_irq-v2-0-53098e11705a@altera.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755003637; l=956; i=mahesh.rao@altera.com; s=20250107; h=from:subject:message-id; bh=kTWn6GvwTe/xGzLhUbTFDEIXbzJ45fZ902gWQA8lOkM=; b=e5LrUNd0bULmIlviqmFxaoO/8SP95VX4DsDCBH3fqKIB6Dur2nzJiKnCGldefsvimolevV7YQ 55Mb+Vi4SqkCQOPlrkPd75kz6MYl1eXd2f+qz4Opm56QdHlZlRO+TL+ X-Developer-Key: i=mahesh.rao@altera.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= X-Endpoint-Received: by B4 Relay for mahesh.rao@altera.com/20250107 with auth_id=337 X-Original-From: Mahesh Rao Reply-To: mahesh.rao@altera.com From: Mahesh Rao Add support for Secure Device Manager (SDM) mailbox doorbell interrupt on Agilex SoC FPGA for supporting asynchronous transactions. Signed-off-by: Mahesh Rao Reviewed-by: Matthew Gerlach --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boo= t/dts/intel/socfpga_agilex.dtsi index c1e66db0f4c524809d4334b86ef741f834a9b896..c3c72e8c1c10fcff818dcc934a3= 6e2ffaa0bd347 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -65,6 +65,8 @@ svc { compatible =3D "intel,agilex-svc"; method =3D "smc"; memory-region =3D <&service_reserved>; + interrupts =3D ; + interrupt-parent =3D <&intc>; =20 fpga_mgr: fpga-mgr { compatible =3D "intel,agilex-soc-fpga-mgr"; --=20 2.35.3 From nobody Sat Oct 4 21:02:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A24D280037; Tue, 12 Aug 2025 13:00:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755003641; cv=none; b=IzdaRrfaMZ/OHSeR7OyM6aquM7ugaZeTxi95xZ3L+p/E3IDBXFo0/Zq+108+0fCppQPZNk9cU7vWTUfKzgJbA+y/8GOQFRlQ+q9BsIE0lTJRW3mTU0CrxrHuMWbKqt9ZZ8aiL12iBb0fEQsPcJFLd3f4IZ488zSowaLshfhhLqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755003641; c=relaxed/simple; bh=GD+CuAWLXSm+fQaLF9A5X/6cvNCIJxhOBEqUK57Iydg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LlMSWy9/mMIXc1CNiCgJdMxRL4WhRojWsO0PwZ5e99W3mWLtGVgUfz2h1DdxVM329v3DHFRgOd5k/hLD2RxbpQ3ah7GRcopwA5MKSW5l2x72e6RqfR/b6YVRclmoWaiJtqfP2cmwyGMt8XMdfhWeMSInjRM4b8p93cCpV/J4QXc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cJpA2q5a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cJpA2q5a" Received: by smtp.kernel.org (Postfix) with ESMTPS id DB357C4CEF9; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755003640; bh=GD+CuAWLXSm+fQaLF9A5X/6cvNCIJxhOBEqUK57Iydg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cJpA2q5abMNY7V4igk9IrRnHcwZ42EubI4pikkXyBgOQQTXCffmy7jjbF7ce4+NZe lJStoQ5oofYvwmNibHLDtIayOM6cwOan6fmZQOmR1Eloc8zSmEJJYVChCrgGpT4y9c g1oQuZeUYktP5uOmZaWERlVOdmtSrkgrGlC95aH5NRdy0FWdi8eSripcETaYc1W+mM tefZ5SM6IKt8EoJjawiiQrkUHV8Eg+XOUjNkBJtLE3bqzqi8obe9rQrkgpNBqHRano G+GUmo8Ad1m+6KL4QaYA2cM8kJmiDI+/dEM7sCmcJX6DttRSJR6CeuRDaKw0mrQM93 NCSs8mK+ZzH9w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D12ABCA0EDA; Tue, 12 Aug 2025 13:00:40 +0000 (UTC) From: Mahesh Rao via B4 Relay Date: Tue, 12 Aug 2025 20:59:27 +0800 Subject: [PATCH RESEND v2 4/4] firmware: stratix10-svc: Add for SDM mailbox doorbell interrupt Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-sip_svc_irq-v2-4-53098e11705a@altera.com> References: <20250812-sip_svc_irq-v2-0-53098e11705a@altera.com> In-Reply-To: <20250812-sip_svc_irq-v2-0-53098e11705a@altera.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755003637; l=10436; i=mahesh.rao@altera.com; s=20250107; h=from:subject:message-id; bh=kD1dKAGC5+KV8f19LP5klFEJsJBn+SrRu6Htg7n4yPU=; b=DCHlQCv75XfDCh3+VbjOmsktyBbO4f41HSorqTr413sQ4+L1E+SSepmMMAQwea4RIQjZ8YogT VWXbETl3a6DDbPgC3BzTLjj0Ush9283wEykOB9tTfLcDjHwVEY2e7Cc X-Developer-Key: i=mahesh.rao@altera.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= X-Endpoint-Received: by B4 Relay for mahesh.rao@altera.com/20250107 with auth_id=337 X-Original-From: Mahesh Rao Reply-To: mahesh.rao@altera.com From: Mahesh Rao Add support for SDM (Secure Device Manager) mailbox doorbell interrupt for async transactions. On interrupt, a workqueue is triggered which polls the ATF for pending responses and retrieves the bitmap of all retrieved and unprocessed transaction ids of mailbox responses from SDM. It then triggers the corresponding registered callbacks. Signed-off-by: Mahesh Rao Reviewed-by: Matthew Gerlach --- drivers/firmware/stratix10-svc.c | 117 +++++++++++++++++++++++= +--- include/linux/firmware/intel/stratix10-smc.h | 23 ++++++ 2 files changed, 130 insertions(+), 10 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-= svc.c index 491a8149033f975d515444f025723658c51aa1fe..a65c64c1be61d9f1fd27114d7f3= 0d7a759e8201e 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -9,12 +9,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -22,6 +24,7 @@ #include #include #include +#include =20 /** * SVC_NUM_DATA_IN_FIFO - number of struct stratix10_svc_data in the FIFO @@ -213,6 +216,7 @@ struct stratix10_async_chan { * asynchronous operations * @initialized: Flag indicating whether the control structure has * been initialized + * @irq: Interrupt request number associated with the asynchronous control * @invoke_fn: Function pointer for invoking Stratix10 service calls * to EL3 secure firmware * @async_id_pool: Pointer to the ID pool used for asynchronous @@ -223,11 +227,13 @@ struct stratix10_async_chan { * structure * @trx_list_wr_lock: Spinlock for protecting the transaction list * write operations + * @async_work: Work structure for scheduling asynchronous work * @trx_list: Hash table for managing asynchronous transactions */ =20 struct stratix10_async_ctrl { bool initialized; + int irq; void (*invoke_fn)(struct stratix10_async_ctrl *actrl, const struct arm_smccc_1_2_regs *args, struct arm_smccc_1_2_regs *res); @@ -236,6 +242,7 @@ struct stratix10_async_ctrl { struct stratix10_async_chan *common_async_chan; /* spinlock to protect the writes to trx_list hash table */ spinlock_t trx_list_wr_lock; + struct work_struct async_work; DECLARE_HASHTABLE(trx_list, ASYNC_TRX_HASH_BITS); }; =20 @@ -1709,14 +1716,81 @@ static inline void stratix10_smc_1_2(struct stratix= 10_async_ctrl *actrl, arm_smccc_1_2_smc(args, res); } =20 +static irqreturn_t stratix10_svc_async_irq_handler(int irq, void *dev_id) +{ + struct stratix10_svc_controller *ctrl =3D dev_id; + struct stratix10_async_ctrl *actrl =3D &ctrl->actrl; + + queue_work(system_bh_wq, &actrl->async_work); + disable_irq_nosync(actrl->irq); + return IRQ_HANDLED; +} +/** + * stratix10_async_workqueue_handler - Handler for the asynchronous + * workqueue in Stratix10 service controller. + * @work: Pointer to the work structure that contains the asynchronous + * workqueue handler. + * This function is the handler for the asynchronous workqueue. It performs + * the following tasks: + * - Invokes the asynchronous polling on interrupt supervisory call. + * - On success,it retrieves the bitmap of pending transactions from mailb= ox + * fifo in ATF. + * - It processes each pending transaction by calling the corresponding + * callback function. + * + * The function ensures that the IRQ is enabled after processing the trans= actions + * and logs the total time taken to handle the transactions along with the= number + * of transactions handled and the CPU on which the handler ran. + */ +static void stratix10_async_workqueue_handler(struct work_struct *work) +{ + struct stratix10_async_ctrl *actrl =3D + container_of(work, struct stratix10_async_ctrl, async_work); + struct arm_smccc_1_2_regs + args =3D { .a0 =3D INTEL_SIP_SMC_ASYNC_POLL_ON_IRQ }, res; + DECLARE_BITMAP(pend_on_irq, TOTAL_TRANSACTION_IDS); + struct stratix10_svc_async_handler *handler; + unsigned long transaction_id =3D 0; + u64 bitmap_array[4]; + + actrl->invoke_fn(actrl, &args, &res); + if (res.a0 =3D=3D INTEL_SIP_SMC_STATUS_OK) { + bitmap_array[0] =3D res.a1; + bitmap_array[1] =3D res.a2; + bitmap_array[2] =3D res.a3; + bitmap_array[3] =3D res.a4; + bitmap_from_arr64(pend_on_irq, bitmap_array, TOTAL_TRANSACTION_IDS); + rcu_read_lock(); + do { + transaction_id =3D find_next_bit(pend_on_irq, + TOTAL_TRANSACTION_IDS, + transaction_id); + if (transaction_id >=3D TOTAL_TRANSACTION_IDS) + break; + hash_for_each_possible_rcu_notrace(actrl->trx_list, + handler, next, + transaction_id) { + if (handler->transaction_id =3D=3D transaction_id) { + handler->cb(handler->cb_arg); + break; + } + } + transaction_id++; + } while (transaction_id < TOTAL_TRANSACTION_IDS); + rcu_read_unlock(); + } + enable_irq(actrl->irq); +} + /** * stratix10_svc_async_init - Initialize the Stratix10 service * controller for asynchronous operations. * @controller: Pointer to the Stratix10 service controller structure. * * This function initializes the asynchronous service controller by - * setting up the necessary data structures and initializing the - * transaction list. + * setting up the necessary data structures ,initializing the + * transaction list and registering the IRQ handler for asynchronous + * transactions. * * Return: 0 on success, -EINVAL if the controller is NULL or already * initialized, -ENOMEM if memory allocation fails, @@ -1728,7 +1802,7 @@ static int stratix10_svc_async_init(struct stratix10_= svc_controller *controller) struct stratix10_async_ctrl *actrl; struct arm_smccc_res res; struct device *dev; - int ret; + int ret, irq; =20 if (!controller) return -EINVAL; @@ -1775,6 +1849,22 @@ static int stratix10_svc_async_init(struct stratix10= _svc_controller *controller) hash_init(actrl->trx_list); atomic_set(&actrl->common_achan_refcount, 0); =20 + irq =3D of_irq_get(dev_of_node(dev), 0); + if (irq < 0) { + dev_warn(dev, "Failed to get IRQ, falling back to polling mode\n"); + } else { + ret =3D devm_request_any_context_irq(dev, irq, stratix10_svc_async_irq_h= andler, + IRQF_NO_AUTOEN, "stratix10_svc", controller); + if (ret =3D=3D 0) { + dev_alert(dev, + "Registered IRQ %d for sip async operations\n", + irq); + actrl->irq =3D irq; + INIT_WORK(&actrl->async_work, stratix10_async_workqueue_handler); + enable_irq(actrl->irq); + } + } + actrl->initialized =3D true; return 0; } @@ -1784,13 +1874,14 @@ static int stratix10_svc_async_init(struct stratix1= 0_svc_controller *controller) * service controller * @ctrl: Pointer to the stratix10_svc_controller structure * - * This function performs the necessary cleanup for the asynchronous - * service controller. It checks if the controller is valid and if it - * has been initialized. It then locks the transaction list and safely - * removes and deallocates each handler in the list. The function also - * removes any asynchronous clients associated with the controller's - * channels and destroys the asynchronous ID pool. Finally, it resets - * the asynchronous ID pool and invoke function pointers to NULL. + * This function performs the necessary cleanup for the asynchronous servi= ce + * controller. It checks if the controller is valid and if it has been + * initialized. Also If the controller has an IRQ assigned, it frees the I= RQ + * and flushes any pending asynchronous work. It then locks the transaction + * list and safely removes and deallocates each handler in the list. + * The function also removes any asynchronous clients associated with the + * controller's channels and destroys the asynchronous ID pool. Finally, it + * resets the asynchronous ID pool and invoke function pointers to NULL. * * Return: 0 on success, -EINVAL if the controller is invalid or not * initialized. @@ -1812,6 +1903,12 @@ static int stratix10_svc_async_exit(struct stratix10= _svc_controller *ctrl) =20 actrl->initialized =3D false; =20 + if (actrl->irq > 0) { + free_irq(actrl->irq, ctrl); + flush_work(&actrl->async_work); + actrl->irq =3D 0; + } + spin_lock(&actrl->trx_list_wr_lock); hash_for_each_safe(actrl->trx_list, i, tmp, handler, next) { stratix10_deallocate_id(handler->achan->job_id_pool, diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/f= irmware/intel/stratix10-smc.h index f87273af5e284b8912d87eb9d7179eb3d43e40e1..45e9dd4211f4994d67e5a6e00a5= a817e96d42a8d 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -645,6 +645,29 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_= CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_ASYNC_POLL \ INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_POLL) =20 +/** + * Request INTEL_SIP_SMC_ASYNC_POLL_ON_IRQ + * Async call used by service driver at EL1 to read response from SDM + * mailbox and to retrieve the transaction id's of the read response's. + * + * Call register usage: + * a0 INTEL_SIP_SMC_ASYNC_POLL_ON_IRQ + * a1 transaction job id + * a2-7 will be used to return the response data + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK + * a1-a4 will contain bitmap of available responses's transaction id as set + * bit position. + * a5-17 not used + * Or + * a0 INTEL_SIP_SMC_STATUS_NO_RESPONSE + * a1-17 not used + */ +#define INTEL_SIP_SMC_ASYNC_FUNC_ID_IRQ_POLL (0xC9) +#define INTEL_SIP_SMC_ASYNC_POLL_ON_IRQ \ + INTEL_SIP_SMC_ASYNC_VAL(INTEL_SIP_SMC_ASYNC_FUNC_ID_IRQ_POLL) + /** * Request INTEL_SIP_SMC_ASYNC_RSU_GET_SPT * Async call to get RSU SPT from SDM. --=20 2.35.3