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To reflect this compatibility, update the binding schema to include qcom,sc7280-qmp-gen3x1-pcie-phy using enum within a oneOf block, while retaining qcom,sm8250-qmp-gen3x1-pcie-phy as a const. Signed-off-by: Krishna Chaitanya Chundru --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 69 ++++++++++++------= ---- 1 file changed, 37 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index a1ae8c7988c891a11f6872e58d25e9d04abb41ce..1e08e26892f7b769b75bb905377= d30a301e6631c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -15,38 +15,43 @@ description: =20 properties: compatible: - enum: - - qcom,qcs615-qmp-gen3x1-pcie-phy - - qcom,qcs8300-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x4-pcie-phy - - qcom,sar2130p-qmp-gen3x2-pcie-phy - - qcom,sc8180x-qmp-pcie-phy - - qcom,sc8280xp-qmp-gen3x1-pcie-phy - - qcom,sc8280xp-qmp-gen3x2-pcie-phy - - qcom,sc8280xp-qmp-gen3x4-pcie-phy - - qcom,sdm845-qhp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sdx65-qmp-gen4x2-pcie-phy - - qcom,sm8150-qmp-gen3x1-pcie-phy - - qcom,sm8150-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8350-qmp-gen3x1-pcie-phy - - qcom,sm8350-qmp-gen3x2-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - - qcom,sm8550-qmp-gen3x2-pcie-phy - - qcom,sm8550-qmp-gen4x2-pcie-phy - - qcom,sm8650-qmp-gen3x2-pcie-phy - - qcom,sm8650-qmp-gen4x2-pcie-phy - - qcom,x1e80100-qmp-gen3x2-pcie-phy - - qcom,x1e80100-qmp-gen4x2-pcie-phy - - qcom,x1e80100-qmp-gen4x4-pcie-phy - - qcom,x1e80100-qmp-gen4x8-pcie-phy - - qcom,x1p42100-qmp-gen4x4-pcie-phy + oneOf: + - items: + - const: qcom,sc7280-qmp-gen3x1-pcie-phy + - const: qcom,sm8250-qmp-gen3x1-pcie-phy + - items: + - enum: + - qcom,qcs615-qmp-gen3x1-pcie-phy + - qcom,qcs8300-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x4-pcie-phy + - qcom,sar2130p-qmp-gen3x2-pcie-phy + - qcom,sc8180x-qmp-pcie-phy + - qcom,sc8280xp-qmp-gen3x1-pcie-phy + - qcom,sc8280xp-qmp-gen3x2-pcie-phy + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy + - qcom,sdx65-qmp-gen4x2-pcie-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8150-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8350-qmp-gen3x2-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy + - qcom,sm8650-qmp-gen3x2-pcie-phy + - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1e80100-qmp-gen4x8-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy =20 reg: minItems: 1 --=20 2.34.1 From nobody Sat Oct 4 21:01:16 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BF152877C4 for ; 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Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 170 +++++++++++++++++++++++++++++++= +++- 1 file changed, 169 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 64a2abd3010018e94eb50c534a509d6b4cf2473b..b0f688ce1c285888c05ed718e58= dfafd51e2c1cf 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -970,7 +970,7 @@ gcc: clock-controller@100000 { reg =3D <0 0x00100000 0 0x1f0000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <&pcie1_phy>, + <&pcie0_phy>, <&pcie1_phy>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; clock-names =3D "bi_tcxo", "bi_tcxo_ao", "sleep_clk", @@ -2200,6 +2200,149 @@ wifi: wifi@17a10040 { qcom,smem-state-names =3D "wlan-smp2p-out"; }; =20 + pcie0: pci@1c00000 { + device_type =3D "pci"; + compatible =3D "qcom,pcie-sc7280"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf1d>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x1000>, + <0x0 0x60100000 0x0 0x100000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <0>; + num-lanes =3D <1>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + + clock-names =3D "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&aggre1_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc2 SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + iommu-map =3D <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc GCC_PCIE_0_GDSC>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; + + status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,sc7280-qmp-gen3x1-pcie-phy", "qcom,sm8250-qmp-gen3= x1-pcie-phy"; + reg =3D <0 0x01c06000 0 0x1000>; + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names =3D "pcie_0_pipe_clk"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + }; + pcie1: pcie@1c08000 { compatible =3D "qcom,pcie-sc7280"; reg =3D <0 0x01c08000 0 0x3000>, @@ -5285,6 +5428,31 @@ mi2s1_ws: mi2s1-ws-state { function =3D "mi2s1_ws"; }; =20 + pcie0_reset_n: pcie0-reset-n-state { + pins =3D "gpio87"; + function =3D "gpio"; + + drive-strength =3D <16>; + output-low; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins =3D "gpio89"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-up; + }; + + pcie0_clkreq_n: pcie0-clkreq-n-state { + pins =3D "gpio88"; + function =3D "pcie0_clkreqn"; + + bias-pull-up; + drive-strength =3D <2>; + }; + pcie1_clkreq_n: pcie1-clkreq-n-state { pins =3D "gpio79"; function =3D "pcie1_clkreqn"; --=20 2.34.1