From nobody Sat Oct 4 22:39:34 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC3D02F5337; Tue, 12 Aug 2025 14:11:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755007921; cv=none; b=uF8Cd3WuQeAkj+lK0kfPxOg58RYG++m29/aqia927pOuXQxN4/84NpUiRdl2LTKI/LqwLLRbzdajssjQvseGdAuYwkw1GTofy+365WTFm6OQ84aMcQPvSUGbLTfX/J9i09RYHrtWoeEq+mvr3JHPezYQaJMTfJeoEDDWesKQDos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755007921; c=relaxed/simple; bh=uypVqAWNF0yCdigPLP9veh96veIikQC2vWFszall9/s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=u5n81UbkbhPl2WI/qMKpLNbFLCP9GIhETb73n3D1sayA59N1xNdKWaouPHf0+uUt2nvorWRh3h8SyH7pIRl3bXyOosQKlummr44Yh0L8syPcF/CDUJJcCA8xQeGIxmM8Nb0Tp1+BaB4WZ+m/yLZw9QX2zPaDjK0gdJD53qfAgS8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=DTGge+yc; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DTGge+yc" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57CAvpJL032388; Tue, 12 Aug 2025 14:11:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= i7ivdIogUhQ2ah8cQPvOzYLAOJePsUjEEXCp/k8zl+Q=; b=DTGge+ycnsw/BqfE pizR7Ml4cW3486hpEYHLrxV9hP4Sii+TNDvuTKcstOlnGj+H1aKS58ayO/+rkaaM e+ahCa1WnaD1JgP57qw2c43M7C8ps1oGZnkZEr/fw9iR805ONbP6pbuAo+aC9sHl T30EISeij9cCZn3ExYYP8kyLphXv7gxKikMVrtlW8XFxqFWDJOrgX5gdJktwJerH jsio7Kjx+ndn6oyvxaObkRCh9xMySTn8cOtvKKM7krQRugAE3ydaHZE7WPgD0lwG Fm4PfsoAtueiXE5X8KoFFlnTJRxlET8Do5zaH0IxIVwuJ2v+Fm0PS4ZlctKTHo8I Vq47MA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48fm3vk9dw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Aug 2025 14:11:48 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57CEBlBX026376 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Aug 2025 14:11:47 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 07:11:42 -0700 From: Luo Jie Date: Tue, 12 Aug 2025 22:10:36 +0800 Subject: [PATCH net-next v7 12/14] net: ethernet: qualcomm: Initialize PPE L2 bridge settings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-qcom_ipq_ppe-v7-12-789404bdbc9a@quicinc.com> References: <20250812-qcom_ipq_ppe-v7-0-789404bdbc9a@quicinc.com> In-Reply-To: <20250812-qcom_ipq_ppe-v7-0-789404bdbc9a@quicinc.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lei Wei , Suruchi Agarwal , Pavithra R , "Simon Horman" , Jonathan Corbet , Kees Cook , "Gustavo A. R. Silva" , "Philipp Zabel" CC: , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755007841; l=7562; i=quic_luoj@quicinc.com; s=20250209; h=from:subject:message-id; bh=/5TSUUidSy3OGtjZrmWTRQjmK8EPIF6sm5KvCPL7+5M=; b=P7k6TPWgPotjcj3yLDfqGzgYOOZjTnL2jCjSN2GuSpTRfnsH7x68Xqov6zNQuaDdnyHwzNhvP I+92W7i4o1xA89IrF5WKvk9vvrH3fIEm/YJEbZdTZaWvivrzaY4mZBL X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=pzwy8bU5tJZ5UKGTv28n+QOuktaWuriznGmriA9Qkfc= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDEwNyBTYWx0ZWRfX+uTtcBTlDQ5E FA0rKPgs9Q5dozwsFSNKnL4SerpguK3k2+eHDiJ9F7dyqCArafR0R9PTn6OZDY0Apung5wPoUE6 Q+3QHwUNeXx2c4M+43TmCeUAmrDqc6yKm36SPO0vU+NXUTBM3y2/MeSIGhywYtkSlBJAMQvubWD dAsitiLQFxIpm5BlQQtBnUai0GEon+b9HUNdZJ2xprh8YMNdsLuY0ybW9FWq7gq/WoJbb6Sc0Xy iQ87+ogXizK8qJ3vCHv35Kz5yeQYx1Z1IZ5uAQ92Ex1/I9dxerSW97zd2YJXfZ0V+PkM5vMZO3r OprcLB+V1ojh8N0eosFb47ooAKhXGO0tUdHCmE21VmVlah88GC902RnzEWANOwFtFDFcBeaLutD +D8kY3W5 X-Proofpoint-GUID: jVtn6_jYavXb7iLaiDZRzXDKJo7pdlvN X-Authority-Analysis: v=2.4 cv=A+1sP7WG c=1 sm=1 tr=0 ts=689b4ba4 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=kjK3jMQdVcNyYKlBoqoA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: jVtn6_jYavXb7iLaiDZRzXDKJo7pdlvN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110107 From: Lei Wei Initialize the L2 bridge settings for the PPE ports to only enable L2 frame forwarding between CPU port and PPE Ethernet ports. The per-port L2 bridge settings are initialized as follows: For PPE CPU port, the PPE bridge TX is enabled and FDB learning is disabled. For PPE physical ports, the default L2 forwarding action is initialized to forward to CPU port only. L2/FDB learning and forwarding will not be enabled for PPE physical ports yet, since the port's VSI (Virtual Switch Instance) and VSI membership are not yet configured, which are required for FDB forwarding. The VSI and FDB forwarding will later be enabled when switchdev is enabled. Signed-off-by: Lei Wei Signed-off-by: Luo Jie --- drivers/net/ethernet/qualcomm/ppe/ppe_config.c | 80 ++++++++++++++++++++++= +++- drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 50 ++++++++++++++++ 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c b/drivers/net/e= thernet/qualcomm/ppe/ppe_config.c index 928fc0879269..e9a0e22907a6 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c @@ -1920,6 +1920,80 @@ static int ppe_queues_to_ring_init(struct ppe_device= *ppe_dev) return ppe_ring_queue_map_set(ppe_dev, 0, queue_bmap); } =20 +/* Initialize PPE bridge settings to only enable L2 frame receive and + * transmit between CPU port and PPE Ethernet ports. + */ +static int ppe_bridge_init(struct ppe_device *ppe_dev) +{ + u32 reg, mask, port_cfg[4], vsi_cfg[2]; + int ret, i; + + /* Configure the following settings for CPU port0: + * a.) Enable Bridge TX + * b.) Disable FDB new address learning + * c.) Disable station move address learning + */ + mask =3D PPE_PORT_BRIDGE_TXMAC_EN; + mask |=3D PPE_PORT_BRIDGE_NEW_LRN_EN; + mask |=3D PPE_PORT_BRIDGE_STA_MOVE_LRN_EN; + ret =3D regmap_update_bits(ppe_dev->regmap, + PPE_PORT_BRIDGE_CTRL_ADDR, + mask, + PPE_PORT_BRIDGE_TXMAC_EN); + if (ret) + return ret; + + for (i =3D 1; i < ppe_dev->num_ports; i++) { + /* Enable invalid VSI forwarding for all the physical ports + * to CPU port0, in case no VSI is assigned to the physical + * port. + */ + reg =3D PPE_L2_VP_PORT_TBL_ADDR + PPE_L2_VP_PORT_TBL_INC * i; + ret =3D regmap_bulk_read(ppe_dev->regmap, reg, + port_cfg, ARRAY_SIZE(port_cfg)); + + if (ret) + return ret; + + PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(port_cfg, true); + PPE_L2_PORT_SET_DST_INFO(port_cfg, 0); + + ret =3D regmap_bulk_write(ppe_dev->regmap, reg, + port_cfg, ARRAY_SIZE(port_cfg)); + if (ret) + return ret; + } + + for (i =3D 0; i < PPE_VSI_TBL_ENTRIES; i++) { + /* Set the VSI forward membership to include only CPU port0. + * FDB learning and forwarding take place only after switchdev + * is supported later to create the VSI and join the physical + * ports to the VSI port member. + */ + reg =3D PPE_VSI_TBL_ADDR + PPE_VSI_TBL_INC * i; + ret =3D regmap_bulk_read(ppe_dev->regmap, reg, + vsi_cfg, ARRAY_SIZE(vsi_cfg)); + if (ret) + return ret; + + PPE_VSI_SET_MEMBER_PORT_BITMAP(vsi_cfg, BIT(0)); + PPE_VSI_SET_UUC_BITMAP(vsi_cfg, BIT(0)); + PPE_VSI_SET_UMC_BITMAP(vsi_cfg, BIT(0)); + PPE_VSI_SET_BC_BITMAP(vsi_cfg, BIT(0)); + PPE_VSI_SET_NEW_ADDR_LRN_EN(vsi_cfg, true); + PPE_VSI_SET_NEW_ADDR_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD); + PPE_VSI_SET_STATION_MOVE_LRN_EN(vsi_cfg, true); + PPE_VSI_SET_STATION_MOVE_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD); + + ret =3D regmap_bulk_write(ppe_dev->regmap, reg, + vsi_cfg, ARRAY_SIZE(vsi_cfg)); + if (ret) + return ret; + } + + return 0; +} + int ppe_hw_config(struct ppe_device *ppe_dev) { int ret; @@ -1952,5 +2026,9 @@ int ppe_hw_config(struct ppe_device *ppe_dev) if (ret) return ret; =20 - return ppe_queues_to_ring_init(ppe_dev); + ret =3D ppe_queues_to_ring_init(ppe_dev); + if (ret) + return ret; + + return ppe_bridge_init(ppe_dev); } diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h b/drivers/net/eth= ernet/qualcomm/ppe/ppe_regs.h index 224beda046d4..6fc63f82ee80 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h @@ -117,6 +117,14 @@ #define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \ FIELD_MODIFY(PPE_EG_SERVICE_W1_TX_CNT_EN, (tbl_cfg) + 0x1, value) =20 +/* PPE port bridge configuration */ +#define PPE_PORT_BRIDGE_CTRL_ADDR 0x60300 +#define PPE_PORT_BRIDGE_CTRL_ENTRIES 8 +#define PPE_PORT_BRIDGE_CTRL_INC 4 +#define PPE_PORT_BRIDGE_NEW_LRN_EN BIT(0) +#define PPE_PORT_BRIDGE_STA_MOVE_LRN_EN BIT(3) +#define PPE_PORT_BRIDGE_TXMAC_EN BIT(16) + /* PPE port control configurations for the traffic to the multicast queues= . */ #define PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00 #define PPE_MC_MTU_CTRL_TBL_ENTRIES 8 @@ -125,6 +133,36 @@ #define PPE_MC_MTU_CTRL_TBL_MTU_CMD GENMASK(15, 14) #define PPE_MC_MTU_CTRL_TBL_TX_CNT_EN BIT(16) =20 +/* PPE VSI configurations */ +#define PPE_VSI_TBL_ADDR 0x63800 +#define PPE_VSI_TBL_ENTRIES 64 +#define PPE_VSI_TBL_INC 0x10 +#define PPE_VSI_W0_MEMBER_PORT_BITMAP GENMASK(7, 0) +#define PPE_VSI_W0_UUC_BITMAP GENMASK(15, 8) +#define PPE_VSI_W0_UMC_BITMAP GENMASK(23, 16) +#define PPE_VSI_W0_BC_BITMAP GENMASK(31, 24) +#define PPE_VSI_W1_NEW_ADDR_LRN_EN BIT(0) +#define PPE_VSI_W1_NEW_ADDR_FWD_CMD GENMASK(2, 1) +#define PPE_VSI_W1_STATION_MOVE_LRN_EN BIT(3) +#define PPE_VSI_W1_STATION_MOVE_FWD_CMD GENMASK(5, 4) + +#define PPE_VSI_SET_MEMBER_PORT_BITMAP(tbl_cfg, value) \ + FIELD_MODIFY(PPE_VSI_W0_MEMBER_PORT_BITMAP, tbl_cfg, value) +#define PPE_VSI_SET_UUC_BITMAP(tbl_cfg, value) \ + FIELD_MODIFY(PPE_VSI_W0_UUC_BITMAP, tbl_cfg, value) +#define PPE_VSI_SET_UMC_BITMAP(tbl_cfg, value) \ + FIELD_MODIFY(PPE_VSI_W0_UMC_BITMAP, tbl_cfg, value) +#define PPE_VSI_SET_BC_BITMAP(tbl_cfg, value) \ + FIELD_MODIFY(PPE_VSI_W0_BC_BITMAP, tbl_cfg, value) +#define PPE_VSI_SET_NEW_ADDR_LRN_EN(tbl_cfg, value) \ + FIELD_MODIFY(PPE_VSI_W1_NEW_ADDR_LRN_EN, (tbl_cfg) + 0x1, value) +#define PPE_VSI_SET_NEW_ADDR_FWD_CMD(tbl_cfg, value) \ + FIELD_MODIFY(PPE_VSI_W1_NEW_ADDR_FWD_CMD, (tbl_cfg) + 0x1, value) +#define PPE_VSI_SET_STATION_MOVE_LRN_EN(tbl_cfg, value) \ + FIELD_MODIFY(PPE_VSI_W1_STATION_MOVE_LRN_EN, (tbl_cfg) + 0x1, value) +#define PPE_VSI_SET_STATION_MOVE_FWD_CMD(tbl_cfg, value) \ + FIELD_MODIFY(PPE_VSI_W1_STATION_MOVE_FWD_CMD, (tbl_cfg) + 0x1, value) + /* PPE port control configurations for the traffic to the unicast queues. = */ #define PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000 #define PPE_MRU_MTU_CTRL_TBL_ENTRIES 256 @@ -163,6 +201,18 @@ #define PPE_IN_L2_SERVICE_TBL_RX_CNT_EN BIT(30) #define PPE_IN_L2_SERVICE_TBL_TX_CNT_EN BIT(31) =20 +/* L2 Port configurations */ +#define PPE_L2_VP_PORT_TBL_ADDR 0x98000 +#define PPE_L2_VP_PORT_TBL_ENTRIES 256 +#define PPE_L2_VP_PORT_TBL_INC 0x10 +#define PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN BIT(0) +#define PPE_L2_VP_PORT_W0_DST_INFO GENMASK(9, 2) + +#define PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(tbl_cfg, value) \ + FIELD_MODIFY(PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN, tbl_cfg, value) +#define PPE_L2_PORT_SET_DST_INFO(tbl_cfg, value) \ + FIELD_MODIFY(PPE_L2_VP_PORT_W0_DST_INFO, tbl_cfg, value) + /* PPE service code configuration for the tunnel packet. */ #define PPE_TL_SERVICE_TBL_ADDR 0x306000 #define PPE_TL_SERVICE_TBL_ENTRIES 256 --=20 2.34.1