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Tue, 12 Aug 2025 09:30:24 -0700 (PDT) Received: from [127.0.0.2] ([2a02:2454:ff21:ef41:5574:c911:d648:8bca]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459ebede65asm255302755e9.8.2025.08.12.09.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 09:30:24 -0700 (PDT) From: Stephan Gerhold Date: Tue, 12 Aug 2025 18:30:19 +0200 Subject: [PATCH] phy: qcom: qmp-pcie: Fix PHY initialization when powered down by firmware Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-phy-qcom-qmp-pcie-nocsr-fix-v1-1-9a7d0a5d2b46@linaro.org> X-B4-Tracking: v=1; b=H4sIABpsm2gC/x3MPQqAMAxA4atIZgNt/UG9ijhIjJrBtrYgSvHuF sfvDS9B5CAcYSgSBL4kirMZuiyA9tlujLJkg1GmUZ026PcHT3IHnodHT8JoHcWAq9yoW1Vp1Zq +pgXywQfO+b+P0/t+8JKf320AAAA= X-Change-ID: 20250812-phy-qcom-qmp-pcie-nocsr-fix-1603106294cd To: Vinod Koul Cc: Kishon Vijay Abraham I , Wenbin Yao , Qiang Yu , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 Commit 0cc22f5a861c ("phy: qcom: qmp-pcie: Add PHY register retention support") added support for using the "no_csr" reset to skip configuration of the PHY if the init sequence was already applied by the boot firmware. The expectation is that the PHY is only turned on/off by using the "no_csr" reset, instead of powering it down and re-programming it after a full reset. The boot firmware on X1E does not fully conform to this expectation: If the PCIe3 link fails to come up (e.g. because no PCIe card is inserted), the firmware powers down the PHY using the QPHY_PCS_POWER_DOWN_CONTROL register. The QPHY_START_CTRL register is kept as-is, so the driver assumes the PHY is already initialized and skips the configuration/power up sequence. The PHY won't come up again without clearing the QPHY_PCS_POWER_DOWN_CONTROL, so eventually initialization fails: qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out phy phy-1be0000.phy.0: phy poweron failed --> -110 qcom-pcie 1bd0000.pcie: cannot initialize host qcom-pcie 1bd0000.pcie: probe with driver qcom-pcie failed with error -110 This can be reliably reproduced on the X1E CRD, QCP and Devkit when no card is inserted for PCIe3. Fix this by checking the QPHY_PCS_POWER_DOWN_CONTROL register in addition to QPHY_START_CTRL. If the PHY is powered down with the register, it doesn't conform to the expectations for using the "no_csr" reset, so we fully re-initialize with the normal reset sequence. Cc: stable@vger.kernel.org Fixes: 0cc22f5a861c ("phy: qcom: qmp-pcie: Add PHY register retention suppo= rt") Signed-off-by: Stephan Gerhold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 95830dcfdec9b1f68fd55d1cc3c102985cfafcc1..6a469a8f5ae7eba6e4d1d702efa= ae1c658c4321e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4339,10 +4339,12 @@ static int qmp_pcie_init(struct phy *phy) struct qmp_pcie *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; void __iomem *pcs =3D qmp->pcs; - bool phy_initialized =3D !!(readl(pcs + cfg->regs[QPHY_START_CTRL])); int ret; =20 - qmp->skip_init =3D qmp->nocsr_reset && phy_initialized; + qmp->skip_init =3D qmp->nocsr_reset && + readl(pcs + cfg->regs[QPHY_START_CTRL]) && + readl(pcs + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]); + /* * We need to check the existence of init sequences in two cases: * 1. The PHY doesn't support no_csr reset. --- base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 change-id: 20250812-phy-qcom-qmp-pcie-nocsr-fix-1603106294cd Best regards, --=20 Stephan Gerhold