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Tue, 12 Aug 2025 05:13:05 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:55 +0200 Subject: [PATCH RESEND 13/14] gpio: mpc8xxx: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-13-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10008; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=8xlnAhAzfwO4+HhxnfhDkoiDZ7pkFtIamWGlMtDqlhM=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBomy/BD/P/xaKsdeGc+eVubcf3SBVOQW3li84GX T7I2LtL3RWJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaJsvwQAKCRARpy6gFHHX ckahD/wOI88EUItkZnUpOxrHCMdSSXQHbpiHNnCobvI4RrEZHjhEGhbZqFXVz4l/FcH62kvUBPK crpJY3loYZaQn9PnGhkGKAf+BsPYuQF7UEGloMb4/+Tt9EWssHSLVIzwgqhERnRVKVopSqwyomD ZlZzBluREJoGiE67Tysf7TSqm1nXYyqdi8y9zDHbskLdSme9v8woThvPZBIPcaqiPqfnFPjKIOY FqNPiN2upsAUTSXt9APqX3M79HY5OhgKxmYrYXMflZx7pIUGOHxDFuS8bOfYQ3U1GESDjE6A8M+ Q5E4PqYoRlpe8sjt/YVL8VkEOA7m57RpXdMy1cY/fUP3sf0bBmHqlM6KjAxJuk3frz4Ja1BK1pL ldQmwOKFb4T2jvT2Vck7IoXgA/ZMVMAoaAdVPpOOQBMDD5cnnpmJnryB4BqURV48JkveBEVJIdD emtqTKnFgM6QWCHSU7eavO/RS+ighIlkpFjw8RU8JdDkOKYWqZMlqLO2mbPks1tdICszaHtG5wI EmysuD8juH/B97h2bOpSqPgWiiTk8BTCew0EaOlEdT0ZwELE5B2IRV3mxEYAz4sxpFmjV+ru3iE Z35C/A1OhZZCtXnB0tInzQ9W/nvZ2mq4Y6f+lWPHVAkfrSfK16w7IH9wWnpX2X63X4DPHSdF9B1 3Ho8+wKSAB4iltg== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-mpc8xxx.c | 102 +++++++++++++++++++++++++++-------------= ---- 1 file changed, 62 insertions(+), 40 deletions(-) diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 121efdd71e451d4f992fa195b0d56d7146a6f3dd..38643fb813c562957076aab48d8= 04f8048cee5e4 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,7 @@ #define GPIO_IBE 0x18 =20 struct mpc8xxx_gpio_chip { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *regs; raw_spinlock_t lock; =20 @@ -66,8 +67,10 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsign= ed int gpio) struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D gpiochip_get_data(gc); u32 out_mask, out_shadow; =20 - out_mask =3D gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); - val =3D gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; + out_mask =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_DIR); + val =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; out_shadow =3D gc->bgpio_data & out_mask; =20 return !!((val | out_shadow) & mpc_pin2mask(gpio)); @@ -108,12 +111,13 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, = unsigned offset) static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D data; - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; unsigned long mask; int i; =20 - mask =3D gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) - & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); + mask =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IER) & + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR); for_each_set_bit(i, &mask, 32) generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); =20 @@ -124,15 +128,17 @@ static void mpc8xxx_irq_unmask(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; + struct gpio_chip *gc =3D &mpc8xxx_gc->chip.gc; unsigned long flags; =20 gpiochip_enable_irq(gc, hwirq); =20 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); =20 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, - gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR, + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR) | mpc_pin2mask(irqd_to_hwirq(d))); =20 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); @@ -142,13 +148,14 @@ static void mpc8xxx_irq_mask(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; + struct gpio_chip *gc =3D &mpc8xxx_gc->chip.gc; unsigned long flags; =20 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); =20 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, - gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) + gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IMR, + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR) & ~mpc_pin2mask(irqd_to_hwirq(d))); =20 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); @@ -159,32 +166,34 @@ static void mpc8xxx_irq_mask(struct irq_data *d) static void mpc8xxx_irq_ack(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; =20 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, + gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IER, mpc_pin2mask(irqd_to_hwirq(d))); } =20 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; unsigned long flags; =20 switch (flow_type) { case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, - gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_ICR, + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_ICR) | mpc_pin2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; =20 case IRQ_TYPE_EDGE_BOTH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, - gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_ICR, + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_ICR) & ~mpc_pin2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; @@ -199,7 +208,6 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, uns= igned int flow_type) static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; unsigned long gpio =3D irqd_to_hwirq(d); void __iomem *reg; unsigned int shift; @@ -217,7 +225,9 @@ static int mpc512x_irq_set_type(struct irq_data *d, uns= igned int flow_type) case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, + (gpio_generic_read_reg(&mpc8xxx_gc->chip, + reg) & ~(3 << shift)) | (2 << shift)); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; @@ -225,14 +235,18 @@ static int mpc512x_irq_set_type(struct irq_data *d, u= nsigned int flow_type) case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, + (gpio_generic_read_reg(&mpc8xxx_gc->chip, + reg) & ~(3 << shift)) | (1 << shift)); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; =20 case IRQ_TYPE_EDGE_BOTH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, + (gpio_generic_read_reg(&mpc8xxx_gc->chip, + reg) & ~(3 << shift))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; =20 @@ -309,6 +323,7 @@ static const struct of_device_id mpc8xxx_gpio_ids[] =3D= { static int mpc8xxx_probe(struct platform_device *pdev) { const struct mpc8xxx_gpio_devtype *devtype =3D NULL; + struct gpio_generic_chip_config config; struct mpc8xxx_gpio_chip *mpc8xxx_gc; struct device *dev =3D &pdev->dev; struct fwnode_handle *fwnode; @@ -327,26 +342,28 @@ static int mpc8xxx_probe(struct platform_device *pdev) if (IS_ERR(mpc8xxx_gc->regs)) return PTR_ERR(mpc8xxx_gc->regs); =20 - gc =3D &mpc8xxx_gc->gc; + gc =3D &mpc8xxx_gc->chip.gc; gc->parent =3D dev; =20 + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D mpc8xxx_gc->regs + GPIO_DAT, + .dirout =3D mpc8xxx_gc->regs + GPIO_DIR, + .flags =3D BGPIOF_BIG_ENDIAN + }; + if (device_property_read_bool(dev, "little-endian")) { - ret =3D bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, - NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, - NULL, BGPIOF_BIG_ENDIAN); - if (ret) - return ret; dev_dbg(dev, "GPIO registers are LITTLE endian\n"); } else { - ret =3D bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, - NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, - NULL, BGPIOF_BIG_ENDIAN - | BGPIOF_BIG_ENDIAN_BYTE_ORDER); - if (ret) - return ret; + config.flags |=3D BGPIOF_BIG_ENDIAN_BYTE_ORDER; dev_dbg(dev, "GPIO registers are BIG endian\n"); } =20 + ret =3D gpio_generic_chip_init(&mpc8xxx_gc->chip, &config); + if (ret) + return ret; + mpc8xxx_gc->direction_output =3D gc->direction_output; =20 devtype =3D device_get_match_data(dev); @@ -379,10 +396,13 @@ static int mpc8xxx_probe(struct platform_device *pdev) device_is_compatible(dev, "fsl,ls1028a-gpio") || device_is_compatible(dev, "fsl,ls1088a-gpio") || is_acpi_node(fwnode)) { - gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); /* Also, latch state of GPIOs configured as output by bootloader. */ - gc->bgpio_data =3D gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & - gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); + gc->bgpio_data =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_DAT) & + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_DIR); } =20 ret =3D devm_gpiochip_add_data(dev, gc, mpc8xxx_gc); @@ -405,8 +425,10 @@ static int mpc8xxx_probe(struct platform_device *pdev) return 0; =20 /* ack and mask all irqs */ - gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR, 0); =20 ret =3D devm_request_irq(dev, mpc8xxx_gc->irqn, mpc8xxx_gpio_irq_cascade, --=20 2.48.1