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Tue, 12 Aug 2025 05:13:04 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:54 +0200 Subject: [PATCH RESEND 12/14] gpio: grgpio: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-12-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7995; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=AGhvI8vG5SGj9cxXM06eRQt9v1ofBIcmVl22/TTQOT4=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBomy/B2uC99j03LG6YqrSjYI1DM3Eo3y3JKfFEx QfAdkwocqqJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaJsvwQAKCRARpy6gFHHX chomD/99PF5ZgALZBSBXLGEmNVP7fTB67ncQva5kxfSiNoteRRRSkHkgyCVNYJysG2jPmja7155 ulYjRWLmnmVbYErcjNj5Nvg0VL/vAOSPQX1cl1f0c84S2aDWvq3ZFVZSEDm7gh5EpQRX4TRzmGg onz7NzmDK4Y+0azft8KtDcvi/d9fHs8KIS+x18FgiCaNK+CajZXvfFtrYfARotRnPjIFOcs7srb fYZwT9K4zO4GEwdxNJRugc5TARAcIcB03ts+P9hfmfgO/joVcjAcziRcj/gUQcCBydm3esCULXJ 1D2GxsOZ2QUbFZMuKyawmi8yKzIL4XRx/ba/B9i5Lyav5+vVBna0IrbhlpYiLIb6JQRh5h3MJUg PdgU8SBqGgxxUUeS0UESQpmBkgdJ7aHfKg84ILJOpsUYuV0BO+43Njn2T+9bpQqa4l3vBWLZqI6 JDzhxB8Z8a4HwaSJcLb5eUCLZNA0s9BQfWwdlOcXhFpT5KwfiYmXF5Jz5KcOVoZYJmtAgS2OgYR 0cQWDr34AuW+XtCcXmTe6uliwoo+vUA0oqxTIppfpBzHfV0nw8Jp0+09ZCBbFjProMX0JoP/d6J wVO/DYB19bf8sSMEZIN1kQplBcUH9QbtQoug0Hsr+NbStzWLjoSMFWcuqre6llR2E4IjU1sIiIz Ph/5uDayKWYxl8A== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-grgpio.c | 87 +++++++++++++++++++++++-------------------= ---- 1 file changed, 44 insertions(+), 43 deletions(-) diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c index f3f8bab62f94cefb69d31d76b961ab2d346df49e..3b77fad00749cd5218268b267b5= 848515c6a26fc 100644 --- a/drivers/gpio/gpio-grgpio.c +++ b/drivers/gpio/gpio-grgpio.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -59,7 +60,7 @@ struct grgpio_lirq { }; =20 struct grgpio_priv { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *regs; struct device *dev; =20 @@ -91,13 +92,12 @@ struct grgpio_priv { static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset, int val) { - struct gpio_chip *gc =3D &priv->gc; - if (val) priv->imask |=3D BIT(offset); else priv->imask &=3D ~BIT(offset); - gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); + + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IMASK, priv->imas= k); } =20 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset) @@ -118,7 +118,6 @@ static int grgpio_to_irq(struct gpio_chip *gc, unsigned= offset) static int grgpio_irq_set_type(struct irq_data *d, unsigned int type) { struct grgpio_priv *priv =3D irq_data_get_irq_chip_data(d); - unsigned long flags; u32 mask =3D BIT(d->hwirq); u32 ipol; u32 iedge; @@ -146,15 +145,13 @@ static int grgpio_irq_set_type(struct irq_data *d, un= signed int type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&priv->chip); =20 - ipol =3D priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask; - iedge =3D priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask; + ipol =3D gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IPOL) & ~= mask; + iedge =3D gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IEDGE) &= ~mask; =20 - priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol); - priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge); - - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IPOL, ipol | pol); + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IEDGE, iedge | ed= ge); =20 return 0; } @@ -163,29 +160,23 @@ static void grgpio_irq_mask(struct irq_data *d) { struct grgpio_priv *priv =3D irq_data_get_irq_chip_data(d); int offset =3D d->hwirq; - unsigned long flags; =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &priv->chip) + grgpio_set_imask(priv, offset, 0); =20 - grgpio_set_imask(priv, offset, 0); - - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); - - gpiochip_disable_irq(&priv->gc, d->hwirq); + gpiochip_disable_irq(&priv->chip.gc, d->hwirq); } =20 static void grgpio_irq_unmask(struct irq_data *d) { struct grgpio_priv *priv =3D irq_data_get_irq_chip_data(d); int offset =3D d->hwirq; - unsigned long flags; =20 - gpiochip_enable_irq(&priv->gc, d->hwirq); - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + gpiochip_enable_irq(&priv->chip.gc, d->hwirq); + + guard(gpio_generic_lock_irqsave)(&priv->chip); =20 grgpio_set_imask(priv, offset, 1); - - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); } =20 static const struct irq_chip grgpio_irq_chip =3D { @@ -200,12 +191,11 @@ static const struct irq_chip grgpio_irq_chip =3D { static irqreturn_t grgpio_irq_handler(int irq, void *dev) { struct grgpio_priv *priv =3D dev; - int ngpio =3D priv->gc.ngpio; - unsigned long flags; + int ngpio =3D priv->chip.gc.ngpio; int i; int match =3D 0; =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&priv->chip); =20 /* * For each gpio line, call its interrupt handler if it its underlying @@ -221,8 +211,6 @@ static irqreturn_t grgpio_irq_handler(int irq, void *de= v) } } =20 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); - if (!match) dev_warn(priv->dev, "No gpio line matched irq %d\n", irq); =20 @@ -253,13 +241,18 @@ static int grgpio_irq_map(struct irq_domain *d, unsig= ned int irq, dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n", irq, offset); =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_lock_irqsave(&priv->chip, flags); =20 /* Request underlying irq if not already requested */ lirq->irq =3D irq; uirq =3D &priv->uirqs[lirq->index]; if (uirq->refcnt =3D=3D 0) { - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + /* + * FIXME: This is not how locking works at all, you can't just + * release the lock for a moment to do something that can't + * sleep... + */ + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); ret =3D request_irq(uirq->uirq, grgpio_irq_handler, 0, dev_name(priv->dev), priv); if (ret) { @@ -268,11 +261,11 @@ static int grgpio_irq_map(struct irq_domain *d, unsig= ned int irq, uirq->uirq); return ret; } - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_lock_irqsave(&priv->chip, flags); } uirq->refcnt++; =20 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); =20 /* Setup irq */ irq_set_chip_data(irq, priv); @@ -290,13 +283,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, un= signed int irq) struct grgpio_lirq *lirq; struct grgpio_uirq *uirq; unsigned long flags; - int ngpio =3D priv->gc.ngpio; + int ngpio =3D priv->chip.gc.ngpio; int i; =20 irq_set_chip_and_handler(irq, NULL, NULL); irq_set_chip_data(irq, NULL); =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_lock_irqsave(&priv->chip, flags); =20 /* Free underlying irq if last user unmapped */ index =3D -1; @@ -315,13 +308,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, un= signed int irq) uirq =3D &priv->uirqs[lirq->index]; uirq->refcnt--; if (uirq->refcnt =3D=3D 0) { - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); free_irq(uirq->uirq, priv); return; } } =20 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); } =20 static void grgpio_irq_domain_remove(void *data) @@ -341,6 +334,7 @@ static const struct irq_domain_ops grgpio_irq_domain_op= s =3D { static int grgpio_probe(struct platform_device *ofdev) { struct device_node *np =3D ofdev->dev.of_node; + struct gpio_generic_chip_config config; struct device *dev =3D &ofdev->dev; void __iomem *regs; struct gpio_chip *gc; @@ -359,17 +353,24 @@ static int grgpio_probe(struct platform_device *ofdev) if (IS_ERR(regs)) return PTR_ERR(regs); =20 - gc =3D &priv->gc; - err =3D bgpio_init(gc, dev, 4, regs + GRGPIO_DATA, - regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL, - BGPIOF_BIG_ENDIAN_BYTE_ORDER); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D regs + GRGPIO_DATA, + .set =3D regs + GRGPIO_OUTPUT, + .dirout =3D regs + GRGPIO_DIR, + .flags =3D BGPIOF_BIG_ENDIAN_BYTE_ORDER, + }; + + gc =3D &priv->chip.gc; + err =3D gpio_generic_chip_init(&priv->chip, &config); if (err) { - dev_err(dev, "bgpio_init() failed\n"); + dev_err(dev, "failed to initialize the generic GPIO chip\n"); return err; } =20 priv->regs =3D regs; - priv->imask =3D gc->read_reg(regs + GRGPIO_IMASK); + priv->imask =3D gpio_generic_read_reg(&priv->chip, regs + GRGPIO_IMASK); priv->dev =3D dev; =20 gc->owner =3D THIS_MODULE; --=20 2.48.1