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Tue, 12 Aug 2025 05:13:01 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:52 +0200 Subject: [PATCH RESEND 10/14] gpio: amdpt: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-10-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4007; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=J+TT9XjbJJKbjE77nqgtMEqiO3qZwqcbYA98JKh3zw8=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBomy/BELGF8WeZdyE8Hb//8DlU41prWqZVK+ZHx SzPK2xIFM2JAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaJsvwQAKCRARpy6gFHHX cjErD/9odeqgoWXMsX2plGrfcpj1RQRBtlsnb9eFQkWpAVjcW1hoCl4XAfvVDQmzRV0j8FjesqV EV3vPblsndq9BdJoGUSt8PPNWxdGwu8d7tI+RNqqlBpBop0y1tdWa3Ucm9KYYEY8l+CFlReGW3e pFPpXTdH4cxSYWrTWxtzS0chesSyWIU63ZOFixhjI2iHsv12Sato+vmcVjXLVZ1Eu0acgjzwxYK Wjyz008T6Tch9NfqM9hxx0DHzTPnD+YB1+IiCLjyNiZZ/pO1HeImB5T2ZsX1r6HHJ8TXLMtXroh sXsYaprSVJYsPnRYUc5rJfXkHiAAWQVD7DrVxC51JSZRKkOYFxgs4TaV4kc9ojCFjjf6OXSWQ+p qnqFsSNrStWXiEdrf36V6em8VFWMdiqGQski900NPGD1RFRf+V+Eof5+d2pkwubi7U1WpLNwnG1 Gov2a5U8f3chK6lZVsz/E43l1iExRjhH+B7yuSrOKn0iW//hBvI3S7hZ0qmPmoT7qd8TApPS5VI R45U0wm+HUY+ADxLILCUZu4nlXSdLkad0hamI6rVOd/jv6nra/pjfkwMaGNvgfgKJCb8Vbyh+24 4fH+tQSsqzr3dxNjWIpNdEl6Nw6WB4sKyVgXXkUzenkLTxILNHAd+CydMfJa8pW6eZbU8SgLnLb +WSik3H2GcYxE9Q== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-amdpt.c | 44 +++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/gpio/gpio-amdpt.c b/drivers/gpio/gpio-amdpt.c index b70036587d9c3f64bb73ed3b94e1c14f249c9e21..0a9b870705b90bdc9bdab93ce5a= 4a33ebdafccc6 100644 --- a/drivers/gpio/gpio-amdpt.c +++ b/drivers/gpio/gpio-amdpt.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -24,54 +25,50 @@ #define PT_SYNC_REG 0x28 =20 struct pt_gpio_chip { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *reg_base; }; =20 static int pt_gpio_request(struct gpio_chip *gc, unsigned offset) { + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct pt_gpio_chip *pt_gpio =3D gpiochip_get_data(gc); - unsigned long flags; u32 using_pins; =20 dev_dbg(gc->parent, "pt_gpio_request offset=3D%x\n", offset); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); =20 using_pins =3D readl(pt_gpio->reg_base + PT_SYNC_REG); if (using_pins & BIT(offset)) { dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n", offset); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); return -EINVAL; } =20 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); - return 0; } =20 static void pt_gpio_free(struct gpio_chip *gc, unsigned offset) { + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct pt_gpio_chip *pt_gpio =3D gpiochip_get_data(gc); - unsigned long flags; u32 using_pins; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); =20 using_pins =3D readl(pt_gpio->reg_base + PT_SYNC_REG); using_pins &=3D ~BIT(offset); writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); - dev_dbg(gc->parent, "pt_gpio_free offset=3D%x\n", offset); } =20 static int pt_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct pt_gpio_chip *pt_gpio; int ret =3D 0; @@ -91,22 +88,27 @@ static int pt_gpio_probe(struct platform_device *pdev) return PTR_ERR(pt_gpio->reg_base); } =20 - ret =3D bgpio_init(&pt_gpio->gc, dev, 4, - pt_gpio->reg_base + PT_INPUTDATA_REG, - pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, - pt_gpio->reg_base + PT_DIRECTION_REG, NULL, - BGPIOF_READ_OUTPUT_REG_SET); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D pt_gpio->reg_base + PT_INPUTDATA_REG, + .set =3D pt_gpio->reg_base + PT_OUTPUTDATA_REG, + .dirout =3D pt_gpio->reg_base + PT_DIRECTION_REG, + .flags =3D BGPIOF_READ_OUTPUT_REG_SET, + }; + + ret =3D gpio_generic_chip_init(&pt_gpio->chip, &config); if (ret) { - dev_err(dev, "bgpio_init failed\n"); + dev_err(dev, "failed to initialize the generic GPIO chip\n"); return ret; } =20 - pt_gpio->gc.owner =3D THIS_MODULE; - pt_gpio->gc.request =3D pt_gpio_request; - pt_gpio->gc.free =3D pt_gpio_free; - pt_gpio->gc.ngpio =3D (uintptr_t)device_get_match_data(dev); + pt_gpio->chip.gc.owner =3D THIS_MODULE; + pt_gpio->chip.gc.request =3D pt_gpio_request; + pt_gpio->chip.gc.free =3D pt_gpio_free; + pt_gpio->chip.gc.ngpio =3D (uintptr_t)device_get_match_data(dev); =20 - ret =3D devm_gpiochip_add_data(dev, &pt_gpio->gc, pt_gpio); + ret =3D devm_gpiochip_add_data(dev, &pt_gpio->chip.gc, pt_gpio); if (ret) { dev_err(dev, "Failed to register GPIO lib\n"); return ret; --=20 2.48.1