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Tue, 12 Aug 2025 05:12:51 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:43 +0200 Subject: [PATCH RESEND 01/14] gpio: generic: provide to_gpio_generic_chip() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-1-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=872; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=q7IZHV9NOU3n+seY+p1AeQbkCwKHTjI/3z6Qnen62yA=; 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- include/linux/gpio/generic.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h index f3a8db4598bb59f1dba4fbebace24dc10be44ae4..5a85ecbef8d234d9cf0c2f1db7a= 97f5f3781b2e4 100644 --- a/include/linux/gpio/generic.h +++ b/include/linux/gpio/generic.h @@ -55,6 +55,12 @@ struct gpio_generic_chip { struct gpio_chip gc; }; =20 +static inline struct gpio_generic_chip * +to_gpio_generic_chip(struct gpio_chip *gc) +{ + return container_of(gc, struct gpio_generic_chip, gc); +} + /** * gpio_generic_chip_init() - Initialize a generic GPIO chip. * @chip: Generic GPIO chip to set up. --=20 2.48.1 From nobody Sat Oct 4 22:33:04 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2062E2EFD87 for ; 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Tue, 12 Aug 2025 05:12:53 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:16c8:50:27fe:4d94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e6867193sm298878535e9.6.2025.08.12.05.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 05:12:52 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:44 +0200 Subject: [PATCH RESEND 02/14] gpio: generic: provide helpers for reading and writing registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-2-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Provide helpers wrapping the read_reg() and write_reg() callbacks of the generic GPIO API that are called directly by many users. This is done to hide their implementation ahead of moving them into the separate generic GPIO struct. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- include/linux/gpio/generic.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h index 5a85ecbef8d234d9cf0c2f1db7a97f5f3781b2e4..4c0626b53ec90388a034bc7797e= efa53e7ea064e 100644 --- a/include/linux/gpio/generic.h +++ b/include/linux/gpio/generic.h @@ -100,6 +100,37 @@ gpio_generic_chip_set(struct gpio_generic_chip *chip, = unsigned int offset, return chip->gc.set(&chip->gc, offset, value); } =20 +/** + * gpio_generic_read_reg() - Read a register using the underlying callback. + * @chip: Generic GPIO chip to use. + * @reg: Register to read. + * + * Returns: value read from register. + */ +static inline unsigned long +gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg) +{ + if (WARN_ON(!chip->gc.read_reg)) + return 0; + + return chip->gc.read_reg(reg); +} + +/** + * gpio_generic_write_reg() - Write a register using the underlying callba= ck. + * @chip: Generic GPIO chip to use. + * @reg: Register to write to. + * @val: New value to write. + */ +static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip, + void __iomem *reg, unsigned long val) +{ + if (WARN_ON(!chip->gc.write_reg)) + return; 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Tue, 12 Aug 2025 05:12:53 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:45 +0200 Subject: [PATCH RESEND 03/14] gpio: hisi: use the BGPIOF_UNREADABLE_REG_DIR flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-3-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1294; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=LGZlUs6AQDs8ng5Nn7ommqnFHh3w6/vhUJqzq5JniBE=; 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-hisi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-hisi.c b/drivers/gpio/gpio-hisi.c index ef5cc654a24e2327510b872563e68fb0b9aaef71..6016e6f0ed0fb80ea670ebb5754= 52d9ec23976fa 100644 --- a/drivers/gpio/gpio-hisi.c +++ b/drivers/gpio/gpio-hisi.c @@ -295,7 +295,7 @@ static int hisi_gpio_probe(struct platform_device *pdev) hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX, hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX, hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX, - BGPIOF_NO_SET_ON_INPUT); + BGPIOF_NO_SET_ON_INPUT | BGPIOF_UNREADABLE_REG_DIR); if (ret) { dev_err(dev, "failed to init, ret =3D %d\n", ret); return ret; @@ -303,7 +303,6 @@ static int hisi_gpio_probe(struct platform_device *pdev) =20 hisi_gpio->chip.set_config =3D hisi_gpio_set_config; hisi_gpio->chip.ngpio =3D hisi_gpio->line_num; - hisi_gpio->chip.bgpio_dir_unreadable =3D 1; hisi_gpio->chip.base =3D -1; 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Tue, 12 Aug 2025 05:12:54 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:46 +0200 Subject: [PATCH RESEND 04/14] gpio: ts4800: remove the unnecessary call to platform_set_drvdata() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-4-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=749; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=l19XxlCMzrhQb7segGk57h4S+g8U8d8cxgGqBJH6nF0=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBomy+/9er37Ak/sFPPdUpU+bYimsPDTN2yc6x42 FQ8FY/oejWJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaJsvvwAKCRARpy6gFHHX cs1kEACnksREk9QmO2FhzrwUyQY6DFqRCpWOw11t0IdlkTmT1crGP48e6IKjx54SKHyp4sN42jo stgwcLRvwFedR2zvmHej3NLE2HegxIm4m7iEfrgRnaPO3fLODyWUW/lMX114rXBqNa6GrspT2ne dP5ciZfuBXiSlsOVW16bgOErzHt187wcG825R98099jTmshxHjqsrTUlIsEsTtrLi3FEN4zIzv0 hr5+6atZ0zl9joHZx2V7PTzwKZGbgzWcQrs6PieTOlLSiSCvWomMaM/tZhuro2JemTnb476JlhH //BD0Iw7ncTNdylkaDpA3Xb3JTcbgipc3GNuhp7mJhdruTE7AfWI0V92/a2P4rWfWSHPvAurGnC Nte/Q7KLeNVJzz1rv1O/6Phap6sCLBL7Brkop+kaa5OQPDW2wWX6fBTiC+UiYm0E5WwP/JhhxYK DGTWaHo7PDMXaxR9zrtJVnPiPLa/RRbAx4MUpsbEFx60d6vuyTkBFj4iDmVILm/a0fd0BxssCA5 GvKxj0iXDd3zlORV3S3Ux716TyKOEVfwghYqPxOs5ZI84XPMKMuo4zsZXniZWfY+Cr690AiYvcX f9lCK5D8o3flMW7LKN5i2yjOd5DAJAHljz+naFZ34U5udYaR5ywzIftABA2Q0648whgtGJ0IEGM uS04lz8L4PvZKuQ== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski There's no corresponding call to platform_get_drvdata() or dev_get_drvdata(). Remove the call to platform_set_drvdata() from .probe(). Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ts4800.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpio/gpio-ts4800.c b/drivers/gpio/gpio-ts4800.c index 4748e3d47106cd2db6a994928b20f76921540a60..86f7947ca9b2d23292c1e6660fe= 93c611e0cb837 100644 --- a/drivers/gpio/gpio-ts4800.c +++ b/drivers/gpio/gpio-ts4800.c @@ -51,8 +51,6 @@ static int ts4800_gpio_probe(struct platform_device *pdev) =20 chip->ngpio =3D ngpios; =20 - platform_set_drvdata(pdev, chip); - return devm_gpiochip_add_data(&pdev->dev, chip, NULL); } =20 --=20 2.48.1 From nobody Sat Oct 4 22:33:04 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2A542EF672 for ; Tue, 12 Aug 2025 12:12:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Avoid pulling in linux/of.h by using the generic device properties. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ts4800.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-ts4800.c b/drivers/gpio/gpio-ts4800.c index 86f7947ca9b2d23292c1e6660fe93c611e0cb837..f4ae87325393c909c66eda3bb7b= 2f849e645b7a4 100644 --- a/drivers/gpio/gpio-ts4800.c +++ b/drivers/gpio/gpio-ts4800.c @@ -7,8 +7,8 @@ =20 #include #include -#include #include +#include =20 #define DEFAULT_PIN_NUMBER 16 #define INPUT_REG_OFFSET 0x00 @@ -17,7 +17,7 @@ =20 static int ts4800_gpio_probe(struct platform_device *pdev) { - struct device_node *node; + struct device *dev =3D &pdev->dev; struct gpio_chip *chip; void __iomem *base_addr; int retval; @@ -31,11 +31,7 @@ static int ts4800_gpio_probe(struct platform_device *pde= v) if (IS_ERR(base_addr)) return PTR_ERR(base_addr); =20 - node =3D pdev->dev.of_node; - if (!node) - return -EINVAL; - - retval =3D of_property_read_u32(node, "ngpios", &ngpios); + retval =3D device_property_read_u32(dev, "ngpios", &ngpios); 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Tue, 12 Aug 2025 05:12:57 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:48 +0200 Subject: [PATCH RESEND 06/14] gpio: ts4800: use dev_err_probe() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-6-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=906; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=JVVbThM9xH2PXWbYe03tJE2jElHw1ibdCVrW+ltAkLs=; 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ts4800.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-ts4800.c b/drivers/gpio/gpio-ts4800.c index f4ae87325393c909c66eda3bb7b2f849e645b7a4..cb3eeeb1e9df9aa687e880b16f8= d0a31b04a3b07 100644 --- a/drivers/gpio/gpio-ts4800.c +++ b/drivers/gpio/gpio-ts4800.c @@ -40,10 +40,8 @@ static int ts4800_gpio_probe(struct platform_device *pde= v) retval =3D bgpio_init(chip, &pdev->dev, 2, base_addr + INPUT_REG_OFFSET, base_addr + OUTPUT_REG_OFFSET, NULL, base_addr + DIRECTION_REG_OFFSET, NULL, 0); - if (retval) { - dev_err(&pdev->dev, "bgpio_init failed\n"); - return retval; - } + if (retval) + return dev_err_probe(dev, retval, "bgpio_init failed\n"); =20 chip->ngpio =3D ngpios; =20 --=20 2.48.1 From nobody Sat Oct 4 22:33:04 2025 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D07612F1FE1 for ; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ts4800.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-ts4800.c b/drivers/gpio/gpio-ts4800.c index cb3eeeb1e9df9aa687e880b16f8d0a31b04a3b07..844347945e8e71fa0f456be0ba8= de7217f6760a3 100644 --- a/drivers/gpio/gpio-ts4800.c +++ b/drivers/gpio/gpio-ts4800.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -17,13 +18,14 @@ =20 static int ts4800_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; - struct gpio_chip *chip; + struct gpio_generic_chip *chip; void __iomem *base_addr; int retval; u32 ngpios; =20 - chip =3D devm_kzalloc(&pdev->dev, sizeof(struct gpio_chip), GFP_KERNEL); + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; =20 @@ -37,15 +39,22 @@ static int ts4800_gpio_probe(struct platform_device *pd= ev) else if (retval) return retval; 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Tue, 12 Aug 2025 05:13:00 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:16c8:50:27fe:4d94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e6867193sm298878535e9.6.2025.08.12.05.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 05:12:59 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:50 +0200 Subject: [PATCH RESEND 08/14] gpio: loongson-64bit: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-8-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-loongson-64bit.c | 42 ++++++++++++++++++++++------------= ---- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/gpio/gpio-loongson-64bit.c b/drivers/gpio/gpio-loongso= n-64bit.c index 818c606fbc5149b2e4274f0776e558332700d916..482e64ba9b4209443c2f64ae742= 6b8fa9034011a 100644 --- a/drivers/gpio/gpio-loongson-64bit.c +++ b/drivers/gpio/gpio-loongson-64bit.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -30,7 +31,7 @@ struct loongson_gpio_chip_data { }; =20 struct loongson_gpio_chip { - struct gpio_chip chip; + struct gpio_generic_chip chip; spinlock_t lock; void __iomem *reg_base; const struct loongson_gpio_chip_data *chip_data; @@ -38,7 +39,8 @@ struct loongson_gpio_chip { =20 static inline struct loongson_gpio_chip *to_loongson_gpio_chip(struct gpio= _chip *chip) { - return container_of(chip, struct loongson_gpio_chip, chip); + return container_of(to_gpio_generic_chip(chip), + struct loongson_gpio_chip, chip); } =20 static inline void loongson_commit_direction(struct loongson_gpio_chip *lg= pio, unsigned int pin, @@ -138,36 +140,40 @@ static int loongson_gpio_to_irq(struct gpio_chip *chi= p, unsigned int offset) static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chi= p *lgpio, void __iomem *reg_base) { + struct gpio_generic_chip_config config; int ret; =20 lgpio->reg_base =3D reg_base; if (lgpio->chip_data->mode =3D=3D BIT_CTRL_MODE) { - ret =3D bgpio_init(&lgpio->chip, dev, 8, - lgpio->reg_base + lgpio->chip_data->in_offset, - lgpio->reg_base + lgpio->chip_data->out_offset, - NULL, NULL, - lgpio->reg_base + lgpio->chip_data->conf_offset, - 0); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 8, + .dat =3D lgpio->reg_base + lgpio->chip_data->in_offset, + .set =3D lgpio->reg_base + lgpio->chip_data->out_offset, + .dirin =3D lgpio->reg_base + lgpio->chip_data->conf_offset, + }; + + ret =3D gpio_generic_chip_init(&lgpio->chip, &config); if (ret) { dev_err(dev, "unable to init generic GPIO\n"); return ret; } } else { - lgpio->chip.direction_input =3D loongson_gpio_direction_input; - lgpio->chip.get =3D loongson_gpio_get; - lgpio->chip.get_direction =3D loongson_gpio_get_direction; - lgpio->chip.direction_output =3D loongson_gpio_direction_output; - lgpio->chip.set =3D loongson_gpio_set; - lgpio->chip.parent =3D dev; + lgpio->chip.gc.direction_input =3D loongson_gpio_direction_input; + lgpio->chip.gc.get =3D loongson_gpio_get; + lgpio->chip.gc.get_direction =3D loongson_gpio_get_direction; + lgpio->chip.gc.direction_output =3D loongson_gpio_direction_output; + lgpio->chip.gc.set =3D loongson_gpio_set; + lgpio->chip.gc.parent =3D dev; spin_lock_init(&lgpio->lock); } =20 - lgpio->chip.label =3D lgpio->chip_data->label; - lgpio->chip.can_sleep =3D false; + lgpio->chip.gc.label =3D lgpio->chip_data->label; + lgpio->chip.gc.can_sleep =3D false; if (lgpio->chip_data->inten_offset) - lgpio->chip.to_irq =3D loongson_gpio_to_irq; + lgpio->chip.gc.to_irq =3D loongson_gpio_to_irq; =20 - return devm_gpiochip_add_data(dev, &lgpio->chip, lgpio); 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Tue, 12 Aug 2025 05:13:00 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:51 +0200 Subject: [PATCH RESEND 09/14] gpio: dwapb: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-9-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=13939; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=bJtZHBh+83sX2WnxophXL3lqiaxB1fbZNtH20byx7Cc=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBomy/AnYJuWsz30v00nAH6s4/F4QP10/gYP0EYB zrDitfavHKJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaJsvwAAKCRARpy6gFHHX cm2mEADEOVIS0r6KZZMd5jgCGz/UwMrPxOtdaBj09eROp2VUSveAatNTq4F9tmimo1FgMnWXc7l YmcDtqdZjolxNxYAcqUbzhHSqsKlmwMAh+QLnzUMelPwm3C6qQLHDmw8RsGb+h1N5+QVlQH4Q3b WCq+bAZui/KqF2sbuZRlZEINAZifcntIK1jak25iiGwuDivCxvOwTUfMrTQypPMdjwto3i+5tg+ MLypRjs8EzzqbyFCdpFqzW38Y8w3whbj29gQsOaQqh1Lc+igg6CEwk7T23WT2jZf53xuayicM4q +/LpYfO6qgQNIZsXPkBcFSzY8dr9Le3EKHz3Yfr3XSo8GcnITcu0pp29nCq6GV4Zwkg/7acrNVj JpMT2UCJ+G/pHVOTXsfFMs0LfSpL3JRuQbLEYJzhHhHLFDAIV/HjXuCYG+Va4uncRRfnlnuId+n bew4Rrvz6Hhthajd+NsP/+Lw06OY3Rj9a4Wm63bxGTlvW5yViqYZ0JiTJha8XVCX9ru1l0V8h5c JTMegxb96K1N0L6BaU5SdBcKOjJ4HEKCegWmzA1z+kjV8hLW4Sm6mWb0u3KwLRXaLnh11Yhfc8Y n+s3Uy35NKBPN3RBe+PiCcW2qvxG/N7USNRXuz3XdhAAOqlPy9WZzSMIQImETrQGQWLFY8RzH1D 4E/46U9kOn4Zy/A== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-dwapb.c | 160 +++++++++++++++++++++++++-----------------= ---- 1 file changed, 86 insertions(+), 74 deletions(-) diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c index 43b667b41f5dce4a1a971af4506146e4ffb59b25..0fb781ca9da29545dce23ddbdf3= bd5927c714b4c 100644 --- a/drivers/gpio/gpio-dwapb.c +++ b/drivers/gpio/gpio-dwapb.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -99,7 +100,7 @@ struct dwapb_gpio_port_irqchip { }; =20 struct dwapb_gpio_port { - struct gpio_chip gc; + struct gpio_generic_chip chip; struct dwapb_gpio_port_irqchip *pirq; struct dwapb_gpio *gpio; #ifdef CONFIG_PM_SLEEP @@ -107,8 +108,12 @@ struct dwapb_gpio_port { #endif unsigned int idx; }; -#define to_dwapb_gpio(_gc) \ - (container_of(_gc, struct dwapb_gpio_port, gc)->gpio) + +static inline struct dwapb_gpio *to_dwapb_gpio(struct gpio_chip *gc) +{ + return container_of(to_gpio_generic_chip(gc), + struct dwapb_gpio_port, chip)->gpio; +} =20 struct dwapb_gpio { struct device *dev; @@ -148,19 +153,19 @@ static inline u32 gpio_reg_convert(struct dwapb_gpio = *gpio, unsigned int offset) =20 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) { - struct gpio_chip *gc =3D &gpio->ports[0].gc; - void __iomem *reg_base =3D gpio->regs; + struct gpio_generic_chip *chip =3D &gpio->ports[0].chip; + void __iomem *reg_base =3D gpio->regs; =20 - return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); + return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offs= et)); } =20 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offse= t, u32 val) { - struct gpio_chip *gc =3D &gpio->ports[0].gc; - void __iomem *reg_base =3D gpio->regs; + struct gpio_generic_chip *chip =3D &gpio->ports[0].chip; + void __iomem *reg_base =3D gpio->regs; =20 - gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); + gpio_generic_write_reg(chip, reg_base + gpio_reg_convert(gpio, offset), v= al); } =20 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio,= unsigned int offs) @@ -186,7 +191,7 @@ static void dwapb_toggle_trigger(struct dwapb_gpio *gpi= o, unsigned int offs) =20 if (!port) return; - gc =3D &port->gc; + gc =3D &port->chip.gc; =20 pol =3D dwapb_read(gpio, GPIO_INT_POLARITY); /* Just read the current value right out of the data register */ @@ -201,13 +206,13 @@ static void dwapb_toggle_trigger(struct dwapb_gpio *g= pio, unsigned int offs) =20 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) { - struct gpio_chip *gc =3D &gpio->ports[0].gc; + struct gpio_generic_chip *gen_gc =3D &gpio->ports[0].chip; unsigned long irq_status; irq_hw_number_t hwirq; =20 irq_status =3D dwapb_read(gpio, GPIO_INTSTATUS); for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) { - int gpio_irq =3D irq_find_mapping(gc->irq.domain, hwirq); + int gpio_irq =3D irq_find_mapping(gen_gc->gc.irq.domain, hwirq); u32 irq_type =3D irq_get_trigger_type(gpio_irq); =20 generic_handle_irq(gpio_irq); @@ -237,27 +242,27 @@ static irqreturn_t dwapb_irq_handler_mfd(int irq, voi= d *dev_id) static void dwapb_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); u32 val =3D BIT(irqd_to_hwirq(d)); - unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + dwapb_write(gpio, GPIO_PORTA_EOI, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static void dwapb_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - val =3D dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); - dwapb_write(gpio, GPIO_INTMASK, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, gen_gc) { + val =3D dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); + dwapb_write(gpio, GPIO_INTMASK, val); + } =20 gpiochip_disable_irq(gc, hwirq); } @@ -265,59 +270,61 @@ static void dwapb_irq_mask(struct irq_data *d) static void dwapb_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; u32 val; =20 gpiochip_enable_irq(gc, hwirq); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + val =3D dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); dwapb_write(gpio, GPIO_INTMASK, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static void dwapb_irq_enable(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + val =3D dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq); dwapb_write(gpio, GPIO_INTEN, val); val =3D dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); dwapb_write(gpio, GPIO_INTMASK, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static void dwapb_irq_disable(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + val =3D dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); dwapb_write(gpio, GPIO_INTMASK, val); val =3D dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq); dwapb_write(gpio, GPIO_INTEN, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static int dwapb_irq_set_type(struct irq_data *d, u32 type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t bit =3D irqd_to_hwirq(d); - unsigned long level, polarity, flags; + unsigned long level, polarity; + + guard(gpio_generic_lock_irqsave)(gen_gc); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); level =3D dwapb_read(gpio, GPIO_INTTYPE_LEVEL); polarity =3D dwapb_read(gpio, GPIO_INT_POLARITY); =20 @@ -352,7 +359,6 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 t= ype) dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); if (type !=3D IRQ_TYPE_EDGE_BOTH) dwapb_write(gpio, GPIO_INT_POLARITY, polarity); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); =20 return 0; } @@ -393,11 +399,12 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *= gc, unsigned offset, unsigned debounce) { struct dwapb_gpio_port *port =3D gpiochip_get_data(gc); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D port->gpio; - unsigned long flags, val_deb; + unsigned long val_deb; unsigned long mask =3D BIT(offset); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); =20 val_deb =3D dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); if (debounce) @@ -406,8 +413,6 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc, val_deb &=3D ~mask; dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); - return 0; } =20 @@ -445,7 +450,7 @@ static void dwapb_configure_irqs(struct dwapb_gpio *gpi= o, struct dwapb_port_property *pp) { struct dwapb_gpio_port_irqchip *pirq; - struct gpio_chip *gc =3D &port->gc; + struct gpio_chip *gc =3D &port->chip.gc; struct gpio_irq_chip *girq; int err; =20 @@ -501,6 +506,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, struct dwapb_port_property *pp, unsigned int offs) { + struct gpio_generic_chip_config config; struct dwapb_gpio_port *port; void __iomem *dat, *set, *dirout; int err; @@ -519,32 +525,39 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpi= o, set =3D gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; dirout =3D gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRI= DE; =20 + config =3D (typeof(config)){ + .dev =3D gpio->dev, + .sz =3D 4, + .dat =3D dat, + .set =3D set, + .dirout =3D dirout, + }; + /* This registers 32 GPIO lines per port */ - err =3D bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, - NULL, 0); + err =3D gpio_generic_chip_init(&port->chip, &config); if (err) { dev_err(gpio->dev, "failed to init gpio chip for port%d\n", port->idx); return err; } =20 - port->gc.fwnode =3D pp->fwnode; - port->gc.ngpio =3D pp->ngpio; - port->gc.base =3D pp->gpio_base; - port->gc.request =3D gpiochip_generic_request; - port->gc.free =3D gpiochip_generic_free; + port->chip.gc.fwnode =3D pp->fwnode; + port->chip.gc.ngpio =3D pp->ngpio; + port->chip.gc.base =3D pp->gpio_base; + port->chip.gc.request =3D gpiochip_generic_request; + port->chip.gc.free =3D gpiochip_generic_free; =20 /* Only port A support debounce */ if (pp->idx =3D=3D 0) - port->gc.set_config =3D dwapb_gpio_set_config; + port->chip.gc.set_config =3D dwapb_gpio_set_config; else - port->gc.set_config =3D gpiochip_generic_config; + port->chip.gc.set_config =3D gpiochip_generic_config; =20 /* Only port A can provide interrupts in all configurations of the IP */ if (pp->idx =3D=3D 0) dwapb_configure_irqs(gpio, port, pp); =20 - err =3D devm_gpiochip_add_data(gpio->dev, &port->gc, port); + err =3D devm_gpiochip_add_data(gpio->dev, &port->chip.gc, port); if (err) { dev_err(gpio->dev, "failed to register gpiochip for port%d\n", port->idx); @@ -750,38 +763,37 @@ static int dwapb_gpio_probe(struct platform_device *p= dev) static int dwapb_gpio_suspend(struct device *dev) { struct dwapb_gpio *gpio =3D dev_get_drvdata(dev); - struct gpio_chip *gc =3D &gpio->ports[0].gc; - unsigned long flags; + struct gpio_generic_chip *gen_gc =3D &gpio->ports[0].chip; int i; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - for (i =3D 0; i < gpio->nr_ports; i++) { - unsigned int offset; - unsigned int idx =3D gpio->ports[i].idx; - struct dwapb_context *ctx =3D gpio->ports[i].ctx; + scoped_guard(gpio_generic_lock_irqsave, gen_gc) { + for (i =3D 0; i < gpio->nr_ports; i++) { + unsigned int offset; + unsigned int idx =3D gpio->ports[i].idx; + struct dwapb_context *ctx =3D gpio->ports[i].ctx; =20 - offset =3D GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; - ctx->dir =3D dwapb_read(gpio, offset); + offset =3D GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; + ctx->dir =3D dwapb_read(gpio, offset); =20 - offset =3D GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; - ctx->data =3D dwapb_read(gpio, offset); + offset =3D GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; + ctx->data =3D dwapb_read(gpio, offset); =20 - offset =3D GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; - ctx->ext =3D dwapb_read(gpio, offset); + offset =3D GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; + ctx->ext =3D dwapb_read(gpio, offset); =20 - /* Only port A can provide interrupts */ - if (idx =3D=3D 0) { - ctx->int_mask =3D dwapb_read(gpio, GPIO_INTMASK); - ctx->int_en =3D dwapb_read(gpio, GPIO_INTEN); - ctx->int_pol =3D dwapb_read(gpio, GPIO_INT_POLARITY); - ctx->int_type =3D dwapb_read(gpio, GPIO_INTTYPE_LEVEL); - ctx->int_deb =3D dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); + /* Only port A can provide interrupts */ + if (idx =3D=3D 0) { + ctx->int_mask =3D dwapb_read(gpio, GPIO_INTMASK); + ctx->int_en =3D dwapb_read(gpio, GPIO_INTEN); + ctx->int_pol =3D dwapb_read(gpio, GPIO_INT_POLARITY); + ctx->int_type =3D dwapb_read(gpio, GPIO_INTTYPE_LEVEL); + ctx->int_deb =3D dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); =20 - /* Mask out interrupts */ - dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); + /* Mask out interrupts */ + dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); + } } } - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); =20 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-amdpt.c | 44 +++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/gpio/gpio-amdpt.c b/drivers/gpio/gpio-amdpt.c index b70036587d9c3f64bb73ed3b94e1c14f249c9e21..0a9b870705b90bdc9bdab93ce5a= 4a33ebdafccc6 100644 --- a/drivers/gpio/gpio-amdpt.c +++ b/drivers/gpio/gpio-amdpt.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -24,54 +25,50 @@ #define PT_SYNC_REG 0x28 =20 struct pt_gpio_chip { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *reg_base; }; =20 static int pt_gpio_request(struct gpio_chip *gc, unsigned offset) { + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct pt_gpio_chip *pt_gpio =3D gpiochip_get_data(gc); - unsigned long flags; u32 using_pins; =20 dev_dbg(gc->parent, "pt_gpio_request offset=3D%x\n", offset); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); =20 using_pins =3D readl(pt_gpio->reg_base + PT_SYNC_REG); if (using_pins & BIT(offset)) { dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n", offset); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); return -EINVAL; } =20 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); - return 0; } =20 static void pt_gpio_free(struct gpio_chip *gc, unsigned offset) { + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct pt_gpio_chip *pt_gpio =3D gpiochip_get_data(gc); - unsigned long flags; u32 using_pins; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); =20 using_pins =3D readl(pt_gpio->reg_base + PT_SYNC_REG); using_pins &=3D ~BIT(offset); writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); - dev_dbg(gc->parent, "pt_gpio_free offset=3D%x\n", offset); } =20 static int pt_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct pt_gpio_chip *pt_gpio; int ret =3D 0; @@ -91,22 +88,27 @@ static int pt_gpio_probe(struct platform_device *pdev) return PTR_ERR(pt_gpio->reg_base); } =20 - ret =3D bgpio_init(&pt_gpio->gc, dev, 4, - pt_gpio->reg_base + PT_INPUTDATA_REG, - pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, - pt_gpio->reg_base + PT_DIRECTION_REG, NULL, - BGPIOF_READ_OUTPUT_REG_SET); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D pt_gpio->reg_base + PT_INPUTDATA_REG, + .set =3D pt_gpio->reg_base + PT_OUTPUTDATA_REG, + .dirout =3D pt_gpio->reg_base + PT_DIRECTION_REG, + .flags =3D BGPIOF_READ_OUTPUT_REG_SET, + }; + + ret =3D gpio_generic_chip_init(&pt_gpio->chip, &config); if (ret) { - dev_err(dev, "bgpio_init failed\n"); + dev_err(dev, "failed to initialize the generic GPIO chip\n"); return ret; } =20 - pt_gpio->gc.owner =3D THIS_MODULE; - pt_gpio->gc.request =3D pt_gpio_request; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-rda.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-rda.c b/drivers/gpio/gpio-rda.c index cb2f63eee2aa10a2708ec91dfd610ed1ea76917d..bcd85a2237a532b875df9470d97= 2ac88b95a91cc 100644 --- a/drivers/gpio/gpio-rda.c +++ b/drivers/gpio/gpio-rda.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -35,7 +36,7 @@ #define RDA_GPIO_BANK_NR 32 =20 struct rda_gpio { - struct gpio_chip chip; + struct gpio_generic_chip chip; void __iomem *base; spinlock_t lock; int irq; @@ -208,6 +209,7 @@ static const struct irq_chip rda_gpio_irq_chip =3D { =20 static int rda_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct gpio_irq_chip *girq; struct rda_gpio *rda_gpio; @@ -235,24 +237,29 @@ static int rda_gpio_probe(struct platform_device *pde= v) =20 spin_lock_init(&rda_gpio->lock); =20 - ret =3D bgpio_init(&rda_gpio->chip, dev, 4, - rda_gpio->base + RDA_GPIO_VAL, - rda_gpio->base + RDA_GPIO_SET, - rda_gpio->base + RDA_GPIO_CLR, - rda_gpio->base + RDA_GPIO_OEN_SET_OUT, - rda_gpio->base + RDA_GPIO_OEN_SET_IN, - BGPIOF_READ_OUTPUT_REG_SET); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D rda_gpio->base + RDA_GPIO_VAL, + .set =3D rda_gpio->base + RDA_GPIO_SET, + .clr =3D rda_gpio->base + RDA_GPIO_CLR, + .dirout =3D rda_gpio->base + RDA_GPIO_OEN_SET_OUT, + .dirin =3D rda_gpio->base + RDA_GPIO_OEN_SET_IN, + .flags =3D BGPIOF_READ_OUTPUT_REG_SET, + }; + + ret =3D gpio_generic_chip_init(&rda_gpio->chip, &config); if (ret) { - dev_err(dev, "bgpio_init failed\n"); + dev_err(dev, "failed to initialize the generic GPIO chip\n"); return ret; } =20 - rda_gpio->chip.label =3D dev_name(dev); - rda_gpio->chip.ngpio =3D ngpios; - rda_gpio->chip.base =3D -1; + rda_gpio->chip.gc.label =3D dev_name(dev); + rda_gpio->chip.gc.ngpio =3D ngpios; + rda_gpio->chip.gc.base =3D -1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-grgpio.c | 87 +++++++++++++++++++++++-------------------= ---- 1 file changed, 44 insertions(+), 43 deletions(-) diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c index f3f8bab62f94cefb69d31d76b961ab2d346df49e..3b77fad00749cd5218268b267b5= 848515c6a26fc 100644 --- a/drivers/gpio/gpio-grgpio.c +++ b/drivers/gpio/gpio-grgpio.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -59,7 +60,7 @@ struct grgpio_lirq { }; =20 struct grgpio_priv { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *regs; struct device *dev; =20 @@ -91,13 +92,12 @@ struct grgpio_priv { static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset, int val) { - struct gpio_chip *gc =3D &priv->gc; - if (val) priv->imask |=3D BIT(offset); else priv->imask &=3D ~BIT(offset); - gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); + + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IMASK, priv->imas= k); } =20 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset) @@ -118,7 +118,6 @@ static int grgpio_to_irq(struct gpio_chip *gc, unsigned= offset) static int grgpio_irq_set_type(struct irq_data *d, unsigned int type) { struct grgpio_priv *priv =3D irq_data_get_irq_chip_data(d); - unsigned long flags; u32 mask =3D BIT(d->hwirq); u32 ipol; u32 iedge; @@ -146,15 +145,13 @@ static int grgpio_irq_set_type(struct irq_data *d, un= signed int type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&priv->chip); =20 - ipol =3D priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask; - iedge =3D priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask; + ipol =3D gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IPOL) & ~= mask; + iedge =3D gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IEDGE) &= ~mask; =20 - priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol); - priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge); - - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IPOL, ipol | pol); + gpio_generic_write_reg(&priv->chip, priv->regs + GRGPIO_IEDGE, iedge | ed= ge); =20 return 0; } @@ -163,29 +160,23 @@ static void grgpio_irq_mask(struct irq_data *d) { struct grgpio_priv *priv =3D irq_data_get_irq_chip_data(d); int offset =3D d->hwirq; - unsigned long flags; =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &priv->chip) + grgpio_set_imask(priv, offset, 0); =20 - grgpio_set_imask(priv, offset, 0); - - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); - - gpiochip_disable_irq(&priv->gc, d->hwirq); + gpiochip_disable_irq(&priv->chip.gc, d->hwirq); } =20 static void grgpio_irq_unmask(struct irq_data *d) { struct grgpio_priv *priv =3D irq_data_get_irq_chip_data(d); int offset =3D d->hwirq; - unsigned long flags; =20 - gpiochip_enable_irq(&priv->gc, d->hwirq); - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + gpiochip_enable_irq(&priv->chip.gc, d->hwirq); + + guard(gpio_generic_lock_irqsave)(&priv->chip); =20 grgpio_set_imask(priv, offset, 1); - - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); } =20 static const struct irq_chip grgpio_irq_chip =3D { @@ -200,12 +191,11 @@ static const struct irq_chip grgpio_irq_chip =3D { static irqreturn_t grgpio_irq_handler(int irq, void *dev) { struct grgpio_priv *priv =3D dev; - int ngpio =3D priv->gc.ngpio; - unsigned long flags; + int ngpio =3D priv->chip.gc.ngpio; int i; int match =3D 0; =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&priv->chip); =20 /* * For each gpio line, call its interrupt handler if it its underlying @@ -221,8 +211,6 @@ static irqreturn_t grgpio_irq_handler(int irq, void *de= v) } } =20 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); - if (!match) dev_warn(priv->dev, "No gpio line matched irq %d\n", irq); =20 @@ -253,13 +241,18 @@ static int grgpio_irq_map(struct irq_domain *d, unsig= ned int irq, dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n", irq, offset); =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_lock_irqsave(&priv->chip, flags); =20 /* Request underlying irq if not already requested */ lirq->irq =3D irq; uirq =3D &priv->uirqs[lirq->index]; if (uirq->refcnt =3D=3D 0) { - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + /* + * FIXME: This is not how locking works at all, you can't just + * release the lock for a moment to do something that can't + * sleep... + */ + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); ret =3D request_irq(uirq->uirq, grgpio_irq_handler, 0, dev_name(priv->dev), priv); if (ret) { @@ -268,11 +261,11 @@ static int grgpio_irq_map(struct irq_domain *d, unsig= ned int irq, uirq->uirq); return ret; } - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_lock_irqsave(&priv->chip, flags); } uirq->refcnt++; =20 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); =20 /* Setup irq */ irq_set_chip_data(irq, priv); @@ -290,13 +283,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, un= signed int irq) struct grgpio_lirq *lirq; struct grgpio_uirq *uirq; unsigned long flags; - int ngpio =3D priv->gc.ngpio; + int ngpio =3D priv->chip.gc.ngpio; int i; =20 irq_set_chip_and_handler(irq, NULL, NULL); irq_set_chip_data(irq, NULL); =20 - raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_lock_irqsave(&priv->chip, flags); =20 /* Free underlying irq if last user unmapped */ index =3D -1; @@ -315,13 +308,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, un= signed int irq) uirq =3D &priv->uirqs[lirq->index]; uirq->refcnt--; if (uirq->refcnt =3D=3D 0) { - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); free_irq(uirq->uirq, priv); return; } } =20 - raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags); + gpio_generic_chip_unlock_irqrestore(&priv->chip, flags); } =20 static void grgpio_irq_domain_remove(void *data) @@ -341,6 +334,7 @@ static const struct irq_domain_ops grgpio_irq_domain_op= s =3D { static int grgpio_probe(struct platform_device *ofdev) { struct device_node *np =3D ofdev->dev.of_node; + struct gpio_generic_chip_config config; struct device *dev =3D &ofdev->dev; void __iomem *regs; struct gpio_chip *gc; @@ -359,17 +353,24 @@ static int grgpio_probe(struct platform_device *ofdev) if (IS_ERR(regs)) return PTR_ERR(regs); =20 - gc =3D &priv->gc; - err =3D bgpio_init(gc, dev, 4, regs + GRGPIO_DATA, - regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL, - BGPIOF_BIG_ENDIAN_BYTE_ORDER); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D regs + GRGPIO_DATA, + .set =3D regs + GRGPIO_OUTPUT, + .dirout =3D regs + GRGPIO_DIR, + .flags =3D BGPIOF_BIG_ENDIAN_BYTE_ORDER, + }; + + gc =3D &priv->chip.gc; + err =3D gpio_generic_chip_init(&priv->chip, &config); if (err) { - dev_err(dev, "bgpio_init() failed\n"); + dev_err(dev, "failed to initialize the generic GPIO chip\n"); return err; } =20 priv->regs =3D regs; - priv->imask =3D gc->read_reg(regs + GRGPIO_IMASK); + priv->imask =3D gpio_generic_read_reg(&priv->chip, regs + GRGPIO_IMASK); priv->dev =3D dev; =20 gc->owner =3D THIS_MODULE; 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Tue, 12 Aug 2025 05:13:05 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:55 +0200 Subject: [PATCH RESEND 13/14] gpio: mpc8xxx: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-13-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10008; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=8xlnAhAzfwO4+HhxnfhDkoiDZ7pkFtIamWGlMtDqlhM=; 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mpc8xxx.c | 102 +++++++++++++++++++++++++++-------------= ---- 1 file changed, 62 insertions(+), 40 deletions(-) diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 121efdd71e451d4f992fa195b0d56d7146a6f3dd..38643fb813c562957076aab48d8= 04f8048cee5e4 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,7 @@ #define GPIO_IBE 0x18 =20 struct mpc8xxx_gpio_chip { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *regs; raw_spinlock_t lock; =20 @@ -66,8 +67,10 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsign= ed int gpio) struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D gpiochip_get_data(gc); u32 out_mask, out_shadow; =20 - out_mask =3D gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); - val =3D gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; + out_mask =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_DIR); + val =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; out_shadow =3D gc->bgpio_data & out_mask; =20 return !!((val | out_shadow) & mpc_pin2mask(gpio)); @@ -108,12 +111,13 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, = unsigned offset) static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D data; - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; unsigned long mask; int i; =20 - mask =3D gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) - & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); + mask =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IER) & + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR); for_each_set_bit(i, &mask, 32) generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); =20 @@ -124,15 +128,17 @@ static void mpc8xxx_irq_unmask(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; + struct gpio_chip *gc =3D &mpc8xxx_gc->chip.gc; unsigned long flags; =20 gpiochip_enable_irq(gc, hwirq); =20 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); =20 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, - gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR, + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR) | mpc_pin2mask(irqd_to_hwirq(d))); =20 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); @@ -142,13 +148,14 @@ static void mpc8xxx_irq_mask(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; + struct gpio_chip *gc =3D &mpc8xxx_gc->chip.gc; unsigned long flags; =20 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); =20 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, - gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) + gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IMR, + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IMR) & ~mpc_pin2mask(irqd_to_hwirq(d))); =20 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); @@ -159,32 +166,34 @@ static void mpc8xxx_irq_mask(struct irq_data *d) static void mpc8xxx_irq_ack(struct irq_data *d) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; =20 - gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, + gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IER, mpc_pin2mask(irqd_to_hwirq(d))); } =20 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; unsigned long flags; =20 switch (flow_type) { case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, - gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_ICR, + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_ICR) | mpc_pin2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; =20 case IRQ_TYPE_EDGE_BOTH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, - gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_ICR, + gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_ICR) & ~mpc_pin2mask(irqd_to_hwirq(d))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; @@ -199,7 +208,6 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, uns= igned int flow_type) static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) { struct mpc8xxx_gpio_chip *mpc8xxx_gc =3D irq_data_get_irq_chip_data(d); - struct gpio_chip *gc =3D &mpc8xxx_gc->gc; unsigned long gpio =3D irqd_to_hwirq(d); void __iomem *reg; unsigned int shift; @@ -217,7 +225,9 @@ static int mpc512x_irq_set_type(struct irq_data *d, uns= igned int flow_type) case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, + (gpio_generic_read_reg(&mpc8xxx_gc->chip, + reg) & ~(3 << shift)) | (2 << shift)); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; @@ -225,14 +235,18 @@ static int mpc512x_irq_set_type(struct irq_data *d, u= nsigned int flow_type) case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, + (gpio_generic_read_reg(&mpc8xxx_gc->chip, + reg) & ~(3 << shift)) | (1 << shift)); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; =20 case IRQ_TYPE_EDGE_BOTH: raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); - gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); + gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, + (gpio_generic_read_reg(&mpc8xxx_gc->chip, + reg) & ~(3 << shift))); raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); break; =20 @@ -309,6 +323,7 @@ static const struct of_device_id mpc8xxx_gpio_ids[] =3D= { static int mpc8xxx_probe(struct platform_device *pdev) { const struct mpc8xxx_gpio_devtype *devtype =3D NULL; + struct gpio_generic_chip_config config; struct mpc8xxx_gpio_chip *mpc8xxx_gc; struct device *dev =3D &pdev->dev; struct fwnode_handle *fwnode; @@ -327,26 +342,28 @@ static int mpc8xxx_probe(struct platform_device *pdev) if (IS_ERR(mpc8xxx_gc->regs)) return PTR_ERR(mpc8xxx_gc->regs); =20 - gc =3D &mpc8xxx_gc->gc; + gc =3D &mpc8xxx_gc->chip.gc; gc->parent =3D dev; =20 + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D mpc8xxx_gc->regs + GPIO_DAT, + .dirout =3D mpc8xxx_gc->regs + GPIO_DIR, + .flags =3D BGPIOF_BIG_ENDIAN + }; + if (device_property_read_bool(dev, "little-endian")) { - ret =3D bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, - NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, - NULL, BGPIOF_BIG_ENDIAN); - if (ret) - return ret; dev_dbg(dev, "GPIO registers are LITTLE endian\n"); } else { - ret =3D bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, - NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, - NULL, BGPIOF_BIG_ENDIAN - | BGPIOF_BIG_ENDIAN_BYTE_ORDER); - if (ret) - return ret; + config.flags |=3D BGPIOF_BIG_ENDIAN_BYTE_ORDER; dev_dbg(dev, "GPIO registers are BIG endian\n"); } =20 + ret =3D gpio_generic_chip_init(&mpc8xxx_gc->chip, &config); + if (ret) + return ret; + mpc8xxx_gc->direction_output =3D gc->direction_output; =20 devtype =3D device_get_match_data(dev); @@ -379,10 +396,13 @@ static int mpc8xxx_probe(struct platform_device *pdev) device_is_compatible(dev, "fsl,ls1028a-gpio") || device_is_compatible(dev, "fsl,ls1088a-gpio") || is_acpi_node(fwnode)) { - gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); + gpio_generic_write_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); /* Also, latch state of GPIOs configured as output by bootloader. */ - gc->bgpio_data =3D gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & - gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 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Tue, 12 Aug 2025 05:13:08 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:16c8:50:27fe:4d94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459e6867193sm298878535e9.6.2025.08.12.05.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 05:13:08 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 12 Aug 2025 14:12:56 +0200 Subject: [PATCH RESEND 14/14] gpio: ge: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-gpio-mmio-gpio-conv-v1-14-aac41d656979@linaro.org> References: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> In-Reply-To: <20250812-gpio-mmio-gpio-conv-v1-0-aac41d656979@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ge.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-ge.c b/drivers/gpio/gpio-ge.c index 5dc49648d8e378e9741213f9c2de05b4c75b347f..a02dd322e0d4cecd4564a71a550= 204983df33568 100644 --- a/drivers/gpio/gpio-ge.c +++ b/drivers/gpio/gpio-ge.c @@ -16,6 +16,7 @@ */ =20 #include +#include #include #include #include @@ -51,24 +52,36 @@ MODULE_DEVICE_TABLE(of, gef_gpio_ids); =20 static int __init gef_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; + struct gpio_generic_chip *chip; struct gpio_chip *gc; void __iomem *regs; int ret; =20 - gc =3D devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); - if (!gc) + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) return -ENOMEM; =20 regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) return PTR_ERR(regs); =20 - ret =3D bgpio_init(gc, dev, 4, regs + GEF_GPIO_IN, regs + GEF_GPIO_OUT, - NULL, NULL, regs + GEF_GPIO_DIRECT, - BGPIOF_BIG_ENDIAN_BYTE_ORDER); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D regs + GEF_GPIO_IN, + .set =3D regs + GEF_GPIO_OUT, + .dirin =3D regs + GEF_GPIO_DIRECT, + .flags =3D BGPIOF_BIG_ENDIAN_BYTE_ORDER, + }; + + ret =3D gpio_generic_chip_init(chip, &config); if (ret) - return dev_err_probe(dev, ret, "bgpio_init failed\n"); + return dev_err_probe(dev, ret, + "failed to initialize the generic GPIO chip\n"); + + gc =3D &chip->gc; =20 /* Setup pointers to chip functions */ gc->label =3D devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev)); --=20 2.48.1