From nobody Sat Oct 4 20:54:34 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D6E6283CBE; Tue, 12 Aug 2025 13:51:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006682; cv=none; b=d1Sq5+oi47fCl4Zy9YEZGyIwpD2KLJASa077Z79T6U7MHw3AyfH6wzyosaXXoSEUawQUK67NpOtClgZFyF8De5dPuFNMExS59UGT7ZArNmzym4LruZ5PctJyHGd2Gc1WYNX3xvmooimnRyCzTBKbvgG6jSc41ibLq/zOfN8o4Qo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006682; c=relaxed/simple; bh=QtFiPQwqtfUKyUgZ4mcLcBYZnt2tbvlUxmUGzUjf1bI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=hwsGD7SVQuxlP6L8RBiA9H4LLL16GwH8U72+/XnXqMqKS9WzGlafVI0itmfAE5MG6fndJxK8h/eCO6V0ygmmNYb8/MwRLCJaSzrLKXNFTR4ud17F1Y6GPbSs3U2ls9RatdFekTrpLpRs5X7g6g7cdhO5GIG83yVpn/dXk166/3Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=C7rCuNp6; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="C7rCuNp6" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57CDRMS5015833; Tue, 12 Aug 2025 15:50:55 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= oAwGtXCt61vEDQiPJGllj41kqCZRlmT4VkAeHMFPj6A=; b=C7rCuNp6A46dMf4A eFvlqfFy4VflaF/wdnMrk3vRW92ZwfO7FOvuZV+FDBZWVFhltgT5hTPoDORpHzo0 mxLRJgqXxum0ew9/femmUzIKekhC7q9yCM/nmHVeAeTiqEyHkLr/wFsOGeL6gEbA i1oAW22nAmVVBfm7tXeg0xuWuhXZ6Z/YwH4C7RVuQ36QMcyrHcXYus1RIl9gI/po oNszow1F+ol+N4iHSUq6XCSplrXDlY08RbelTUwaxyPD2krMnRF+sNsX3RamNWgx xSSxPc89eZeOzeS7yk0KKz2iSIHHXvH0efJwfo0Oh0NEcTxPWTYchicMj5m/hFHi uJY3pA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48dw7gad8j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Aug 2025 15:50:55 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 70AF64004B; Tue, 12 Aug 2025 15:49:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6F14278B509; Tue, 12 Aug 2025 15:49:00 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:00 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:48:58 +0200 Subject: [PATCH v2 01/13] dt-bindings: display: st: add new compatible to LTDC device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-1-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 The new STMicroelectronics SoC features a display controller similar to the one used in previous SoCs. Because there is additional registers, it is incompatible with existing IPs. Add the new name to the list of compatible string. Signed-off-by: Raphael Gallais-Pou --- .../devicetree/bindings/display/st,stm32-ltdc.yaml | 30 ++++++++++++++++++= ++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b= /Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index d6ea4d62a2cfae26353c9f20a326a4329fed3a2f..33e814f8b85679a09df697246d2= f8ccdbfc44223 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -12,7 +12,9 @@ maintainers: =20 properties: compatible: - const: st,stm32-ltdc + enum: + - st,stm32-ltdc + - st,stm32mp251-ltdc =20 reg: maxItems: 1 @@ -24,11 +26,16 @@ properties: minItems: 1 =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 =20 clock-names: items: - const: lcd + - const: bus + - const: ref + - const: lvds + minItems: 1 =20 resets: maxItems: 1 @@ -51,6 +58,25 @@ required: - resets - port =20 +if: + properties: + compatible: + contains: + enum: + - st,stm32-ltdc +then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 +else: + properties: + clocks: + maxItems: 4 + clock-names: + maxItems: 4 + additionalProperties: false =20 examples: --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCFBF283FFA; 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Tue, 12 Aug 2025 15:50:55 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 66BC240045; Tue, 12 Aug 2025 15:49:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1980D78BFD9; Tue, 12 Aug 2025 15:49:01 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:00 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:48:59 +0200 Subject: [PATCH v2 02/13] dt-bindings: display: st,stm32-ltdc: add access-controllers property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-2-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b= /Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index 33e814f8b85679a09df697246d2f8ccdbfc44223..0ff47ac48ec655c1d126e16922e= f37e9c739dbea 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -40,6 +40,9 @@ properties: resets: maxItems: 1 =20 + access-controllers: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port description: | --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D65427FD7C; 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Tue, 12 Aug 2025 15:50:55 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 65DD640044; Tue, 12 Aug 2025 15:49:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B48C878C456; Tue, 12 Aug 2025 15:49:01 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:01 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:00 +0200 Subject: [PATCH v2 03/13] dt-bindings: display: st: add new compatible to LVDS device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-3-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 Update the compatible to accept both "st,stm32mp255-lvds" and st,stm32mp25-lvds" respectively. Default will fall back to "st,stm32mp25-lvds". Signed-off-by: Raphael Gallais-Pou Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 8 +++++= ++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 6736f93256b5cebb558cda5250369ec4b1b3033c..b777c55626e4b322d77ef411ad9= e4a3afb6c9131 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -31,7 +31,13 @@ description: | =20 properties: compatible: - const: st,stm32mp25-lvds + oneOf: + - items: + - enum: + - st,stm32mp255-lvds + - const: st,stm32mp25-lvds + - items: + - const: st,stm32mp25-lvds =20 "#clock-cells": const: 0 --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D5EE27FD59; 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Tue, 12 Aug 2025 15:50:55 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EC7D840071; Tue, 12 Aug 2025 15:49:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5A66078BFD2; Tue, 12 Aug 2025 15:49:02 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:02 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:01 +0200 Subject: [PATCH v2 04/13] dt-bindings: display: st,stm32mp25-lvds: add access-controllers property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-4-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index b777c55626e4b322d77ef411ad9e4a3afb6c9131..96fa0cb5cb86c41d978c4093448= afa3bb2a946fa 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -60,6 +60,9 @@ properties: resets: maxItems: 1 =20 + access-controllers: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97B5245C0B; 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Tue, 12 Aug 2025 15:50:58 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C5DF040073; Tue, 12 Aug 2025 15:49:25 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 04F4078C44D; Tue, 12 Aug 2025 15:49:03 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:02 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:02 +0200 Subject: [PATCH v2 05/13] dt-bindings: display: st,stm32mp25-lvds: add power-domains property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-5-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 STM32 LVDS peripheral may be in a power domain. Allow an optional single 'power-domains' entry for STM32 LVDS devices. Acked-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 96fa0cb5cb86c41d978c4093448afa3bb2a946fa..e9f4be172180b1de9e6b750e8e7= c8103d6838798 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -63,6 +63,9 @@ properties: access-controllers: maxItems: 1 =20 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79351284B58; 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Tue, 12 Aug 2025 15:50:58 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C31134006E; Tue, 12 Aug 2025 15:49:25 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A3C4878BFD5; Tue, 12 Aug 2025 15:49:03 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:03 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:03 +0200 Subject: [PATCH v2 06/13] dt-bindings: arm: stm32: add required #clock-cells property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-6-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Reviewed-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 +++++++++++++++---= ---- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.ya= ml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c84922813e94b1818c07fe8714891c089..95d2319afe235fa86974d80f89c= 9deeae2275232 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 =20 + "#clock-cells": + const: 0 + required: - compatible - reg =20 -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" =20 additionalProperties: false =20 --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1F1E283FF8; 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Tue, 12 Aug 2025 15:50:58 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D3B5940074; Tue, 12 Aug 2025 15:49:25 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 51D3B78C454; Tue, 12 Aug 2025 15:49:04 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:04 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:04 +0200 Subject: [PATCH v2 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-7-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 From: Yannick Fertre STM32MP25 SoC features a new version of the LTDC IP. Add its compatible to the list of device to probe and implement its quirks. This hardware supports a pad frequency of 150MHz and a peripheral bus clock. Signed-off-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/drv.c | 11 ++++++++++- drivers/gpu/drm/stm/ltdc.c | 37 ++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/stm/ltdc.h | 5 +++++ 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c index 8ebcaf953782d806a738d5a41ff1f428b0ccff78..8bfdeb486862a95df77427d25ce= 373e69e886c01 100644 --- a/drivers/gpu/drm/stm/drv.c +++ b/drivers/gpu/drm/stm/drv.c @@ -236,8 +236,17 @@ static void stm_drm_platform_shutdown(struct platform_= device *pdev) drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); } =20 +static struct ltdc_plat_data stm_drm_plat_data =3D { + .pad_max_freq_hz =3D 90000000, +}; + +static struct ltdc_plat_data stm_drm_plat_data_mp25 =3D { + .pad_max_freq_hz =3D 150000000, +}; + static const struct of_device_id drv_dt_ids[] =3D { - { .compatible =3D "st,stm32-ltdc"}, + { .compatible =3D "st,stm32-ltdc", .data =3D &stm_drm_plat_data, }, + { .compatible =3D "st,stm32mp251-ltdc", .data =3D &stm_drm_plat_data_mp25= , }, { /* end node */ }, }; MODULE_DEVICE_TABLE(of, drv_dt_ids); diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index ba315c66a04d72758b9d3cfcd842432877f66d3a..74e93f076b62a46e7835985d9d3= 30ba66d990e58 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,7 @@ #define HWVER_10300 0x010300 #define HWVER_20101 0x020101 #define HWVER_40100 0x040100 +#define HWVER_40101 0x040101 =20 /* * The address of some registers depends on the HW version: such registers= have @@ -1779,6 +1781,7 @@ static int ltdc_get_caps(struct drm_device *ddev) { struct ltdc_device *ldev =3D ddev->dev_private; u32 bus_width_log2, lcr, gc2r; + const struct ltdc_plat_data *pdata =3D of_device_get_match_data(ddev->dev= ); =20 /* * at least 1 layer must be managed & the number of layers @@ -1794,6 +1797,8 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.bus_width =3D 8 << bus_width_log2; regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); =20 + ldev->caps.pad_max_freq_hz =3D pdata->pad_max_freq_hz; + switch (ldev->caps.hw_version) { case HWVER_10200: case HWVER_10300: @@ -1811,7 +1816,6 @@ static int ltdc_get_caps(struct drm_device *ddev) * does not work on 2nd layer. */ ldev->caps.non_alpha_only_l1 =3D true; - ldev->caps.pad_max_freq_hz =3D 90000000; if (ldev->caps.hw_version =3D=3D HWVER_10200) ldev->caps.pad_max_freq_hz =3D 65000000; ldev->caps.nb_irq =3D 2; @@ -1842,6 +1846,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.fifo_threshold =3D false; break; case HWVER_40100: + case HWVER_40101: ldev->caps.layer_ofs =3D LAY_OFS_1; ldev->caps.layer_regs =3D ltdc_layer_regs_a2; ldev->caps.pix_fmt_hw =3D ltdc_pix_fmt_a2; @@ -1849,7 +1854,6 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.pix_fmt_nb =3D ARRAY_SIZE(ltdc_drm_fmt_a2); ldev->caps.pix_fmt_flex =3D true; ldev->caps.non_alpha_only_l1 =3D false; - ldev->caps.pad_max_freq_hz =3D 90000000; ldev->caps.nb_irq =3D 2; ldev->caps.ycbcr_input =3D true; ldev->caps.ycbcr_output =3D true; @@ -1872,6 +1876,8 @@ void ltdc_suspend(struct drm_device *ddev) =20 DRM_DEBUG_DRIVER("\n"); clk_disable_unprepare(ldev->pixel_clk); + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1887,7 +1893,13 @@ int ltdc_resume(struct drm_device *ddev) return ret; } =20 - return 0; + if (ldev->bus_clk) { + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) + drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + } + + return ret; } =20 int ltdc_load(struct drm_device *ddev) @@ -1922,6 +1934,19 @@ int ltdc_load(struct drm_device *ddev) return -ENODEV; } =20 + if (of_device_is_compatible(np, "st,stm32mp251-ltdc")) { + ldev->bus_clk =3D devm_clk_get(dev, "bus"); + if (IS_ERR(ldev->bus_clk)) + return dev_err_probe(dev, PTR_ERR(ldev->bus_clk), + "Unable to get bus clock\n"); + + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) { + drm_err(ddev, "Unable to prepare bus clock\n"); + return ret; + } + } + /* Get endpoints if any */ for (i =3D 0; i < nb_endpoints; i++) { ret =3D drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); @@ -2034,6 +2059,9 @@ int ltdc_load(struct drm_device *ddev) =20 clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + pinctrl_pm_select_sleep_state(ddev->dev); =20 pm_runtime_enable(ddev->dev); @@ -2042,6 +2070,9 @@ int ltdc_load(struct drm_device *ddev) err: clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + return ret; } =20 diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 9d488043ffdbc652deeede71c9d57d45fb89d3c6..ddfa8ae61a7ba5dc446fae64756= 2d0ec8e6953e1 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -40,10 +40,15 @@ struct fps_info { ktime_t last_timestamp; }; =20 +struct ltdc_plat_data { + int pad_max_freq_hz; /* max frequency supported by pad */ +}; + struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; /* lcd pixel clock */ + struct clk *bus_clk; /* bus clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps; u32 irq_status; --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BC1F288526; Tue, 12 Aug 2025 13:51:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006689; cv=none; b=jDbP6qzgpoEzS4Oq2b/qyJGuCtaCxopTPsM+Sbv3dFD0GHHueaHHvy2s+2DRmGB9wqukomNcnAs0UZ6PNFxwkwUJs0hdFvzENvANq+PzZSmbkNklk1pI4LpDWgHTherVrcV2Oq8I0qwpTemiJxaRCrN8sgIwFy6swPxiDFbIY8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755006689; c=relaxed/simple; bh=M1epPi1z75So7wCDT7hunVpp0NtGO9StJqs3OghkwYI=; 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Tue, 12 Aug 2025 15:49:26 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EB83878C44F; Tue, 12 Aug 2025 15:49:04 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:04 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:05 +0200 Subject: [PATCH v2 08/13] drm/stm: ltdc: handle lvds pixel clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-8-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 From: Yannick Fertre Handle LVDS pixel clock. The LTDC operates with multiple clock domains for register access, requiring all clocks to be provided during read/write operations. This imposes a dependency between the LVDS and LTDC to access correctly all LTDC registers. And because both IPs' pixel rates must be synchronized, the LTDC has to handle the LVDS clock. Signed-off-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/ltdc.c | 22 +++++++++++++++++++++- drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 74e93f076b62a46e7835985d9d330ba66d990e58..a4c2a1e960fbe426bf5dd2b3f0a= 88ccff927d041 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -837,6 +837,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, int target_max =3D target + CLK_TOLERANCE_HZ; int result; =20 + if (ldev->lvds_clk) { + result =3D clk_round_rate(ldev->lvds_clk, target); + drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", + target, result); + } + result =3D clk_round_rate(ldev->pixel_clk, target); =20 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); @@ -1878,6 +1884,8 @@ void ltdc_suspend(struct drm_device *ddev) clk_disable_unprepare(ldev->pixel_clk); if (ldev->bus_clk) clk_disable_unprepare(ldev->bus_clk); + if (ldev->lvds_clk) + clk_disable_unprepare(ldev->lvds_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1895,8 +1903,16 @@ int ltdc_resume(struct drm_device *ddev) =20 if (ldev->bus_clk) { ret =3D clk_prepare_enable(ldev->bus_clk); - if (ret) + if (ret) { drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + return ret; + } + } + + if (ldev->lvds_clk) { + ret =3D clk_prepare_enable(ldev->lvds_clk); + if (ret) + drm_err(ddev, "failed to prepare lvds clock\n"); } =20 return ret; @@ -1980,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev) } } =20 + ldev->lvds_clk =3D devm_clk_get(dev, "lvds"); + if (IS_ERR(ldev->lvds_clk)) + ldev->lvds_clk =3D NULL; + rstc =3D devm_reset_control_get_exclusive(dev, NULL); =20 mutex_init(&ldev->err_lock); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1..17b51a7ce28eee5de6d24ca943c= a3b1f48695dfd 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -48,6 +48,7 @@ struct ltdc_device { void __iomem *regs; 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It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 8d87865850a7a6e8095c36acdef83c8e3a73ae54..6e8f76aa4680d5c253bae882edc= 455f4e95413f3 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1052,6 +1052,18 @@ dcmipp: dcmipp@48030000 { status =3D "disabled"; }; =20 + ltdc: display-controller@48010000 { + compatible =3D "st,stm32mp251-ltdc"; + reg =3D <0x48010000 0x400>; + interrupts =3D , + ; + clocks =3D <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; + clock-names =3D "lcd", "bus"; + resets =3D <&rcc LTDC_R>; + access-controllers =3D <&rifsc 80>; + status =3D "disabled"; + }; + combophy: phy@480c0000 { compatible =3D "st,stm32mp25-combophy"; reg =3D <0x480c0000 0x1000>; --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80EBF288514; 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Tue, 12 Aug 2025 15:51:10 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9368640078; Tue, 12 Aug 2025 15:49:27 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 340F478C455; Tue, 12 Aug 2025 15:49:06 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:05 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:07 +0200 Subject: [PATCH v2 10/13] arm64: dts: st: add lvds support on stm32mp255 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-10-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 The LVDS is used on STM32MP2 as a display interface. Add the LVDS node. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp255.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index f689b47c5010033120146cf1954d6624c0270045..a3b5ae25d28c83ade12c2ff69b8= 2c9cccfd29b00 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -6,6 +6,18 @@ #include "stm32mp253.dtsi" =20 &rifsc { + lvds: lvds@48060000 { + compatible =3D "st,stm32mp255-lvds", "st,stm32mp25-lvds"; + #clock-cells =3D <0>; + reg =3D <0x48060000 0x2000>; + clocks =3D <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names =3D "pclk", "ref"; + resets =3D <&rcc LVDS_R>; + access-controllers =3D <&rifsc 84>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + vdec: vdec@480d0000 { compatible =3D "st,stm32mp25-vdec"; reg =3D <0x480d0000 0x3c8>; @@ -22,4 +34,4 @@ venc: venc@480e0000 { clocks =3D <&rcc CK_BUS_VENC>; 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Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 6e8f76aa4680d5c253bae882edc455f4e95413f3..d833b2b7904bef1cf1db8f1da21= 0a1abd8a87d09 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1344,6 +1344,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible =3D "st,stm32mp25-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; + #clock-cells =3D <0>; }; =20 pinctrl: pinctrl@44240000 { --=20 2.25.1 From nobody Sat Oct 4 20:54:34 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0A58283FF8; Tue, 12 Aug 2025 13:51:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 12 Aug 2025 15:51:10 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E6BAF400AC; Tue, 12 Aug 2025 15:49:27 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7DF0B765D1F; Tue, 12 Aug 2025 15:49:07 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:07 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:09 +0200 Subject: [PATCH v2 12/13] arm64: dts: st: enable display support on stm32mp257f-ev1 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-12-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 2f561ad4066544445e93db78557bc4be1c27095a..b324b0c226ddf043e62f0124524= 0f3e8d2b0a53c 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -86,6 +86,43 @@ mm_ospi1: mm-ospi@60000000 { no-map; }; }; + + panel_lvds: display { + compatible =3D "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios =3D <&gpiog 15 GPIO_ACTIVE_HIGH>; + backlight =3D <&panel_lvds_backlight>; + power-supply =3D <&scmi_v3v3>; + status =3D "okay"; + + width-mm =3D <156>; + height-mm =3D <92>; + data-mapping =3D "vesa-24"; + + panel-timing { + clock-frequency =3D <54000000>; + hactive =3D <1024>; + vactive =3D <600>; + hfront-porch =3D <150>; + hback-porch =3D <150>; + hsync-len =3D <21>; + vfront-porch =3D <24>; + vback-porch =3D <24>; + vsync-len =3D <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint =3D <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible =3D "gpio-backlight"; + gpios =3D <&gpioi 5 GPIO_ACTIVE_HIGH>; + default-on; + status =3D "okay"; + }; }; =20 &arm_wdt { @@ -183,6 +220,15 @@ imx335_ep: endpoint { }; }; }; + + ili2511: ili2511@41 { + compatible =3D "ilitek,ili251x"; + reg =3D <0x41>; + interrupt-parent =3D <&gpioi>; + interrupts =3D <13 IRQ_TYPE_EDGE_FALLING>; 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Tue, 12 Aug 2025 15:51:10 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E6CE7400AE; Tue, 12 Aug 2025 15:49:27 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2486678C45C; Tue, 12 Aug 2025 15:49:08 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 15:49:07 +0200 From: Raphael Gallais-Pou Date: Tue, 12 Aug 2025 15:49:10 +0200 Subject: [PATCH v2 13/13] arm64: dts: st: add loopback clocks on LTDC node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250812-drm-misc-next-v2-13-132fd84463d7@foss.st.com> References: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> In-Reply-To: <20250812-drm-misc-next-v2-0-132fd84463d7@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_07,2025-08-11_01,2025-03-28_01 ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock. Add the clocks needed for the LTDC to work. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index d833b2b7904bef1cf1db8f1da210a1abd8a87d09..55f63cb7b881a91498042a71fcd= 39ac5191ad47d 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ clk_rcbsec: clk-rcbsec { compatible =3D "fixed-clock"; clock-frequency =3D <64000000>; }; + + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <54000000>; + }; }; =20 firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index a3b5ae25d28c83ade12c2ff69b82c9cccfd29b00..07c200470b2cedde771ae987f22= 67d6097ea78f0 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,6 +5,11 @@ */ #include "stm32mp253.dtsi" =20 +<dc { + clocks =3D <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds= >; + clock-names =3D "lcd", "bus", "ref", "lvds"; +}; + &rifsc { lvds: lvds@48060000 { compatible =3D "st,stm32mp255-lvds", "st,stm32mp25-lvds"; --=20 2.25.1