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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0aa1efe78sm76186821cf.8.2025.08.12.07.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 07:40:51 -0700 (PDT) From: Brian Masney Date: Tue, 12 Aug 2025 10:40:31 -0400 Subject: [PATCH v3 1/9] clk: add kernel docs for struct clk_core Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-clk-tests-docs-v3-1-054aed58dcd3@redhat.com> References: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> In-Reply-To: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755009649; l=4276; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=dCRqataLA66dZJ1YRHlWTY3qoxuRgsndmQxu0wuYWhA=; b=oYaK35NUukGmkDI7mBbltcQ75razu+JbR47JwXDr1gECCF1sVqMWwKb+m+OjRJ15VmTltfH3X ugTMGFoIYW2DIQWzBZQz7WcqlyUxSmyw2aT25DvUDyQGDbFIMZpfoXV X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Document all of the members of struct clk_core. Signed-off-by: Brian Masney Reviewed-by: Maxime Ripard --- drivers/clk/clk.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 55 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index b821b2cdb155331c85fafbd2fac8ab3703a08e4d..41690448ce9ada8eaa30221950d= a4a3b1c4552d2 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -57,6 +57,61 @@ struct clk_parent_map { int index; }; =20 +/** + * struct clk_core - This structure represents the internal state of a clk + * within the kernel's clock tree. Drivers do not interact with this struc= ture + * directly. The clk_core is manipulated by the framework to manage clock + * operations, parent/child relationships, rate, and other properties. + * + * @name: Unique name of the clk for identification. + * @ops: Pointer to hardware-specific operations for this cl= k. + * @hw: Pointer for traversing from a struct clk to its + * corresponding hardware-specific structure. + * @owner: Kernel module owning this clk (for reference counti= ng). + * @dev: Device associated with this clk (optional) + * @rpm_node: Node for runtime power management list management. + * @of_node: Device tree node associated with this clk (if appli= cable) + * @parent: Pointer to the current parent in the clock tree. + * @parents: Array of possible parents (for muxes/selectable par= ents). + * @num_parents: Number of possible parents + * @new_parent_index: Index of the new parent during parent change. + * @rate: Current clock rate (Hz). This is effectively a cach= ed + * value of what the hardware has been programmed with= . It's + * initialized by reading the value at boot time, and = will + * be updated every time an operation affects the rate. + * Clocks with the CLK_GET_RATE_NOCACHE flag should no= t use + * this value, as its rate is expected to change behin= d the + * kernel's back (because the firmware might change it= , for + * example). Also, if the clock is orphan, it's set to= 0 + * and updated when (and if) its parent is later loade= d, so + * its content is only ever valid if clk_core->orphan = is + * false. + * @req_rate: The last rate requested by a call to clk_set_rate. = It's + * initialized to clk_core->rate. It's also updated to + * clk_core->rate every time the clock is reparented, = and + * when we're doing the orphan -> !orphan transition. + * @new_rate: New rate to be set during a rate change operation. + * @new_parent: Pointer to new parent during parent change. + * @new_child: Pointer to new child during reparenting. + * @flags: Clock property and capability flags. + * @orphan: True if this clk is currently orphaned. + * @rpm_enabled: True if runtime power management is enabled for thi= s clk. + * @enable_count: Reference count of enables. + * @prepare_count: Reference count of prepares. + * @protect_count: Protection reference count against disable. + * @min_rate: Minimum supported clock rate (Hz). + * @max_rate: Maximum supported clock rate (Hz). + * @accuracy: Accuracy of the clock rate (parts per billion). + * @phase: Current phase (degrees). + * @duty: Current duty cycle configuration. + * @children: All of the children of this clk. + * @child_node: Node for linking as a child in the parent's list. + * @clks: All of the clk consumers registered. + * @notifier_count: Number of notifiers registered for this clk. + * @dentry: DebugFS entry for this clk. + * @debug_node: DebugFS node for this clk. + * @ref: Reference count for structure lifetime management. + */ struct clk_core { const char *name; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0aa1efe78sm76186821cf.8.2025.08.12.07.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 07:40:52 -0700 (PDT) From: Brian Masney Date: Tue, 12 Aug 2025 10:40:32 -0400 Subject: [PATCH v3 2/9] clk: test: introduce clk_dummy_rate_mhz() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-clk-tests-docs-v3-2-054aed58dcd3@redhat.com> References: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> In-Reply-To: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755009649; l=1196; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=/B24jKgY1eYxf812cHNT9gVhTnmgGeQi+I8gZG7p4+k=; b=Yw4rGAFhMHmhnXH7wLnB9dvYYoAVL5j+A7SIbu0eCs1NsVZ82Zj7a89QGc6B2urIhCODHr6bL FFF7iXoEBOfDGqrgVyFbIT1FDeTZoBfbiDNSypgylL5OWhHcl5ivR8I X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Some of the mock tests care about the relationship between two different rates to ensure that functionality in the clk core is exercised when the parent rate is negotiated by using specific rates. Introduce clk_dummy_rate_mhz() to improve readability. Change the DUMMY_CLOCK_* rate constants over to use this. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index a268d7b5d4cb28ec1f029f828c31107f8e130556..fafa736ca32144a2feae75a8d64= 1abca3162d42d 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -21,9 +21,10 @@ =20 static const struct clk_ops empty_clk_ops =3D { }; =20 -#define DUMMY_CLOCK_INIT_RATE (42 * 1000 * 1000) -#define DUMMY_CLOCK_RATE_1 (142 * 1000 * 1000) -#define DUMMY_CLOCK_RATE_2 (242 * 1000 * 1000) +#define clk_dummy_rate_mhz(rate) ((rate) * 1000 * 1000) +#define DUMMY_CLOCK_INIT_RATE clk_dummy_rate_mhz(42) +#define DUMMY_CLOCK_RATE_1 clk_dummy_rate_mhz(142) +#define DUMMY_CLOCK_RATE_2 clk_dummy_rate_mhz(242) =20 struct clk_dummy_context { struct clk_hw hw; --=20 2.50.1 From nobody Sat Oct 4 20:57:10 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2AB12F5305 for ; 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Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index fafa736ca32144a2feae75a8d641abca3162d42d..61668fcd7203c4cef9f22b8c0c5= bb5a50d331f53 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -137,6 +137,48 @@ static const struct clk_ops clk_dummy_single_parent_op= s =3D { .get_parent =3D clk_dummy_single_get_parent, }; =20 +// 4 ought to be enough for anybody +#define CLK_DUMMY_DIV_WIDTH 4 +#define CLK_DUMMY_DIV_FLAGS (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLO= SEST) + +struct clk_dummy_div { + struct clk_hw hw; + unsigned int div; +}; + +static unsigned long clk_dummy_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + + return divider_recalc_rate(hw, parent_rate, div->div, NULL, + CLK_DUMMY_DIV_FLAGS, CLK_DUMMY_DIV_WIDTH); +} + +static long clk_dummy_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return divider_round_rate(hw, rate, parent_rate, NULL, + CLK_DUMMY_DIV_WIDTH, CLK_DUMMY_DIV_FLAGS); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0aa1efe78sm76186821cf.8.2025.08.12.07.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 07:40:59 -0700 (PDT) From: Brian Masney Date: Tue, 12 Aug 2025 10:40:34 -0400 Subject: [PATCH v3 4/9] clk: test: introduce test suite for sibling rate changes on a divider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-clk-tests-docs-v3-4-054aed58dcd3@redhat.com> References: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> In-Reply-To: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755009649; l=6637; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=vyZW28lbH7FtzudF1QBo50QacGCE1YcnXyZjBOXhCNI=; b=xiP6mRmZepVnpwhapEW0RGWWNo6nO4GNFAUOg8HBW0CD0fhrHRDAC04qR50DGyjfwahOskDID 97VRfpO3AWdCDLWd7HJjOoGvJRgH+qWDwHMJpkVpRVSKY/Qid32cEY7 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a test suite that creates a parent with two divider-only children, and ensure that changing the rate of one child does not affect the rate of the sibling. Some of the tests are disabled until the underlying issue is fixed in the clk core. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 145 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 145 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 61668fcd7203c4cef9f22b8c0c5bb5a50d331f53..81095fd80b270c1fd5e73e90a2f= 36da0071d10a4 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -651,6 +651,150 @@ clk_multiple_parents_mux_test_suite =3D { .test_cases =3D clk_multiple_parents_mux_test_cases, }; =20 +struct clk_rate_change_sibling_div_div_context { + struct clk_dummy_context parent; + struct clk_dummy_div child1, child2; + struct clk *parent_clk, *child1_clk, *child2_clk; +}; + +static int clk_rate_change_sibling_div_div_test_init(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + test->priv =3D ctx; + + ctx->parent.hw.init =3D CLK_HW_INIT_NO_PARENT("parent", &clk_dummy_rate_o= ps, 0); + ctx->parent.rate =3D clk_dummy_rate_mhz(24); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->parent.hw); + if (ret) + return ret; + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->parent.hw, &clk_du= mmy_div_ops, + CLK_SET_RATE_PARENT); + ctx->child1.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ret; + + ctx->child2.hw.init =3D CLK_HW_INIT_HW("child2", &ctx->parent.hw, &clk_du= mmy_div_ops, + CLK_SET_RATE_PARENT); + ctx->child2.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child2.hw); + if (ret) + return ret; + + ctx->parent_clk =3D clk_hw_get_clk(&ctx->parent.hw, NULL); + ctx->child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->child2_clk =3D clk_hw_get_clk(&ctx->child2.hw, NULL); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), clk_dummy_rate_mhz(2= 4)); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), clk_dummy_rate_mhz(2= 4)); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), clk_dummy_rate_mhz(2= 4)); + + return 0; +} + +static void clk_rate_change_sibling_div_div_test_exit(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + + clk_put(ctx->parent_clk); + clk_put(ctx->child1_clk); + clk_put(ctx->child2_clk); +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT set + * and one requests a rate compatible with the existing parent rate, the p= arent and + * sibling rates are not affected. + */ +static void clk_test_rate_change_sibling_div_div_1(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + ret =3D clk_set_rate(ctx->child1_clk, clk_dummy_rate_mhz(6)); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), clk_dummy_rate_mhz(2= 4)); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), clk_dummy_rate_mhz(6= )); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 4); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), clk_dummy_rate_mhz(2= 4)); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is not affected. The requested child rate picks a parent r= ate + * that's compatible with both children. + */ +static void clk_test_rate_change_sibling_div_div_2(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + kunit_skip(test, "This needs to be fixed in the core."); + + ret =3D clk_set_rate(ctx->child1_clk, clk_dummy_rate_mhz(48)); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), clk_dummy_rate_mhz(4= 8)); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), clk_dummy_rate_mhz(4= 8)); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), clk_dummy_rate_mhz(2= 4)); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 2); +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is not affected. The requested child rates require a paren= t rate + * that neither child would initially pick. + */ +static void clk_test_rate_change_sibling_div_div_3(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + kunit_skip(test, "This needs to be fixed in the core."); + + ret =3D clk_set_rate(ctx->child1_clk, clk_dummy_rate_mhz(32)); + KUNIT_ASSERT_EQ(test, ret, 0); + + ret =3D clk_set_rate(ctx->child2_clk, clk_dummy_rate_mhz(48)); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), clk_dummy_rate_mhz(9= 6)); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), clk_dummy_rate_mhz(3= 2)); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 3); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), clk_dummy_rate_mhz(4= 8)); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 2); +} + +static struct kunit_case clk_rate_change_sibling_div_div_cases[] =3D { + KUNIT_CASE(clk_test_rate_change_sibling_div_div_1), + KUNIT_CASE(clk_test_rate_change_sibling_div_div_2), + KUNIT_CASE(clk_test_rate_change_sibling_div_div_3), + {} +}; + +/* + * Test suite that creates a parent with two divider-only children, and + * ensures that changing the rate of one child does not affect the rate + * of the other child. + */ +static struct kunit_suite clk_rate_change_sibling_div_div_test_suite =3D { + .name =3D "clk-rate-change-sibling-div-div", + .init =3D clk_rate_change_sibling_div_div_test_init, + .exit =3D clk_rate_change_sibling_div_div_test_exit, + .test_cases =3D clk_rate_change_sibling_div_div_cases, +}; + static int clk_orphan_transparent_multiple_parent_mux_test_init(struct kunit *test) { @@ -3591,6 +3735,7 @@ kunit_test_suites( &clk_leaf_mux_set_rate_parent_test_suite, &clk_test_suite, &clk_multiple_parents_mux_test_suite, + &clk_rate_change_sibling_div_div_test_suite, &clk_mux_no_reparent_test_suite, &clk_mux_notifier_test_suite, &clk_orphan_transparent_multiple_parent_mux_test_suite, --=20 2.50.1 From nobody Sat Oct 4 20:57:10 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E6FE2F5339 for ; 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Reviewed-by: Maxime Ripard Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 81095fd80b270c1fd5e73e90a2f36da0071d10a4..9ed887551cd9b4926075d85b30b= 6cdfc8d307ea6 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -179,6 +179,40 @@ static const struct clk_ops clk_dummy_div_ops =3D { .set_rate =3D clk_dummy_div_set_rate, }; =20 +struct clk_dummy_gate { + struct clk_hw hw; + bool enabled; +}; + +static int clk_dummy_gate_enable(struct clk_hw *hw) +{ + struct clk_dummy_gate *gate =3D container_of(hw, struct clk_dummy_gate, h= w); + + gate->enabled =3D true; + + return 0; +} + +static void clk_dummy_gate_disable(struct clk_hw *hw) +{ + struct clk_dummy_gate *gate =3D container_of(hw, struct clk_dummy_gate, h= w); + + gate->enabled =3D false; +} + +static int clk_dummy_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_dummy_gate *gate =3D container_of(hw, struct clk_dummy_gate, h= w); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0aa1efe78sm76186821cf.8.2025.08.12.07.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 07:41:02 -0700 (PDT) From: Brian Masney Date: Tue, 12 Aug 2025 10:40:36 -0400 Subject: [PATCH v3 6/9] clk: test: introduce test suite for sibling rate changes on a gate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-clk-tests-docs-v3-6-054aed58dcd3@redhat.com> References: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> In-Reply-To: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755009649; l=6817; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=1HCjF9b0ejjYW6k+GcOOU4iJhvsGJNM1EUbh1YteUW4=; b=jdSoFnEcL85yl309OP1iUg5iItDeZdqOO1hHWFuYSXRUYF7JPk4JW6QXUFySpH8IrevuUKJXa BCZgUBArooOAOUkPUDtTs1ehA9KkHZHqaQFKPAzkYos6kB2CjhdLv+4 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a test suite that creates a parent with two children: a divider and a gate. Ensure that changing the rate of one child does not affect the rate of the gate. Some of the tests are disabled until the relevant issue(s) are fixed in the clk core. This is also implemented as a parameterized kunit test since additional test variations will be added. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 155 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 155 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 9ed887551cd9b4926075d85b30b6cdfc8d307ea6..2e002f3154430e8cd4bafb5addc= 350798d4b02bb 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -829,6 +829,160 @@ static struct kunit_suite clk_rate_change_sibling_div= _div_test_suite =3D { .test_cases =3D clk_rate_change_sibling_div_div_cases, }; =20 +struct clk_test_rate_change_sibling_clk_ctx { + struct clk *parent_clk, *child1_clk, *child2_clk; +}; + +static void +clk_test_rate_change_sibling_clk_ctx_put(struct clk_test_rate_change_sibli= ng_clk_ctx *clk_ctx) +{ + clk_put(clk_ctx->parent_clk); + clk_put(clk_ctx->child1_clk); + clk_put(clk_ctx->child2_clk); +} + +struct clk_rate_change_sibling_div_gate_sibling_context { + struct clk_dummy_context parent; + struct clk_dummy_div child1; + struct clk_dummy_gate child2; + struct clk_test_rate_change_sibling_clk_ctx clk_ctx; +}; + +static struct clk_test_rate_change_sibling_clk_ctx * +clk_rate_change_sibling_div_gate_test_init(struct kunit *test) +{ + struct clk_rate_change_sibling_div_gate_sibling_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + test->priv =3D ctx; + + ctx->parent.hw.init =3D CLK_HW_INIT_NO_PARENT("parent", &clk_dummy_rate_o= ps, 0); + ctx->parent.rate =3D clk_dummy_rate_mhz(24); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->parent.hw); + if (ret) + return ERR_PTR(ret); + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->parent.hw, &clk_du= mmy_div_ops, + CLK_SET_RATE_PARENT); + ctx->child1.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ERR_PTR(ret); + + ctx->child2.hw.init =3D CLK_HW_INIT_HW("child2", &ctx->parent.hw, &clk_du= mmy_gate_ops, + CLK_SET_RATE_PARENT); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child2.hw); + if (ret) + return ERR_PTR(ret); + + ctx->clk_ctx.parent_clk =3D clk_hw_get_clk(&ctx->parent.hw, NULL); + ctx->clk_ctx.child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->clk_ctx.child2_clk =3D clk_hw_get_clk(&ctx->child2.hw, NULL); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->clk_ctx.parent_clk), clk_dummy_ra= te_mhz(24)); + + return &ctx->clk_ctx; +} + +struct clk_test_rate_change_sibling_test_case { + const char *desc; + struct clk_test_rate_change_sibling_clk_ctx *(*init)(struct kunit *test); +}; + +static struct clk_test_rate_change_sibling_test_case clk_test_rate_change_= sibling_test_cases[] =3D { + { + .desc =3D "div_gate", + .init =3D clk_rate_change_sibling_div_gate_test_init, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_test_rate_change_sibling_test_case, + clk_test_rate_change_sibling_test_cases, desc); + +/* + * Test that, for a parent with two children with CLK_SET_RATE_PARENT set = and + * one requests a rate change that requires a change to the parent rate, t= he + * sibling rates are not affected. + */ +static void clk_test_rate_change_sibling_1(struct kunit *test) +{ + struct clk_test_rate_change_sibling_test_case *testcase =3D + (struct clk_test_rate_change_sibling_test_case *) test->param_value; + struct clk_test_rate_change_sibling_clk_ctx *ctx; + int ret; + + kunit_skip(test, "This needs to be fixed in the core."); + + ctx =3D testcase->init(test); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), clk_dummy_rate_mhz(2= 4)); + + ret =3D clk_set_rate(ctx->child1_clk, clk_dummy_rate_mhz(48)); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_GE(test, clk_get_rate(ctx->parent_clk), clk_dummy_rate_mhz(4= 8)); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), clk_dummy_rate_mhz(4= 8)); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), clk_dummy_rate_mhz(2= 4)); + + clk_test_rate_change_sibling_clk_ctx_put(ctx); +} + +/* + * Test that, for a parent with two children with CLK_SET_RATE_PARENT set = where + * one requests an exclusive rate and the other requests a rate change that + * requires a change to the parent rate, the sibling rates are not affecte= d. + */ +static void clk_test_rate_change_sibling_2(struct kunit *test) +{ + struct clk_test_rate_change_sibling_test_case *testcase =3D + (struct clk_test_rate_change_sibling_test_case *)(test->param_value); + struct clk_test_rate_change_sibling_clk_ctx *ctx; + int ret; + + ctx =3D testcase->init(test); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ret =3D clk_rate_exclusive_get(ctx->child2_clk); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), clk_dummy_rate_mhz(2= 4)); + + ret =3D clk_set_rate(ctx->child1_clk, clk_dummy_rate_mhz(48)); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_GE(test, clk_get_rate(ctx->parent_clk), clk_dummy_rate_mhz(2= 4)); + /* child1 is rounded to the closest supported rate */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), clk_dummy_rate_mhz(2= 4)); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), clk_dummy_rate_mhz(2= 4)); + + clk_rate_exclusive_put(ctx->child2_clk); + + clk_test_rate_change_sibling_clk_ctx_put(ctx); +} + + +static struct kunit_case clk_rate_change_sibling_cases[] =3D { + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_1, + clk_test_rate_change_sibling_test_case_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_2, + clk_test_rate_change_sibling_test_case_gen_params), + {} +}; + +/* + * Test suite that creates a parent with two children, where the children = can + * be combinations of a divider, gate, and a mux. Ensure that changing the= rate + * of one child does affect the rate of the other child. + */ +static struct kunit_suite clk_rate_change_sibling_test_suite =3D { + .name =3D "clk-rate-change-sibling", + .test_cases =3D clk_rate_change_sibling_cases, +}; + static int clk_orphan_transparent_multiple_parent_mux_test_init(struct kunit *test) { @@ -3770,6 +3924,7 @@ kunit_test_suites( &clk_test_suite, &clk_multiple_parents_mux_test_suite, &clk_rate_change_sibling_div_div_test_suite, + &clk_rate_change_sibling_test_suite, &clk_mux_no_reparent_test_suite, &clk_mux_notifier_test_suite, &clk_orphan_transparent_multiple_parent_mux_test_suite, --=20 2.50.1 From nobody Sat Oct 4 20:57:10 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF9852EFDAC for ; Tue, 12 Aug 2025 14:41:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0aa1efe78sm76186821cf.8.2025.08.12.07.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 07:41:10 -0700 (PDT) From: Brian Masney Date: Tue, 12 Aug 2025 10:40:37 -0400 Subject: [PATCH v3 7/9] clk: test: introduce helper to create a mock mux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-clk-tests-docs-v3-7-054aed58dcd3@redhat.com> References: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> In-Reply-To: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755009649; l=7421; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=XHXNEFI9odB0IIoG8jChbqF/uj+50qUnXYV2Gp5unms=; b=g08sE/ZPUIcWigiq9gMMDGVozwCf9DVFr2Y7RbubTpS/IvY3INOf5roDMU6hCDonrKI96Tlg+ HtLYf/3OmNVC64Hj2VymeJrhDFyNEWoGlZwcFiGZnIQG9WbakfDQnth X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a helper to create a mock mux to reduce code duplication. This also changes it so that the relevant clk_hws are registered with the kunit framework. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 141 ++++++++++++++++++---------------------------= ---- 1 file changed, 52 insertions(+), 89 deletions(-) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 2e002f3154430e8cd4bafb5addc350798d4b02bb..c91de77a5b7a90396d9b4819ff9= 0087445316567 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -536,45 +536,64 @@ static struct kunit_suite clk_uncached_test_suite =3D= { .test_cases =3D clk_uncached_test_cases, }; =20 -static int -clk_multiple_parents_mux_test_init(struct kunit *test) -{ - struct clk_multiple_parent_ctx *ctx; - const char *parents[2] =3D { "parent-0", "parent-1"}; +static int clk_init_multiple_parent_ctx(struct kunit *test, + struct clk_multiple_parent_ctx *ctx, + const char *parent0_name, + unsigned long parent0_rate, + const char *parent1_name, + unsigned long parent1_rate, + const char *mux_name, int mux_flags, + const struct clk_ops *mux_ops) +{ + const struct clk_hw *parents[2]; int ret; =20 - ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return -ENOMEM; - test->priv =3D ctx; - - ctx->parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-0", + ctx->parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT(parent0_name, &clk_dummy_rate_ops, 0); - ctx->parents_ctx[0].rate =3D DUMMY_CLOCK_RATE_1; + ctx->parents_ctx[0].rate =3D parent0_rate; ret =3D clk_hw_register_kunit(test, NULL, &ctx->parents_ctx[0].hw); if (ret) return ret; =20 - ctx->parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-1", + ctx->parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT(parent1_name, &clk_dummy_rate_ops, 0); - ctx->parents_ctx[1].rate =3D DUMMY_CLOCK_RATE_2; + ctx->parents_ctx[1].rate =3D parent1_rate; ret =3D clk_hw_register_kunit(test, NULL, &ctx->parents_ctx[1].hw); if (ret) return ret; =20 - ctx->current_parent =3D 0; - ctx->hw.init =3D CLK_HW_INIT_PARENTS("test-mux", parents, - &clk_multiple_parents_mux_ops, - CLK_SET_RATE_PARENT); + parents[0] =3D &ctx->parents_ctx[0].hw; + parents[1] =3D &ctx->parents_ctx[1].hw; + ctx->hw.init =3D CLK_HW_INIT_PARENTS_HW(mux_name, parents, + mux_ops, mux_flags); ret =3D clk_hw_register_kunit(test, NULL, &ctx->hw); if (ret) return ret; =20 + ctx->current_parent =3D 0; + return 0; } =20 +static int +clk_multiple_parents_mux_test_init(struct kunit *test) +{ + struct clk_multiple_parent_ctx *ctx; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + test->priv =3D ctx; + + return clk_init_multiple_parent_ctx(test, ctx, + "parent-0", DUMMY_CLOCK_RATE_1, + "parent-1", DUMMY_CLOCK_RATE_2, + "test-mux", CLK_SET_RATE_PARENT, + &clk_multiple_parents_mux_ops); +} + /* * Test that for a clock with multiple parents, clk_get_parent() * actually returns the current one. @@ -2539,7 +2558,6 @@ static int clk_leaf_mux_set_rate_parent_test_init(struct kunit *test) { struct clk_leaf_mux_ctx *ctx; - const char *top_parents[2] =3D { "parent-0", "parent-1" }; int ret; =20 ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); @@ -2547,27 +2565,11 @@ clk_leaf_mux_set_rate_parent_test_init(struct kunit= *test) return -ENOMEM; test->priv =3D ctx; =20 - ctx->mux_ctx.parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-0", - &clk_dummy_rate_ops, - 0); - ctx->mux_ctx.parents_ctx[0].rate =3D DUMMY_CLOCK_RATE_1; - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[0].hw); - if (ret) - return ret; - - ctx->mux_ctx.parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-1", - &clk_dummy_rate_ops, - 0); - ctx->mux_ctx.parents_ctx[1].rate =3D DUMMY_CLOCK_RATE_2; - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[1].hw); - if (ret) - return ret; - - ctx->mux_ctx.current_parent =3D 0; - ctx->mux_ctx.hw.init =3D CLK_HW_INIT_PARENTS("test-mux", top_parents, - &clk_multiple_parents_mux_ops, - 0); - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.hw); + ret =3D clk_init_multiple_parent_ctx(test, &ctx->mux_ctx, + "parent-0", DUMMY_CLOCK_RATE_1, + "parent-1", DUMMY_CLOCK_RATE_2, + "test-mux", 0, + &clk_multiple_parents_mux_ops); if (ret) return ret; =20 @@ -2755,7 +2757,6 @@ static int clk_mux_notifier_callback(struct notifier_= block *nb, static int clk_mux_notifier_test_init(struct kunit *test) { struct clk_mux_notifier_ctx *ctx; - const char *top_parents[2] =3D { "parent-0", "parent-1" }; int ret; =20 ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); @@ -2766,27 +2767,11 @@ static int clk_mux_notifier_test_init(struct kunit = *test) init_waitqueue_head(&ctx->pre_rate_change.wq); init_waitqueue_head(&ctx->post_rate_change.wq); =20 - ctx->mux_ctx.parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-0", - &clk_dummy_rate_ops, - 0); - ctx->mux_ctx.parents_ctx[0].rate =3D DUMMY_CLOCK_RATE_1; - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[0].hw); - if (ret) - return ret; - - ctx->mux_ctx.parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-1", - &clk_dummy_rate_ops, - 0); - ctx->mux_ctx.parents_ctx[1].rate =3D DUMMY_CLOCK_RATE_2; - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[1].hw); - if (ret) - return ret; - - ctx->mux_ctx.current_parent =3D 0; - ctx->mux_ctx.hw.init =3D CLK_HW_INIT_PARENTS("test-mux", top_parents, - &clk_multiple_parents_mux_ops, - 0); - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.hw); + ret =3D clk_init_multiple_parent_ctx(test, &ctx->mux_ctx, + "parent-0", DUMMY_CLOCK_RATE_1, + "parent-1", DUMMY_CLOCK_RATE_2, + "test-mux", 0, + &clk_multiple_parents_mux_ops); if (ret) return ret; =20 @@ -2869,39 +2854,17 @@ static int clk_mux_no_reparent_test_init(struct kunit *test) { struct clk_multiple_parent_ctx *ctx; - const char *parents[2] =3D { "parent-0", "parent-1"}; - int ret; =20 ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); if (!ctx) return -ENOMEM; test->priv =3D ctx; =20 - ctx->parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-0", - &clk_dummy_rate_ops, - 0); - ctx->parents_ctx[0].rate =3D DUMMY_CLOCK_RATE_1; - ret =3D clk_hw_register(NULL, &ctx->parents_ctx[0].hw); - if (ret) - return ret; - - ctx->parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-1", - &clk_dummy_rate_ops, - 0); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0aa1efe78sm76186821cf.8.2025.08.12.07.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 07:41:11 -0700 (PDT) From: Brian Masney Date: Tue, 12 Aug 2025 10:40:38 -0400 Subject: [PATCH v3 8/9] clk: test: introduce test variation for sibling rate changes on a mux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-clk-tests-docs-v3-8-054aed58dcd3@redhat.com> References: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> In-Reply-To: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755009649; l=2563; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=IUzDle4gQB8Xk0bxNLtfHL2sLNitV0rVkDxOnQwk0ls=; b=qDeH4KgI9d/t57bzy5StIb5ffHemwEbChn/GxrH3K7AeP8PcRx6fvRik7/HOwF9tbWMLkxdL8 S8oje3gdV1TAabkL5VvIMZchYTHFAoHW3W6BSIo3OVTOHjVOngomwdf X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a test variation that creates a parent with two children: a divider and a mux. Ensure that changing the rate of the divider does not affect the rate of the mux. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index c91de77a5b7a90396d9b4819ff90087445316567..f1c43b5004057eccd0591f17d62= 5c549d9eecc78 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -906,6 +906,47 @@ clk_rate_change_sibling_div_gate_test_init(struct kuni= t *test) return &ctx->clk_ctx; } =20 +struct clk_rate_change_sibling_div_mux_sibling_context { + struct clk_dummy_div child1; + struct clk_multiple_parent_ctx child2_mux; + struct clk_test_rate_change_sibling_clk_ctx clk_ctx; +}; + +static struct clk_test_rate_change_sibling_clk_ctx * +clk_rate_change_sibling_div_mux_test_init(struct kunit *test) +{ + struct clk_rate_change_sibling_div_mux_sibling_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + test->priv =3D ctx; + + ret =3D clk_init_multiple_parent_ctx(test, &ctx->child2_mux, + "parent0", clk_dummy_rate_mhz(24), + "parent1", clk_dummy_rate_mhz(48), + "child2", CLK_SET_RATE_NO_REPARENT, + &clk_multiple_parents_mux_ops); + if (ret) + return ERR_PTR(ret); + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->child2_mux.parents= _ctx[0].hw, + &clk_dummy_div_ops, CLK_SET_RATE_PARENT); + ctx->child1.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ERR_PTR(ret); + + KUNIT_ASSERT_EQ(test, ret, 0); + + ctx->clk_ctx.parent_clk =3D clk_hw_get_clk(&ctx->child2_mux.parents_ctx[0= ].hw, NULL); + ctx->clk_ctx.child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->clk_ctx.child2_clk =3D clk_hw_get_clk(&ctx->child2_mux.hw, NULL); + + return &ctx->clk_ctx; +} + struct clk_test_rate_change_sibling_test_case { const char *desc; struct clk_test_rate_change_sibling_clk_ctx *(*init)(struct kunit *test); @@ -916,6 +957,10 @@ static struct clk_test_rate_change_sibling_test_case c= lk_test_rate_change_siblin .desc =3D "div_gate", .init =3D clk_rate_change_sibling_div_gate_test_init, }, + { + .desc =3D "div_mux", + .init =3D clk_rate_change_sibling_div_mux_test_init, + }, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0aa1efe78sm76186821cf.8.2025.08.12.07.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Aug 2025 07:41:14 -0700 (PDT) From: Brian Masney Date: Tue, 12 Aug 2025 10:40:39 -0400 Subject: [PATCH v3 9/9] clk: test: introduce test variation for sibling rate changes on a gate/mux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250812-clk-tests-docs-v3-9-054aed58dcd3@redhat.com> References: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> In-Reply-To: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755009649; l=2537; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=sDM4TxN8ShOb8aBv+Z7HrYy5822cwlDrWFqdSR4OZKE=; b=r5FvK3WTbTODfyrV1UUlVrGiqX+hXi0edFBQWx7+UwkPASXGz05BP0ajvIkJT4VYwtDbP4lQL wxpW1BxVD+QDZQ4h48aqXcxF0q1N9kAFLxpJrPRt67SoIj70Y7oYpSu X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a test variation that creates a parent with two children: a gate and a mux. Ensure that changing the rate of the gate does not affect the rate of the mux. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index f1c43b5004057eccd0591f17d625c549d9eecc78..abc0e4dd1b79e7d54673d3eeae7= c95b0d1d61e33 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -947,6 +947,46 @@ clk_rate_change_sibling_div_mux_test_init(struct kunit= *test) return &ctx->clk_ctx; } =20 +struct clk_rate_change_sibling_gate_mux_sibling_context { + struct clk_dummy_gate child1; + struct clk_multiple_parent_ctx child2_mux; + struct clk_test_rate_change_sibling_clk_ctx clk_ctx; +}; + +static struct clk_test_rate_change_sibling_clk_ctx * +clk_rate_change_sibling_gate_mux_test_init(struct kunit *test) +{ + struct clk_rate_change_sibling_gate_mux_sibling_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + test->priv =3D ctx; + + ret =3D clk_init_multiple_parent_ctx(test, &ctx->child2_mux, + "parent0", clk_dummy_rate_mhz(24), + "parent1", clk_dummy_rate_mhz(48), + "child2", CLK_SET_RATE_NO_REPARENT, + &clk_multiple_parents_mux_ops); + if (ret) + return ERR_PTR(ret); + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->child2_mux.parents= _ctx[0].hw, + &clk_dummy_gate_ops, CLK_SET_RATE_PARENT); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ERR_PTR(ret); + + KUNIT_ASSERT_EQ(test, ret, 0); + + ctx->clk_ctx.parent_clk =3D clk_hw_get_clk(&ctx->child2_mux.parents_ctx[0= ].hw, NULL); + ctx->clk_ctx.child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->clk_ctx.child2_clk =3D clk_hw_get_clk(&ctx->child2_mux.hw, NULL); + + return &ctx->clk_ctx; +} + struct clk_test_rate_change_sibling_test_case { const char *desc; struct clk_test_rate_change_sibling_clk_ctx *(*init)(struct kunit *test); @@ -961,6 +1001,10 @@ static struct clk_test_rate_change_sibling_test_case = clk_test_rate_change_siblin .desc =3D "div_mux", .init =3D clk_rate_change_sibling_div_mux_test_init, }, + { + .desc =3D "gate_mux", + .init =3D clk_rate_change_sibling_gate_mux_test_init, + }, }; =20 KUNIT_ARRAY_PARAM_DESC(clk_test_rate_change_sibling_test_case, --=20 2.50.1