From nobody Sun Oct 5 01:47:25 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D3412E426A for ; Mon, 11 Aug 2025 18:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754936268; cv=none; b=FXjkKTwcap+5eCeuGdTUxRyItzDmickpBt3LQSw1p3+0/JVW/OvuDPUAAfJdzftb7yw9yNfU12By4ulk0FFr0SJy3z9S+esMmylSQh3E88Rp3Ga5dKwQHvZ1NlEArS5/jb/l4xIQIzPXGNiw0VNtxSTHC/4Ul7zm03OsFUTUK/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754936268; c=relaxed/simple; bh=2hBTZeKFe7at29k2ndEbuBEXfv3Umu+oVEsKx4SAiMk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uJ7uy4a1j6dh46EQPGnGCZpXAP9wLL0M7U6GSGQX1Y+8xz/G38QbwjAWhY0jdAdQDfwf5r2ZufmQ1NNSz4lF5h4kBm5Vx5p/LZdDwSR9cJ6QQ9BjKHq5zdJ+kksxqSjBJzqlhH93VhPWTf5UPrp5LeVgQALNAbxiczTKKfauP6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Wx/f0bgu; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Wx/f0bgu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754936267; x=1786472267; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2hBTZeKFe7at29k2ndEbuBEXfv3Umu+oVEsKx4SAiMk=; b=Wx/f0bgu3gvQT1xrtVlUCwwOpBLrd3S49ZUz9Roz5ckM6OSyOlHTXPBh pO7UEPk6FU+aZK5ATx2ooFC4gq9B1/Hj0ngHfXJ+5I3Qa3GRWOa8KyHos es+FQHJhabtXgn77iIzEtB5Ug/ZkZkSeRMeHJqe8uSxhR/tHdwSLWMtU8 vxR0jE+FBpQ1XIuTSgitJyZccaszW+zJ2dTBiossEFaAoPLNpJKfjc/X0 HnAwJK9VwIQvvC5h6szzZNQaYMAWX+XaGndcO/wp3ELEKDZV22D+eCqSB 9C5pXWADcNCNy7+aXhvnwQ2h/Jaqg8kcVRZ41TcScj7vuvyzDp3o3aJg8 A==; X-CSE-ConnectionGUID: 2SAdUkdGSr2eSUlRco3rqA== X-CSE-MsgGUID: f4Nn8eHlSXyratUYC3RF2Q== X-IronPort-AV: E=McAfee;i="6800,10657,11518"; a="68277473" X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="68277473" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2025 11:17:27 -0700 X-CSE-ConnectionGUID: 7XrgbcmkS0SeVwsbGWYyFw== X-CSE-MsgGUID: dw/XFai1QpGTP4zAi9wSBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="196825683" Received: from puneetse-mobl.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.221.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2025 11:17:25 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Anil Keshavamurthy , Chen Yu Cc: x86@kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v8 21/32] x86,fs/resctrl: Add architectural event pointer Date: Mon, 11 Aug 2025 11:16:55 -0700 Message-ID: <20250811181709.6241-22-tony.luck@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250811181709.6241-1-tony.luck@intel.com> References: <20250811181709.6241-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The resctrl file system layer passes the domain, RMID, and event id to resctrl_arch_rmid_read() to fetch an event counter. For some resources this is not enough information to efficiently access the counter. Fetching a telemetry event counter requires additional information that is private to the architecture, for example, the offset into MMIO space from where counter should be read. Add mon_evt::arch_priv void pointer. Architecture code can initialize this when marking each event enabled. File system code passes this pointer to resctrl_arch_rmid_read(). Suggested-by: Reinette Chatre Signed-off-by: Tony Luck --- include/linux/resctrl.h | 7 +++++-- fs/resctrl/internal.h | 4 ++++ arch/x86/kernel/cpu/resctrl/core.c | 6 +++--- arch/x86/kernel/cpu/resctrl/monitor.c | 2 +- fs/resctrl/monitor.c | 14 ++++++++++---- 5 files changed, 23 insertions(+), 10 deletions(-) diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 61c73772a177..d729e988a475 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -384,7 +384,7 @@ int resctrl_arch_update_domains(struct rdt_resource *r,= u32 closid); #define MAX_BINARY_BITS 27 =20 void resctrl_enable_mon_event(enum resctrl_event_id eventid, bool any_cpu, - unsigned int binary_bits); + unsigned int binary_bits, void *arch_priv); =20 bool resctrl_is_mon_event_enabled(enum resctrl_event_id eventid); =20 @@ -479,6 +479,9 @@ void resctrl_arch_pre_mount(void); * only. * @rmid: rmid of the counter to read. * @eventid: eventid to read, e.g. L3 occupancy. + * @arch_priv: Architecture private data for this event. + * The @arch_priv provided by the architecture via + * resctrl_enable_mon_event(). * @val: result of the counter read in bytes. * @arch_mon_ctx: An architecture specific value from * resctrl_arch_mon_ctx_alloc(), for MPAM this identifies @@ -496,7 +499,7 @@ void resctrl_arch_pre_mount(void); */ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *= hdr, u32 closid, u32 rmid, enum resctrl_event_id eventid, - u64 *val, void *arch_mon_ctx); + void *arch_priv, u64 *val, void *arch_mon_ctx); =20 /** * resctrl_arch_rmid_read_context_check() - warn about invalid contexts diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index b16e2fc42b3f..9c1f821279bb 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -62,6 +62,9 @@ static inline struct rdt_fs_context *rdt_fc2context(struc= t fs_context *fc) * @binary_bits: number of fixed-point binary bits from architecture, * only valid if @is_floating_point is true * @enabled: true if the event is enabled + * @arch_priv: Architecture private data for this event. + * The @arch_priv provided by the architecture via + * resctrl_enable_mon_event(). */ struct mon_evt { enum resctrl_event_id evtid; @@ -72,6 +75,7 @@ struct mon_evt { bool is_floating_point; unsigned int binary_bits; bool enabled; + void *arch_priv; }; =20 extern struct mon_evt mon_event_all[QOS_NUM_EVENTS]; diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 58756d216fe8..6f455454f38d 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -910,15 +910,15 @@ static __init bool get_rdt_mon_resources(void) bool ret =3D false; =20 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { - resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, false, 0); + resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, false, 0, NULL); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { - resctrl_enable_mon_event(QOS_L3_MBM_TOTAL_EVENT_ID, false, 0); + resctrl_enable_mon_event(QOS_L3_MBM_TOTAL_EVENT_ID, false, 0, NULL); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) { - resctrl_enable_mon_event(QOS_L3_MBM_LOCAL_EVENT_ID, false, 0); + resctrl_enable_mon_event(QOS_L3_MBM_LOCAL_EVENT_ID, false, 0, NULL); ret =3D true; } =20 diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 043f777378a6..185b203f6321 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -219,7 +219,7 @@ static u64 mbm_overflow_count(u64 prev_msr, u64 cur_msr= , unsigned int width) =20 int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *= hdr, u32 unused, u32 rmid, enum resctrl_event_id eventid, - u64 *val, void *ignored) + void *arch_priv, u64 *val, void *ignored) { int cpu =3D cpumask_any(&hdr->cpu_mask); struct rdt_hw_l3_mon_domain *hw_dom; diff --git a/fs/resctrl/monitor.c b/fs/resctrl/monitor.c index 879263db8fa3..40c66caf299d 100644 --- a/fs/resctrl/monitor.c +++ b/fs/resctrl/monitor.c @@ -137,9 +137,11 @@ void __check_limbo(struct rdt_l3_mon_domain *d, bool f= orce_free) struct rmid_entry *entry; u32 idx, cur_idx =3D 1; void *arch_mon_ctx; + void *arch_priv; bool rmid_dirty; u64 val =3D 0; =20 + arch_priv =3D mon_event_all[QOS_L3_OCCUP_EVENT_ID].arch_priv; arch_mon_ctx =3D resctrl_arch_mon_ctx_alloc(r, QOS_L3_OCCUP_EVENT_ID); if (IS_ERR(arch_mon_ctx)) { pr_warn_ratelimited("Failed to allocate monitor context: %ld", @@ -160,7 +162,7 @@ void __check_limbo(struct rdt_l3_mon_domain *d, bool fo= rce_free) =20 entry =3D __rmid_entry(idx); if (resctrl_arch_rmid_read(r, &d->hdr, entry->closid, entry->rmid, - QOS_L3_OCCUP_EVENT_ID, &val, + QOS_L3_OCCUP_EVENT_ID, arch_priv, &val, arch_mon_ctx)) { rmid_dirty =3D true; } else { @@ -411,7 +413,8 @@ static int __mon_event_count(u32 closid, u32 rmid, stru= ct rmid_read *rr) if (rr->hdr) { /* Single domain. */ rr->err =3D resctrl_arch_rmid_read(rr->r, rr->hdr, closid, rmid, - rr->evt->evtid, &tval, rr->arch_mon_ctx); + rr->evt->evtid, rr->evt->arch_priv, + &tval, rr->arch_mon_ctx); if (rr->err) return rr->err; =20 @@ -434,7 +437,8 @@ static int __mon_event_count(u32 closid, u32 rmid, stru= ct rmid_read *rr) if (d->ci_id !=3D rr->ci_id) continue; err =3D resctrl_arch_rmid_read(rr->r, &d->hdr, closid, rmid, - rr->evt->evtid, &tval, rr->arch_mon_ctx); + rr->evt->evtid, rr->evt->arch_priv, + &tval, rr->arch_mon_ctx); if (!err) { rr->val +=3D tval; ret =3D 0; @@ -906,7 +910,8 @@ struct mon_evt mon_event_all[QOS_NUM_EVENTS] =3D { MON_EVENT(PMT_EVENT_UOPS_RETIRED, "uops_retired", RDT_RESOURCE_PERF_PKG= , false), }; =20 -void resctrl_enable_mon_event(enum resctrl_event_id eventid, bool any_cpu,= unsigned int binary_bits) +void resctrl_enable_mon_event(enum resctrl_event_id eventid, bool any_cpu, + unsigned int binary_bits, void *arch_priv) { if (WARN_ON_ONCE(eventid < QOS_FIRST_EVENT || eventid >=3D QOS_NUM_EVENTS= || binary_bits > MAX_BINARY_BITS)) @@ -922,6 +927,7 @@ void resctrl_enable_mon_event(enum resctrl_event_id eve= ntid, bool any_cpu, unsig =20 mon_event_all[eventid].any_cpu =3D any_cpu; mon_event_all[eventid].binary_bits =3D binary_bits; + mon_event_all[eventid].arch_priv =3D arch_priv; mon_event_all[eventid].enabled =3D true; } =20 --=20 2.50.1