From nobody Sun Oct 5 02:09:47 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACA511991D4 for ; Tue, 12 Aug 2025 05:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754974932; cv=none; b=HI58E4+GnJTX2d4OYxMrvycjOofFdYYwwmG/1YEc9uplPhGZcAQ50YX/5n6ritbMLiOTpp+84ac5fs2Sq9k2DMDTgZ4GlqRdqljUD0gcQMc++cPly2GpqtBVuH2P1t+FoMN3HiVbyz5Z5uWd8cImn1nVDt25O2mFbUh/42Ct4YU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754974932; c=relaxed/simple; bh=6GNeoJ86xp9/K5fVFW+3oK5Y3XHOLyG/PGdbDUgut3Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=Wz0cOxfO09o7u+4zH+AR0X0yTAe3X1U19GIzMrVxGyER6YWicMgVHkQjtB43kf4zNk0iHVHH8Arkk153qUWaQJ27cHF8LeQLVeVR2tSaUVaC10+W0tKB9kIv6OSgDBhCrJLp1PWcyE5zSmZZXFZtS72b6ClVbk/aARIFp6bp4Gg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=WwFcECIc; arc=none smtp.client-ip=203.254.224.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="WwFcECIc" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout2.samsung.com (KnoxPortal) with ESMTP id 20250812050206epoutp027838671d4fe55208f2da711495e0f311~a7GXXLjlu1104311043epoutp02R for ; Tue, 12 Aug 2025 05:02:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20250812050206epoutp027838671d4fe55208f2da711495e0f311~a7GXXLjlu1104311043epoutp02R DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1754974927; bh=g+OIPYfZeep00nAL2s8vJenk/L6kOEW7w/EsYvIr9eI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WwFcECIcdheeUxpBWxjjNUmJEO1xi56yGg2a/8lub6aL4LGUjv2ddQvDXHqq8LtOv g1QEN3JTlxeRdvVsrutkIUlO3cDABhT0MoUsxdOnTApMIVWrBFm0dJhXWufix1ctwR 9yY74ZQBq7msWCwNDSTaRDwxYZmxpCq76Jrkf/PY= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250812050205epcas5p3ec1d0180b5df6900b1fee304310b01cc~a7GWSXLMn2902829028epcas5p3A; Tue, 12 Aug 2025 05:02:05 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.94]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4c1K9m5Y4Dz2SSKd; Tue, 12 Aug 2025 05:02:04 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250811154659epcas5p1874791c7ce4e26a2bd36e24a7be55f51~awQIcaq_x2692426924epcas5p10; Mon, 11 Aug 2025 15:46:59 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154656epsmtip1d9d756f77820130ac933dbc336675fc2~awQF0WLN42450724507epsmtip1v; Mon, 11 Aug 2025 15:46:56 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 02/12] PCI: exynos: Change macro names to exynos specific Date: Mon, 11 Aug 2025 21:16:28 +0530 Message-ID: <20250811154638.95732-3-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154659epcas5p1874791c7ce4e26a2bd36e24a7be55f51 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154659epcas5p1874791c7ce4e26a2bd36e24a7be55f51 References: <20250811154638.95732-1-shradha.t@samsung.com> Prefix macro names in exynos file with the term "EXYNOS" as the current macro names seem to be generic to PCIe. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 112 ++++++++++++------------ 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index f9140d1f1d19..30d12ff9b0c6 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -26,28 +26,28 @@ #define to_exynos_pcie(x) dev_get_drvdata((x)->dev) =20 /* PCIe ELBI registers */ -#define PCIE_IRQ_PULSE 0x000 -#define IRQ_INTA_ASSERT BIT(0) -#define IRQ_INTB_ASSERT BIT(2) -#define IRQ_INTC_ASSERT BIT(4) -#define IRQ_INTD_ASSERT BIT(6) -#define PCIE_IRQ_EN_PULSE 0x00c -#define PCIE_IRQ_EN_LEVEL 0x010 -#define PCIE_IRQ_EN_SPECIAL 0x014 -#define PCIE_SW_WAKE 0x018 -#define PCIE_BUS_EN BIT(1) -#define PCIE_CORE_RESET 0x01c -#define PCIE_CORE_RESET_ENABLE BIT(0) -#define PCIE_STICKY_RESET 0x020 -#define PCIE_NONSTICKY_RESET 0x024 -#define PCIE_APP_INIT_RESET 0x028 -#define PCIE_APP_LTSSM_ENABLE 0x02c -#define PCIE_ELBI_RDLH_LINKUP 0x074 -#define PCIE_ELBI_XMLH_LINKUP BIT(4) -#define PCIE_ELBI_LTSSM_ENABLE 0x1 -#define PCIE_ELBI_SLV_AWMISC 0x11c -#define PCIE_ELBI_SLV_ARMISC 0x120 -#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) +#define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_IRQ_INTA_ASSERT BIT(0) +#define EXYNOS_IRQ_INTB_ASSERT BIT(2) +#define EXYNOS_IRQ_INTC_ASSERT BIT(4) +#define EXYNOS_IRQ_INTD_ASSERT BIT(6) +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c +#define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 +#define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 +#define EXYNOS_PCIE_SW_WAKE 0x018 +#define EXYNOS_PCIE_BUS_EN BIT(1) +#define EXYNOS_PCIE_CORE_RESET 0x01c +#define EXYNOS_PCIE_CORE_RESET_ENABLE BIT(0) +#define EXYNOS_PCIE_STICKY_RESET 0x020 +#define EXYNOS_PCIE_NONSTICKY_RESET 0x024 +#define EXYNOS_PCIE_APP_INIT_RESET 0x028 +#define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 +#define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 +#define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c +#define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 +#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 struct exynos_pcie { struct dw_pcie pci; @@ -71,49 +71,49 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exyn= os_pcie *ep, bool on) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_AWMISC); if (on) - val |=3D PCIE_ELBI_SLV_DBI_ENABLE; + val |=3D EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &=3D ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); + val &=3D ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_AWMISC); } =20 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool o= n) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_ARMISC); if (on) - val |=3D PCIE_ELBI_SLV_DBI_ENABLE; + val |=3D EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &=3D ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); + val &=3D ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_ARMISC); } =20 static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val &=3D ~PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val &=3D ~EXYNOS_PCIE_CORE_RESET_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); } =20 static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val |=3D PCIE_CORE_RESET_ENABLE; + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val |=3D EXYNOS_PCIE_CORE_RESET_ENABLE; =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_APP_INIT_RESET); } =20 static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -121,21 +121,21 @@ static int exynos_pcie_start_link(struct dw_pcie *pci) struct exynos_pcie *ep =3D to_exynos_pcie(pci); u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); - val &=3D ~PCIE_BUS_EN; - exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_SW_WAKE); + val &=3D ~EXYNOS_PCIE_BUS_EN; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_SW_WAKE); =20 /* assert LTSSM enable */ - exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, - PCIE_APP_LTSSM_ENABLE); + exynos_pcie_writel(ep->elbi_base, EXYNOS_PCIE_ELBI_LTSSM_ENABLE, + EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } =20 static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) { - u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); + u32 val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_IRQ_PULSE); =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_PULSE); } =20 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -148,12 +148,12 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, v= oid *arg) =20 static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) { - u32 val =3D IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; + u32 val =3D EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | + EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } =20 static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -210,9 +210,9 @@ static struct pci_ops exynos_pci_ops =3D { static bool exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep =3D to_exynos_pcie(pci); - u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); + u32 val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_RDLH_LINKUP= ); =20 - return val & PCIE_ELBI_XMLH_LINKUP; + return val & EXYNOS_PCIE_ELBI_XMLH_LINKUP; } =20 static int exynos_pcie_host_init(struct dw_pcie_rp *pp) --=20 2.49.0